soc/amd/genoa: Deal with memory map for 32M or larger flash

Only the lower half of the flash gets memory mapped below 4G in the
current setup.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: Iffe5c17a50f3254411a4847c7e635ce0fd282fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76499
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2023-07-13 14:02:42 +02:00
committed by Felix Held
parent 8f1c707060
commit e4eba133cc
3 changed files with 34 additions and 0 deletions

View File

@@ -15,6 +15,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select UNKNOWN_TSC_RATE
select X86_CUSTOM_BOOTMEDIA
config USE_EXP_X86_64_SUPPORT
default y

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@@ -1,6 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOC_AMD_GENOA),y)
all-y += mmap_boot.c
bootblock-y += early_fch.c
romstage-y += romstage.c

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@@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <boot_device.h>
#include <endian.h>
#include <spi_flash.h>
#if CONFIG_ROM_SIZE >= (16 * MiB)
#define ROM_SIZE (16 * MiB)
#else
#define ROM_SIZE CONFIG_ROM_SIZE
#endif
/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
#define rom_base ((void *)(uintptr_t)(0x100000000ULL-ROM_SIZE))
static const struct mem_region_device boot_dev =
MEM_REGION_DEV_RO_INIT(rom_base, ROM_SIZE);
const struct region_device *boot_device_ro(void)
{
return &boot_dev.rdev;
}
uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
{
table->flash_base = 0;
table->host_base = (uint32_t)(uintptr_t)rom_base;
table->size = ROM_SIZE;
return 1;
}