pci: Move inline PCI functions to pci_ops.h

Move inline function where they belong to. Fixes compilation
on non x86 platforms.

Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/include/arch/io.h

@@ -427,63 +427,4 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq)
 }
 
 #endif /* __SIMPLE_DEVICE__ */
-
-#ifndef __SIMPLE_DEVICE__
-#include <device/pci_ops.h>
-#endif
-
-static inline __attribute__((always_inline))
-void pci_or_config8(device_t dev, unsigned int where, u8 ormask)
-{
-	u8 value = pci_read_config8(dev, where);
-	pci_write_config8(dev, where, value | ormask);
-}
-
-static inline __attribute__((always_inline))
-void pci_or_config16(device_t dev, unsigned int where, u16 ormask)
-{
-	u16 value = pci_read_config16(dev, where);
-	pci_write_config16(dev, where, value | ormask);
-}
-
-static inline __attribute__((always_inline))
-void pci_or_config32(device_t dev, unsigned int where, u32 ormask)
-{
-	u32 value = pci_read_config32(dev, where);
-	pci_write_config32(dev, where, value | ormask);
-}
-
-static inline __attribute__((always_inline))
-void pci_update_config8(device_t dev, int reg, u8 mask, u8 or)
-{
-	u8 reg8;
-
-	reg8 = pci_read_config8(dev, reg);
-	reg8 &= mask;
-	reg8 |= or;
-	pci_write_config8(dev, reg, reg8);
-}
-
-static inline __attribute__((always_inline))
-void pci_update_config16(device_t dev, int reg, u16 mask, u16 or)
-{
-	u16 reg16;
-
-	reg16 = pci_read_config16(dev, reg);
-	reg16 &= mask;
-	reg16 |= or;
-	pci_write_config16(dev, reg, reg16);
-}
-
-static inline __attribute__((always_inline))
-void pci_update_config32(device_t dev, int reg, u32 mask, u32 or)
-{
-	u32 reg32;
-
-	reg32 = pci_read_config32(dev, reg);
-	reg32 &= mask;
-	reg32 |= or;
-	pci_write_config32(dev, reg, reg32);
-}
-
 #endif

src/cpu/intel/haswell/smmrelocate.c

@@ -17,6 +17,7 @@
 #include <string.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>

src/device/pciexp_device.c

@@ -19,6 +19,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <device/pciexp.h>
 
 unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)

src/include/device/device.h

@@ -19,6 +19,7 @@ struct device;
 #ifndef __SIMPLE_DEVICE__
 typedef struct device *device_t;
 #endif
+#include <arch/io.h>
 
 struct pci_operations;
 struct pci_bus_operations;

src/include/device/pci_ops.h

@@ -15,4 +15,62 @@ void pci_write_config32(struct device *dev, unsigned int where, u32 val);
 
 #endif
 
+/*
+ * Use device_t here as the functions are to be used with either
+ * __SIMPLE_DEVICE__ defined or undefined.
+ */
+static inline __attribute__((always_inline))
+void pci_or_config8(device_t dev, unsigned int where, u8 ormask)
+{
+	u8 value = pci_read_config8(dev, where);
+	pci_write_config8(dev, where, value | ormask);
+}
+
+static inline __attribute__((always_inline))
+void pci_or_config16(device_t dev, unsigned int where, u16 ormask)
+{
+	u16 value = pci_read_config16(dev, where);
+	pci_write_config16(dev, where, value | ormask);
+}
+
+static inline __attribute__((always_inline))
+void pci_or_config32(device_t dev, unsigned int where, u32 ormask)
+{
+	u32 value = pci_read_config32(dev, where);
+	pci_write_config32(dev, where, value | ormask);
+}
+
+static inline __attribute__((always_inline))
+void pci_update_config8(device_t dev, int reg, u8 mask, u8 or)
+{
+	u8 reg8;
+
+	reg8 = pci_read_config8(dev, reg);
+	reg8 &= mask;
+	reg8 |= or;
+	pci_write_config8(dev, reg, reg8);
+}
+
+static inline __attribute__((always_inline))
+void pci_update_config16(device_t dev, int reg, u16 mask, u16 or)
+{
+	u16 reg16;
+
+	reg16 = pci_read_config16(dev, reg);
+	reg16 &= mask;
+	reg16 |= or;
+	pci_write_config16(dev, reg, reg16);
+}
+
+static inline __attribute__((always_inline))
+void pci_update_config32(device_t dev, int reg, u32 mask, u32 or)
+{
+	u32 reg32;
+
+	reg32 = pci_read_config32(dev, reg);
+	reg32 &= mask;
+	reg32 |= or;
+	pci_write_config32(dev, reg, reg32);
+}
+
 #endif /* PCI_OPS_H */

src/mainboard/asus/maximus_iv_gene-z/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/dram/ddr3.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>

src/mainboard/gizmosphere/gizmo/mainboard.c

@@ -19,6 +19,7 @@
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 
 #include <southbridge/amd/sb800/sb800.h>
 #include "SBPLATFORM.h"

src/mainboard/google/auron/variant.h

@@ -15,6 +15,7 @@
 #define VARIANT_H
 
 #include <arch/io.h>
+#include <device/device.h>
 #include <soc/romstage.h>
 
 int variant_smbios_data(device_t dev, int *handle, unsigned long *current);

src/mainboard/lenovo/x60/mainboard.c

@@ -18,6 +18,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/device.h>
+#include <device/pci_ops.h>
 #include <arch/io.h>
 #include <ec/acpi/ec.h>
 #include <northbridge/intel/i945/i945.h>

src/northbridge/amd/agesa/family14/state_machine.c

@@ -20,6 +20,7 @@
 #include <cbmem.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <halt.h>
 #include <reset.h>
 #include <smp/node.h>

src/northbridge/intel/fsp_sandybridge/finalize.c

@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <stdlib.h>
+#include <device/pci_ops.h>
 #include "northbridge.h"
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)

src/northbridge/intel/haswell/finalize.c

@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <stdlib.h>
+#include <device/pci_ops.h>
 #include "haswell.h"
 
 #define PCI_DEV_HSW PCI_DEV(0, 0, 0)

src/northbridge/intel/nehalem/finalize.c

@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <stdlib.h>
+#include <device/pci_ops.h>
 #include "nehalem.h"
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)

src/northbridge/intel/sandybridge/finalize.c

@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <stdlib.h>
+#include <device/pci_ops.h>
 #include "sandybridge.h"
 
 #define PCI_DEV_SNB PCI_DEV(0, 0, 0)

src/soc/amd/stoneyridge/cpu.c

@@ -21,6 +21,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/amd/amdfam15.h>
 #include <device/device.h>
+#include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
 #include <soc/northbridge.h>

src/soc/amd/stoneyridge/nb_util.c

@@ -15,6 +15,7 @@
 
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
+#include <device/pci_ops.h>
 
 uint32_t nb_ioapic_read(unsigned int index)
 {

src/soc/amd/stoneyridge/reset.c

@@ -18,6 +18,7 @@
 #include <reset.h>
 #include <soc/northbridge.h>
 #include <soc/pci_devs.h>
+#include <device/pci_ops.h>
 #include <soc/southbridge.h>
 
 /* Clear bits 5, 9 & 10, used to signal the reset type */

src/soc/amd/stoneyridge/tsc_freq.c

@@ -21,6 +21,7 @@
 #include <cpu/amd/amdfam15.h>
 #include <console/console.h>
 #include <soc/pci_devs.h>
+#include <device/pci_ops.h>
 
 unsigned long tsc_freq_mhz(void)
 {

src/soc/intel/apollolake/cse.c

@@ -20,6 +20,7 @@
 #include <fmap.h>
 #include <intelblocks/cse.h>
 #include <soc/pci_devs.h>
+#include <device/pci_ops.h>
 #include <stdint.h>
 #include <compiler.h>
 

src/soc/intel/broadwell/acpi.c

@@ -19,7 +19,7 @@
 #include <arch/io.h>
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
-#include <console/console.h>
+#include <device/pci_ops.h>
 #include <cpu/x86/smm.h>
 #include <console/console.h>
 #include <types.h>

src/soc/intel/broadwell/pcie.c

@@ -20,6 +20,7 @@
 #include <device/pciexp.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <soc/gpio.h>
 #include <soc/lpc.h>
 #include <soc/iobp.h>

src/soc/intel/broadwell/romstage/pch.c

@@ -17,6 +17,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <reg_script.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>

src/soc/intel/cannonlake/pmc.c

@@ -19,6 +19,7 @@
 #include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci_ops.h>
 #include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -16,6 +16,7 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>

src/soc/intel/common/block/gspi/gspi.c

@@ -21,6 +21,7 @@
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <intelblocks/gspi.h>
 #include <string.h>
 #include <timer.h>

src/soc/intel/common/block/pcie/pcie.c

@@ -18,6 +18,7 @@
 #include <device/pciexp.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 
 #define CACHE_LINE_SIZE	0x10
 /* Latency tolerance reporting, max non-snoop latency value 3.14ms */

src/soc/intel/common/block/pcr/pcr.c

@@ -17,6 +17,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <intelblocks/pcr.h>
+#include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <timer.h>

src/soc/intel/skylake/acpi.c

@@ -49,6 +49,7 @@
 #include <types.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <wrdd.h>
+#include <device/pci_ops.h>
 
 /*
  * List of suported C-states in this processor.

src/soc/intel/skylake/pmc.c

@@ -19,6 +19,7 @@
 #include <chip.h>
 #include <console/console.h>
 #include <device/device.h>
+#include <device/pci_ops.h>
 #include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>

src/soc/intel/skylake/systemagent.c

@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <delay.h>
 #include <device/device.h>
+#include <device/pci_ops.h>
 #include <intelblocks/systemagent.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>

src/soc/intel/skylake/vr_config.c

@@ -16,6 +16,7 @@
 
 #include <arch/io.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <fsp/api.h>
 #include <soc/ramstage.h>
 #include <soc/vr_config.h>

src/southbridge/intel/bd82x6x/early_pch_common.c

@@ -18,6 +18,7 @@
 #include <timestamp.h>
 #include <cpu/x86/tsc.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include "pch.h"
 #include <arch/acpi.h>
 #include <console/console.h>

src/southbridge/intel/bd82x6x/finalize.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/post_codes.h>
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/common/rcba.h>

src/southbridge/intel/bd82x6x/lpc.c

@@ -18,6 +18,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <pc80/i8259.h>

src/southbridge/intel/common/acpi_pirq_gen.c

@@ -17,6 +17,7 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/pci_def.h>
+#include <device/pci_ops.h>
 #include <string.h>
 
 #include "acpi_pirq_gen.h"

src/southbridge/intel/fsp_bd82x6x/finalize.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/post_codes.h>
 #include "pch.h"
 #include <spi-generic.h>

src/southbridge/intel/fsp_i89xx/finalize.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/post_codes.h>
 #include "pch.h"
 #include <spi-generic.h>

src/southbridge/intel/lynxpoint/finalize.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/post_codes.h>
 #include <spi-generic.h>
 #include "me.h"

src/southbridge/intel/lynxpoint/lpc.c

@@ -19,6 +19,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
 #include <pc80/isa-dma.h>
 #include <pc80/i8259.h>

src/southbridge/intel/lynxpoint/pcie.c

@@ -19,6 +19,7 @@
 #include <device/pci.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include "pch.h"
 #include <southbridge/intel/common/gpio.h>