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device: Use pcidev_path_on_root()

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Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Kyösti Mälkki
2018-06-21 16:20:55 +03:00
committed by Felix Held
parent c70eed1e62
commit e7377556cc
30 changed files with 40 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/drivers/usb/pci_ehci.c
View File

@@ -37,8 +37,7 @@ int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
#ifdef __SIMPLE_DEVICE__
pci_devfn_t dev = dbg_dev;
#else
struct device *dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev),
PCI_DEV2DEVFN(dbg_dev));
struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(dbg_dev));
#endif
u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
@@ -124,8 +123,7 @@ u8 *pci_ehci_base_regs(pci_devfn_t sdev)
#ifdef __SIMPLE_DEVICE__
u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f);
#else
struct device *dev = dev_find_slot(PCI_DEV2SEGBUS(sdev),
PCI_DEV2DEVFN(sdev));
struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(sdev));
u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f);
#endif
return base + HC_LENGTH(read32(base));

2
src/mainboard/google/kahlee/OemCustomize.c
View File

@@ -79,7 +79,7 @@ void OemPostParams(AMD_POST_PARAMS *PostParams)
void set_board_env_params(GNB_ENV_CONFIGURATION *params)
{
const struct soc_amd_stoneyridge_config *cfg;
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
if (!dev || !dev->chip_info) {
printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree config\n");
return;

4
src/mainboard/google/octopus/mainboard.c
View File

@@ -36,7 +36,7 @@
static bool is_cnvi_held_in_reset(void)
{
struct device *dev = dev_find_slot(0, PCH_DEVFN_CNVI);
struct device *dev = pcidev_path_on_root(PCH_DEVFN_CNVI);
uint32_t reg = pci_read_config32(dev, PCI_VENDOR_ID);
/*
@@ -167,7 +167,7 @@ static void wifi_device_update(void)
else
devfn = PCH_DEVFN_PCIE1;
dev = dev_find_slot(0, devfn);
dev = pcidev_path_on_root(devfn);
if (dev)
dev->enabled = 0;
}

2
src/mainboard/google/octopus/variants/phaser/variant.c
View File

@@ -25,7 +25,7 @@ void variant_update_devtree(struct device *dev)
uint32_t sku_id = SKU_UNKNOWN;
struct device *touchscreen_i2c_host;
touchscreen_i2c_host = dev_find_slot(0, PCH_DEVFN_I2C7);
touchscreen_i2c_host = pcidev_path_on_root(PCH_DEVFN_I2C7);
if (touchscreen_i2c_host == NULL)
return;

2
src/mainboard/google/poppy/variants/atlas/gpio.c
View File

@@ -419,7 +419,7 @@ static const struct pad_config ish_disabled_gpio_table[] = {
const struct pad_config *variant_sku_gpio_table(size_t *num)
{
const struct pad_config *board_gpio_tables;
const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);
const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH);
if (dev && dev->enabled) {
*num = ARRAY_SIZE(ish_enabled_gpio_table);
board_gpio_tables = ish_enabled_gpio_table;

2
src/mainboard/purism/librem_skl/hda_verb.c
View File

@@ -62,7 +62,7 @@ static void mb_hda_codec_init(void *unused)
return;
/* Find base address */
dev = dev_find_slot(0, PCH_DEVFN_HDA);
dev = pcidev_path_on_root(PCH_DEVFN_HDA);
if (dev == NULL)
return;
res = find_resource(dev, PCI_BASE_ADDRESS_0);

2
src/northbridge/amd/amdfam10/amdfam10_util.c
View File

@@ -26,7 +26,7 @@
#include <include/device/pci_def.h>
u32 Get_NB32(u32 dev, u32 reg)
{
return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg);
}
#endif

2
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
View File

@@ -59,7 +59,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
DEVTREE_CONST config_t *config;
printk(BIOS_DEBUG, "Configure Default UPD Data\n");
dev = dev_find_slot(0, SOC_DEV_FUNC);
dev = pcidev_path_on_root(SOC_DEV_FUNC);
config = dev->chip_info;
/* Set SPD addresses */

2
src/northbridge/intel/gm45/raminit.c
View File

@@ -1165,7 +1165,7 @@ static unsigned int get_mmio_size(void)
const struct device *dev;
const struct northbridge_intel_gm45_config *cfg = NULL;
dev = dev_find_slot(0, HOST_BRIDGE);
dev = pcidev_path_on_root(HOST_BRIDGE);
if (dev)
cfg = dev->chip_info;

2
src/northbridge/intel/haswell/northbridge.c
View File

@@ -459,7 +459,7 @@ static void disable_devices(void)
deven = pci_read_config32(host_dev, DEVEN);
for (i = 0; i < ARRAY_SIZE(nb_devs); i++) {
struct device *dev = dev_find_slot(0, nb_devs[i].devfn);
struct device *dev = pcidev_path_on_root(nb_devs[i].devfn);
if (!dev || !dev->enabled) {
printk(BIOS_DEBUG, "Disabling %s.\n", nb_devs[i].name);
deven &= ~nb_devs[i].mask;

2
src/northbridge/intel/nehalem/raminit.c
View File

@@ -1366,7 +1366,7 @@ static unsigned int get_mmio_size(void)
const struct device *dev;
const struct northbridge_intel_nehalem_config *cfg = NULL;
dev = dev_find_slot(0, HOST_BRIDGE);
dev = pcidev_path_on_root(HOST_BRIDGE);
if (dev)
cfg = dev->chip_info;

4
src/northbridge/intel/sandybridge/raminit_common.c
View File

@@ -383,7 +383,7 @@ unsigned int get_mem_min_tck(void)
const struct device *dev;
const struct northbridge_intel_sandybridge_config *cfg = NULL;
dev = dev_find_slot(0, HOST_BRIDGE);
dev = pcidev_path_on_root(HOST_BRIDGE);
if (dev)
cfg = dev->chip_info;
@@ -449,7 +449,7 @@ static unsigned int get_mmio_size(void)
const struct device *dev;
const struct northbridge_intel_sandybridge_config *cfg = NULL;
dev = dev_find_slot(0, HOST_BRIDGE);
dev = pcidev_path_on_root(HOST_BRIDGE);
if (dev)
cfg = dev->chip_info;

2
src/soc/amd/common/block/pi/agesawrapper.c
View File

@@ -324,7 +324,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
*/
AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct);
const struct device *dev = dev_find_slot(0, IOMMU_DEVFN);
const struct device *dev = pcidev_path_on_root(IOMMU_DEVFN);
if (dev && dev->enabled) {
LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS
+ 1;

4
src/soc/amd/stoneyridge/BiosCallOuts.c
View File

@@ -52,7 +52,7 @@ AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData,
void *ConfigPtr)
{
AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
const struct device *dev = dev_find_slot(0, SATA_DEVFN);
const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
@@ -104,7 +104,7 @@ AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr)
if (!ENV_ROMSTAGE)
return AGESA_UNSUPPORTED;
dev = dev_find_slot(0, DCT_DEVFN);
dev = pcidev_path_on_root(DCT_DEVFN);
if (dev == NULL)
return AGESA_ERROR;

2
src/soc/amd/stoneyridge/gpio.c
View File

@@ -347,7 +347,7 @@ static void restore_i2c_pin_registers(uint8_t gpio,
void sb_reset_i2c_slaves(void)
{
const struct soc_amd_stoneyridge_config *cfg;
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
struct soc_amd_i2c_save save_table[saved_pins_count];
uint8_t i, j, control;

2
src/soc/amd/stoneyridge/i2c.c
View File

@@ -45,7 +45,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus)
static const struct soc_amd_stoneyridge_config *get_soc_config(void)
{
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",

4
src/soc/amd/stoneyridge/romstage.c
View File

@@ -187,7 +187,7 @@ asmlinkage void car_stage_entry(void)
void SetMemParams(AMD_POST_PARAMS *PostParams)
{
const struct soc_amd_stoneyridge_config *cfg;
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "ERROR: Cannot find SoC devicetree config\n");
@@ -224,7 +224,7 @@ void SetMemParams(AMD_POST_PARAMS *PostParams)
void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly)
{
const struct soc_amd_stoneyridge_config *cfg;
const struct device *dev = dev_find_slot(0, GNB_DEVFN);
const struct device *dev = pcidev_path_on_root(GNB_DEVFN);
struct _PLATFORM_CONFIGURATION *platform;
if (!dev || !dev->chip_info) {

8
src/soc/amd/stoneyridge/southbridge.c
View File

@@ -73,7 +73,7 @@ static inline int sb_ide_enable(void)
void SetFchResetParams(FCH_RESET_INTERFACE *params)
{
const struct device *dev = dev_find_slot(0, SATA_DEVFN);
const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
params->Xhci0Enable = IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE);
if (dev && dev->enabled) {
params->SataEnable = sb_sata_enable();
@@ -86,7 +86,7 @@ void SetFchResetParams(FCH_RESET_INTERFACE *params)
void SetFchEnvParams(FCH_INTERFACE *params)
{
const struct device *dev = dev_find_slot(0, SATA_DEVFN);
const struct device *dev = pcidev_path_on_root(SATA_DEVFN);
params->AzaliaController = AzEnable;
params->SataClass = CONFIG_STONEYRIDGE_SATA_MODE;
if (dev && dev->enabled) {
@@ -904,9 +904,9 @@ static void set_sb_final_nvs(void)
gnvs->aoac.ehce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB2);
gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3);
/* Rely on these being in sync with devicetree */
sd = dev_find_slot(0, SD_DEVFN);
sd = pcidev_path_on_root(SD_DEVFN);
gnvs->aoac.st_e = sd && sd->enabled ? 1 : 0;
sata = dev_find_slot(0, SATA_DEVFN);
sata = pcidev_path_on_root(SATA_DEVFN);
gnvs->aoac.sd_e = sata && sata->enabled ? 1 : 0;
gnvs->aoac.espi = 1;

2
src/soc/intel/common/block/chip/chip.c
View File

@@ -22,7 +22,7 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void)
const struct soc_intel_common_config *soc_config;
const config_t *config;
int devfn = SA_DEVFN_ROOT;
const struct device *dev = dev_find_slot(0, devfn);
const struct device *dev = pcidev_path_on_root(devfn);
if (!dev || !dev->chip_info)
die("Could not find SA_DEV_ROOT devicetree config!\n");

2
src/soc/intel/common/block/gspi/gspi.c
View File

@@ -236,7 +236,7 @@ static uintptr_t gspi_calc_base_addr(unsigned int gspi_bus)
if (devfn < 0)
return 0;
dev = dev_find_slot(0, devfn);
dev = pcidev_path_on_root(devfn);
if (!dev || !dev->enabled)
return 0;

4
src/soc/intel/common/block/i2c/i2c.c
View File

@@ -65,7 +65,7 @@ static int lpss_i2c_early_init_bus(unsigned int bus)
/* Look up the controller device in the devicetree */
dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn));
tree_dev = dev_find_slot(0, devfn);
tree_dev = pcidev_path_on_root(devfn);
if (!tree_dev || !tree_dev->enabled) {
printk(BIOS_ERR, "I2C%u device not enabled\n", bus);
return -1;
@@ -134,7 +134,7 @@ uintptr_t dw_i2c_base_address(unsigned int bus)
return (uintptr_t)NULL;
/* devfn -> dev */
dev = dev_find_slot(0, devfn);
dev = pcidev_path_on_root(devfn);
if (!dev || !dev->enabled)
return (uintptr_t)NULL;

2
src/soc/intel/fsp_baytrail/acpi.c
View File

@@ -173,7 +173,7 @@ typedef struct soc_intel_fsp_baytrail_config config_t;
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
struct device *lpcdev = dev_find_slot(0, FADT_SOC_LPC_DEVFN);
struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN);
u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
config_t *config = lpcdev->chip_info;

2
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
View File

@@ -86,7 +86,7 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
DEVTREE_CONST config_t *config;
printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n");
dev = dev_find_slot(0, SOC_DEV_FUNC);
dev = pcidev_path_on_root(SOC_DEV_FUNC);
config = dev->chip_info;
/* Set up default verb tables - Just HDMI audio */

4
src/soc/intel/fsp_broadwell_de/acpi.c
View File

@@ -312,7 +312,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
static unsigned long acpi_fill_dmar(unsigned long current)
{
uint32_t vtbar, tmp = current;
struct device *dev = dev_find_slot(0, VTD_DEV_FUNC);
struct device *dev = pcidev_path_on_root(VTD_DEV_FUNC);
uint16_t bdf, hpet_bdf[8];
uint8_t i, j;
@@ -329,7 +329,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
current += acpi_create_dmar_ds_ioapic(current,
9, 0, 5, 4);
/* Get the PCI BDF for the PCH I/O APIC */
dev = dev_find_slot(0, LPC_DEV_FUNC);
dev = pcidev_path_on_root(LPC_DEV_FUNC);
bdf = pci_read_config16(dev, 0x6c);
current += acpi_create_dmar_ds_ioapic(current,
8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf));

2
src/soc/intel/quark/romstage/fsp1_1.c
View File

@@ -84,7 +84,7 @@ void soc_memory_init_params(struct romstage_params *params,
size_t rmu_data_len;
/* Locate the configuration data from devicetree.cb */
dev = dev_find_slot(0, LPC_DEV_FUNC);
dev = pcidev_path_on_root(LPC_DEV_FUNC);
if (!dev) {
printk(BIOS_CRIT,
"Error! Device (PCI:0:%02x.%01x) not found, "

2
src/soc/intel/quark/romstage/fsp2_0.c
View File

@@ -120,7 +120,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
die("Microcode file (rmu.bin) not found.");
/* Locate the configuration data from devicetree.cb */
dev = dev_find_slot(0, LPC_DEV_FUNC);
dev = pcidev_path_on_root(LPC_DEV_FUNC);
if (!dev)
die("ERROR - LPC device not found!");
config = dev->chip_info;

2
src/southbridge/intel/fsp_rangeley/acpi.c
View File

@@ -34,7 +34,7 @@ typedef struct southbridge_intel_fsp_rangeley_config config_t;
void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
struct device *lpcdev = dev_find_slot(0, SOC_LPC_DEVFN);
struct device *lpcdev = pcidev_path_on_root(SOC_LPC_DEVFN);
u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
config_t *config = lpcdev->chip_info;

2
src/southbridge/intel/i82801dx/i82801dx.c
View File

@@ -26,7 +26,7 @@ void i82801dx_enable(struct device *dev)
// all 82801dbm devices are in bus 0
unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
struct device *lpc_dev = dev_find_slot(0, devfn); // 0
struct device *lpc_dev = pcidev_path_on_root(devfn); // 0
if (!lpc_dev)
return;

2
src/southbridge/intel/i82801ix/i82801ix.c
View File

@@ -137,7 +137,7 @@ static void i82801ix_ehci_init(void)
static int i82801ix_function_disabled(const unsigned devfn)
{
const struct device *const dev = dev_find_slot(0, devfn);
struct device *const dev = pcidev_path_on_root(devfn);
if (!dev) {
printk(BIOS_EMERG,
"PCI device 00:%x.%x",

2
src/southbridge/intel/i82801jx/i82801jx.c
View File

@@ -136,7 +136,7 @@ static void i82801jx_ehci_init(void)
static int i82801jx_function_disabled(const unsigned int devfn)
{
const struct device *const dev = dev_find_slot(0, devfn);
struct device *const dev = pcidev_path_on_root(devfn);
if (!dev) {
printk(BIOS_EMERG,
"PCI device 00:%x.%x",