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arch/x86/ioapic: Promote ioapic_get_sci_pin()

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Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.

Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2023-04-10 17:03:32 +03:00
parent ae1b2d49cf
commit e742b68f1a
28 changed files with 56 additions and 42 deletions
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4
src/acpi/acpi.c
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@ -226,7 +226,7 @@ int acpi_create_madt_ioapic_from_hw(acpi_madt_ioapic_t *ioapic, u32 addr)
}
#endif
u16 acpi_sci_int(void)
static u16 acpi_sci_int(void)
{
#if ENV_X86
u8 gsi, irq, flags;
@ -1736,6 +1736,8 @@ static void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
if (CONFIG(USE_PC_CMOS_ALTCENTURY))
fadt->century = RTC_CLK_ALTCENTURY;
fadt->sci_int = acpi_sci_int();
arch_fill_fadt(fadt);
acpi_fill_fadt(fadt);

2
src/include/acpi/acpi.h
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@ -1345,8 +1345,6 @@ unsigned long acpi_create_madt_lapics_with_nmis(unsigned long current);
unsigned long acpi_create_madt_lapic_nmis(unsigned long current);
u16 acpi_sci_int(void);
int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic);
int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic);
int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek,

2
src/soc/amd/cezanne/acpi.c
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@ -49,8 +49,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->sci_int = ACPI_SCI_IRQ;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

8
src/soc/amd/common/block/lpc/lpc.c
View File

@ -16,6 +16,7 @@
#include <amdblocks/ioapic.h>
#include <amdblocks/iomap.h>
#include <amdblocks/lpc.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/southbridge.h>
@ -34,6 +35,13 @@ static void setup_serirq(void)
pm_write8(PM_SERIRQ_CONF, byte);
}
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
{
*gsi = ACPI_SCI_IRQ;
*irq = ACPI_SCI_IRQ;
*flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;
}
static void fch_ioapic_init(void)
{
fch_enable_ioapic_decode();

2
src/soc/amd/glinda/acpi.c
View File

@ -52,8 +52,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->sci_int = ACPI_SCI_IRQ;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/soc/amd/mendocino/acpi.c
View File

@ -51,8 +51,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->sci_int = ACPI_SCI_IRQ;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/soc/amd/phoenix/acpi.c
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@ -52,8 +52,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->sci_int = ACPI_SCI_IRQ;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/soc/amd/picasso/acpi.c
View File

@ -56,8 +56,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->sci_int = ACPI_SCI_IRQ;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/soc/amd/stoneyridge/acpi.c
View File

@ -50,8 +50,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
fadt->sci_int = ACPI_SCI_IRQ;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

3
src/soc/intel/baytrail/fadt.c
View File

@ -2,7 +2,6 @@
#include <acpi/acpi.h>
#include <cpu/x86/smm.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include "chip.h"
@ -11,8 +10,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_int();
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/soc/intel/braswell/fadt.c
View File

@ -11,8 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_int();
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/soc/intel/broadwell/pch/fadt.c
View File

@ -10,8 +10,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = 9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

9
src/soc/intel/broadwell/pch/lpc.c
View File

@ -36,6 +36,15 @@ static void pch_enable_ioapic(struct device *dev)
register_new_ioapic_gsi0(VIO_APIC_VADDR);
}
#define ACPI_SCI_IRQ 9
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
{
*gsi = ACPI_SCI_IRQ;
*irq = ACPI_SCI_IRQ;
*flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
}
static void enable_hpet(struct device *dev)
{
size_t i;

2
src/soc/intel/common/block/acpi/acpi.c
View File

@ -94,8 +94,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
const uint16_t pmbase = ACPI_BASE_ADDRESS;
fadt->sci_int = acpi_sci_int();
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

8
src/soc/intel/quark/lpc.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/ioapic.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/iomap.h>
@ -34,6 +35,13 @@ static void pmc_read_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
/* Implemented just to fill FADT SCI_INT as 0. */
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
{
*irq = 0;
*gsi = 0;
}
static struct device_operations device_ops = {
.read_resources = pmc_read_resources,
.set_resources = pci_dev_set_resources,

2
src/southbridge/amd/pi/hudson/fadt.c
View File

@ -25,8 +25,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE);
fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */
if (permanent_smi_handler()) {
fadt->smi_cmd = ACPI_SMI_CTL_PORT;
fadt->acpi_enable = ACPI_SMI_CMD_ENABLE;

2
src/southbridge/amd/pi/hudson/hudson.h
View File

@ -42,6 +42,8 @@
#define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
#define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
#define ACPI_SCI_IRQ 9
#define ACPI_SMI_CTL_PORT 0xb2
#define ACPI_SMI_CMD_CST_CONTROL 0xde
#define ACPI_SMI_CMD_PST_CONTROL 0xad

7
src/southbridge/amd/pi/hudson/sm.c
View File

@ -19,6 +19,13 @@
* HUDSON enables SATA by default in SMBUS Control.
*/
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
{
*gsi = ACPI_SCI_IRQ;
*irq = ACPI_SCI_IRQ;
*flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;
}
static void sm_init(struct device *dev)
{
register_new_ioapic_gsi0(VIO_APIC_VADDR);

2
src/southbridge/intel/bd82x6x/fadt.c
View File

@ -12,8 +12,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
struct southbridge_intel_bd82x6x_config *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
fadt->sci_int = 0x9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

10
src/southbridge/intel/common/pmbase.c
View File

@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <arch/io.h>
#include <arch/ioapic.h>
#include <assert.h>
#include <bootmode.h>
#include <device/pci_ops.h>
@ -92,3 +93,12 @@ int platform_is_resuming(void)
return acpi_get_sleep_type() == ACPI_S3;
}
#define ACPI_SCI_IRQ 9
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
{
*gsi = ACPI_SCI_IRQ;
*irq = ACPI_SCI_IRQ;
*flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
}

2
src/southbridge/intel/i82371eb/fadt.c
View File

@ -16,8 +16,6 @@
*/
void acpi_fill_fadt(acpi_fadt_t *fadt)
{
fadt->sci_int = 9;
if (permanent_smi_handler()) {
/* TODO: SMI handler is not implemented. */
fadt->smi_cmd = 0x00;

9
src/southbridge/intel/i82371eb/isa.c
View File

@ -67,6 +67,15 @@ static void isa_init(struct device *dev)
}
}
#define ACPI_SCI_IRQ 9
void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags)
{
*gsi = ACPI_SCI_IRQ;
*irq = ACPI_SCI_IRQ;
*flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH;
}
static void sb_read_resources(struct device *dev)
{
struct resource *res;

2
src/southbridge/intel/i82801dx/fadt.c
View File

@ -8,8 +8,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
fadt->sci_int = 0x9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/southbridge/intel/i82801gx/fadt.c
View File

@ -13,8 +13,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
struct southbridge_intel_i82801gx_config *chip = dev->chip_info;
u16 pmbase = lpc_get_pmbase();
fadt->sci_int = 0x9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/southbridge/intel/i82801ix/fadt.c
View File

@ -9,8 +9,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
fadt->sci_int = 0x9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/southbridge/intel/i82801jx/fadt.c
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@ -9,8 +9,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
{
u16 pmbase = pci_read_config16(pcidev_on_root(0x1f, 0), 0x40) & 0xfffe;
fadt->sci_int = 0x9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/southbridge/intel/ibexpeak/fadt.c
View File

@ -12,8 +12,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
struct southbridge_intel_ibexpeak_config *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
fadt->sci_int = 0x9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;

2
src/southbridge/intel/lynxpoint/fadt.c
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@ -12,8 +12,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info;
u16 pmbase = get_pmbase();
fadt->sci_int = 0x9;
if (permanent_smi_handler()) {
fadt->smi_cmd = APM_CNT;
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;