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mainboard/google/nocturne: Set camera power sequence

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To make image sensor working, the intended power sequence need to
applied.

BUG=NONE
TEST=NONE

Change-Id: I4833c0e303174b297c1d193495e08e55d294a717
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/27094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Lijian Zhao
2018-06-13 12:51:47 -07:00
committed by Patrick Georgi
parent d0a5deb46a
commit e78af97349
3 changed files with 132 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

60
src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam0.asl
View File

@@ -34,6 +34,61 @@ Scope (\_SB.PCI0.I2C3)
)
})
Name (STA, 0)
Method (PMON, 0, Serialized) {
If (STA == 0) {
CTXS (GPIO_FCAM_RST_L)
STXS (GPIO_FCAM_PWR_EN)
STXS (GPIO_PCH_FCAM_CLK_EN)
Sleep(3)
STXS (GPIO_FCAM_RST_L)
/*
* A delay of T7 (minimum of 5 ms) + T8
* (max 5 ms + delay of coarse integration
* time value + 14 H, time for 14 horizontal
* lines) is needed to have the sensor ready
* for streaming, as soon as the power on
* sequence completes
*/
Sleep(11);
}
STA++
}
Method (PMOF, 0, Serialized) {
If (STA == 0) {
Return
}
STA--
If (STA == 0) {
CTXS (GPIO_PCH_FCAM_CLK_EN)
CTXS (GPIO_FCAM_RST_L)
CTXS (GPIO_FCAM_PWR_EN)
}
}
Name (_PR0, Package (0x01) { FCPR })
Name (_PR3, Package (0x01) { FCPR })
/* Power resource methods for Rear Camera */
PowerResource (FCPR, 0, 0) {
Method (_ON, 0, Serialized) {
PMON ()
}
Method (_OFF, 0, Serialized) {
PMOF ()
}
Method (_STA, 0, Serialized) {
If (LGreater(STA,0)) {
Return (0x1)
}
Else {
Return (0x0)
}
}
}
/* Port0 of CAM0 is connected to port0 of CIO2 device */
Name (_DSD, Package () {
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
@@ -93,6 +148,11 @@ Scope (\_SB.PCI0.I2C3)
0x00, ResourceConsumer, ,)
})
Name (_DEP, Package() { ^^I2C3.CAM0 })
Name (_PR0, Package (0x01) { ^^I2C3.CAM0.FCPR })
Name (_PR3, Package (0x01) { ^^I2C3.CAM0.FCPR })
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),

64
src/mainboard/google/poppy/variants/nocturne/include/variant/acpi/cam1.asl
View File

@@ -35,6 +35,60 @@ Scope (\_SB.PCI0.I2C5)
)
})
Name (STA, 0)
Method (PMON, 0, Serialized) {
If (STA == 0) {
CTXS(GPIO_RCAM_RST_L)
STXS(GPIO_RCAM_PWR_EN)
STXS(GPIO_PCH_RCAM_CLK_EN)
Sleep(3)
STXS(GPIO_RCAM_RST_L)
/*
* A delay of T7 (minimum of 10 ms) + T8
* (max 1.4 ms + delay of coarse integration
* time value) is needed to have the sensor
* ready for streaming, as soon as the power
* on sequence completes
*/
Sleep(12)
}
STA++
}
Method (PMOF, 0, Serialized) {
If (STA == 0) {
Return
}
STA--
If (STA == 0) {
CTXS(GPIO_PCH_RCAM_CLK_EN)
CTXS(GPIO_RCAM_RST_L)
CTXS(GPIO_RCAM_PWR_EN)
}
}
Name (_PR0, Package (0x01) { RCPR })
Name (_PR3, Package (0x01) { RCPR })
/* Power resource methods for Rear Camera */
PowerResource (RCPR, 0, 0) {
Method (_ON, 0, Serialized) {
PMON ()
}
Method (_OFF, 0, Serialized) {
PMOF ()
}
Method (_STA, 0, Serialized) {
If (LGreater(STA,0)) {
Return (0x1)
}
Else {
Return (0x0)
}
}
}
/* Port0 of CAM1 is connected to port1 of CIO2 device */
Name (_DSD, Package () {
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
@@ -98,6 +152,11 @@ Scope (\_SB.PCI0.I2C5)
)
})
Name (_DEP, Package() { ^^I2C5.CAM1 })
Name (_PR0, Package (0x01) { ^^I2C5.CAM1.RCPR })
Name (_PR3, Package (0x01) { ^^I2C5.CAM1.RCPR })
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package () {
@@ -124,6 +183,11 @@ Scope (\_SB.PCI0.I2C5)
0x00, ResourceConsumer, ,)
})
Name (_DEP, Package () { ^^I2C5.CAM1 })
Name (_PR0, Package (0x01) { ^^I2C5.CAM1.RCPR })
Name (_PR3, Package (0x01) { ^^I2C5.CAM1.RCPR })
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),

8
src/mainboard/google/poppy/variants/nocturne/include/variant/gpio.h
View File

@@ -37,4 +37,12 @@
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* Camera Sensor config */
#define GPIO_RCAM_PWR_EN GPP_D7
#define GPIO_PCH_RCAM_CLK_EN GPP_D14
#define GPIO_RCAM_RST_L GPP_D16
#define GPIO_FCAM_PWR_EN GPP_D8
#define GPIO_PCH_FCAM_CLK_EN GPP_D13
#define GPIO_FCAM_RST_L GPP_D15
#endif /* BASEBOARD_GPIO_H */