cbmem_top: Change the return value to uintptr_t

Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/postcar_loader.c

@@ -181,7 +181,7 @@ static void run_postcar_phase(struct postcar_frame *pcf)
 
 	postcar_flush_cache();
 
-	prog_set_arg(&prog, cbmem_top());
+	prog_set_arg(&prog, (void *)cbmem_top());
 
 	prog_run(&prog);
 }

src/device/pci_device.c

@@ -570,7 +570,7 @@ void pci_domain_read_resources(struct device *dev)
 	 * one big range from cbmem_top to the configured limit.
 	 */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base  = (uintptr_t)cbmem_top();
+	res->base  = cbmem_top();
 	res->limit = CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT - 1;
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED;

src/drivers/amd/agesa/mtrr_fixme.c

@@ -44,8 +44,7 @@ void fixup_cbmem_to_UC(int s3resume)
 	 * writeback possible.
 	 */
 
-	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
-	top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB);
+	const uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 4 * MiB);
 
 	set_range_uc(top_of_ram - 4 * MiB, 4 * MiB);
 	set_range_uc(top_of_ram - 8 * MiB, 4 * MiB);
@@ -78,7 +77,7 @@ static void recover_postcar_frame(struct postcar_frame *pcf)
 	 * speed make them WB after CAR teardown.
 	 */
 	if (s3resume) {
-		uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+		uintptr_t top_of_ram = cbmem_top();
 		top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB);
 
 		postcar_frame_add_mtrr(pcf, top_of_ram - 4 * MiB, 4 * MiB,

src/drivers/intel/fsp1_1/car.c

@@ -12,12 +12,10 @@
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
 	 * above top of the ram. This satisfies MTRR alignment requirement
 	 * with different TSEG size configurations. */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
 }
 

src/drivers/intel/fsp1_1/raminit.c

@@ -138,7 +138,7 @@ void raminit(struct romstage_params *params)
 	}
 
 	/* Migrate CAR data */
-	printk(BIOS_DEBUG, "%p: cbmem_top\n", cbmem_top());
+	printk(BIOS_DEBUG, "%lx: cbmem_top\n", cbmem_top());
 	if (!s3wake) {
 		cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
 			fsp_reserved_bytes);

src/drivers/intel/fsp2_0/hob_verify.c

@@ -43,8 +43,8 @@ void fsp_verify_memory_init_hobs(void)
 		die("Space between FSP reserved region and BIOS TOLUM!\n");
 	}
 
-	if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) {
-		printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n",
+	if (range_entry_end(&tolum) != cbmem_top()) {
+		printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %lx: cbmem_top\n",
 			range_entry_end(&tolum), cbmem_top());
 		die("Space between cbmem_top and BIOS TOLUM!\n");
 	}

src/include/cbmem.h

@@ -57,7 +57,7 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size);
 /* The assumption is made that the result of cbmem_top_romstage fits in the size
    of uintptr_t in the ramstage. */
 extern uintptr_t _cbmem_top_ptr;
-void *cbmem_top(void);
+uintptr_t cbmem_top(void);
 /* With CONFIG_RAMSTAGE_CBMEM_TOP_ARG set, the result of cbmem_top is passed via
  * calling arguments to the next stage and saved in the global _cbmem_top_ptr
  * global variable. Only a romstage callback needs to be implemented by the

src/lib/imd_cbmem.c

@@ -15,17 +15,17 @@ uintptr_t _cbmem_top_ptr;
 
 static struct imd imd;
 
-void *cbmem_top(void)
+uintptr_t cbmem_top(void)
 {
 	if (ENV_CREATES_CBMEM) {
 		static uintptr_t top;
 		if (top)
-			return (void *)top;
+			return top;
 		top = cbmem_top_chipset();
-		return (void *)top;
+		return top;
 	}
 	if (ENV_POSTCAR || ENV_RAMSTAGE)
-		return (void *)_cbmem_top_ptr;
+		return _cbmem_top_ptr;
 
 	dead_code();
 }
@@ -55,7 +55,7 @@ static void cbmem_top_init_once(void)
 
 	/* The test is only effective on X86 and when address hits UC memory. */
 	if (ENV_X86)
-		quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32));
+		quick_ram_check_or_die(cbmem_top() - sizeof(u32));
 }
 
 void cbmem_initialize_empty_id_size(u32 id, u64 size)
@@ -64,7 +64,7 @@ void cbmem_initialize_empty_id_size(u32 id, u64 size)
 
 	cbmem_top_init_once();
 
-	imd_handle_init(&imd, cbmem_top());
+	imd_handle_init(&imd, (void *)cbmem_top());
 
 	printk(BIOS_DEBUG, "CBMEM:\n");
 
@@ -95,7 +95,7 @@ int cbmem_initialize_id_size(u32 id, u64 size)
 
 	cbmem_top_init_once();
 
-	imd_handle_init(&imd, cbmem_top());
+	imd_handle_init(&imd, (void *)cbmem_top());
 
 	if (imd_recover(&imd))
 		return 1;

src/lib/prog_loaders.c

@@ -60,7 +60,7 @@ static void run_ramstage_from_resume(struct prog *ramstage)
 	stage_cache_load_stage(STAGE_RAMSTAGE, ramstage);
 
 	ramstage->cbfs_type = CBFS_TYPE_STAGE;
-	prog_set_arg(ramstage, cbmem_top());
+	prog_set_arg(ramstage, (void *)cbmem_top());
 
 	if (prog_entry(ramstage) != NULL) {
 		printk(BIOS_DEBUG, "Jumping to image.\n");
@@ -126,7 +126,7 @@ void __noreturn run_ramstage(void)
 	console_time_report();
 
 	/* This overrides the arg fetched from the relocatable module */
-	prog_set_arg(&ramstage, cbmem_top());
+	prog_set_arg(&ramstage, (void *)cbmem_top());
 
 	prog_run(&ramstage);
 

src/mainboard/emulation/qemu-aarch64/mainboard.c

@@ -43,7 +43,7 @@ static void qemu_aarch64_domain_read_resources(struct device *dev)
 
 	mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
 
-	ram_from_to(dev, index++, (uintptr_t)_dram, (uintptr_t)cbmem_top());
+	ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top());
 }
 
 struct device_operations qemu_aarch64_pci_domain_ops = {

src/mainboard/emulation/qemu-riscv/mainboard.c

@@ -11,7 +11,7 @@ static void mainboard_enable(struct device *dev)
 		die("No dev0; die\n");
 	}
 
-	ram_from_to(dev, 0, (uintptr_t)_dram, (uintptr_t)cbmem_top());
+	ram_from_to(dev, 0, (uintptr_t)_dram, cbmem_top());
 }
 
 struct chip_operations mainboard_ops = {

src/northbridge/intel/gm45/memmap.c

@@ -117,12 +117,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
 	 * RAM to cover both cbmem as the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
 			       MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),

src/northbridge/intel/gm45/northbridge.c

@@ -81,7 +81,7 @@ static void mch_domain_read_resources(struct device *dev)
 	reserved_ram_from_to(dev, idx++, 0xc0000, 1*MiB);
 
 	/* Report < 4GB memory */
-	ram_range(dev, idx++, 1*MiB, (uintptr_t)cbmem_top());
+	ram_range(dev, idx++, 1*MiB, cbmem_top());
 
 	/* TSEG */
 	uintptr_t tseg_base;
@@ -91,10 +91,10 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* cbmem_top can be shifted downwards due to alignment.
 	   Mark the region between cbmem_top and tseg_base as unusable */
-	if ((uintptr_t)cbmem_top() < tseg_base) {
+	if (cbmem_top() < tseg_base) {
 		printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n",
-		       tseg_base - (uintptr_t)cbmem_top());
-		mmio_from_to(dev, idx++, (uintptr_t)cbmem_top(), tseg_base);
+		       tseg_base - cbmem_top());
+		mmio_from_to(dev, idx++, cbmem_top(), tseg_base);
 	}
 
 	/* graphic memory above TSEG */

src/northbridge/intel/haswell/memmap.c

@@ -69,12 +69,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
 	 * above top of the ram. This satisfies MTRR alignment requirement
 	 * with different TSEG size configurations.
 	 */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB);
+	const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
 }

src/northbridge/intel/i440bx/memmap.c

@@ -53,10 +53,8 @@ uintptr_t cbmem_top_chipset(void)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache CBMEM region as WB. */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
 		MTRR_TYPE_WRBACK);
 }

src/northbridge/intel/i945/memmap.c

@@ -81,12 +81,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
 	 * RAM to cover both cbmem as the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
 			       northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);

src/northbridge/intel/i945/northbridge.c

@@ -34,7 +34,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* Report the memory regions */
 	ram_range(dev, idx++, 0, 0xa0000);
-	ram_from_to(dev, idx++, 1 * MiB, (uintptr_t)cbmem_top());
+	ram_from_to(dev, idx++, 1 * MiB, cbmem_top());
 
 	/* TSEG */
 	uintptr_t tseg_base;
@@ -44,10 +44,10 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* cbmem_top can be shifted downwards due to alignment.
 	   Mark the region between cbmem_top and tseg_base as unusable */
-	if ((uintptr_t)cbmem_top() < tseg_base) {
+	if (cbmem_top() < tseg_base) {
 		printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n",
-		       tseg_base - (uintptr_t)cbmem_top());
-		mmio_from_to(dev, idx++, (uintptr_t)cbmem_top(), tseg_base);
+		       tseg_base - cbmem_top());
+		mmio_from_to(dev, idx++, cbmem_top(), tseg_base);
 	}
 	if (tseg_base + tseg_size < tolud)
 		mmio_from_to(dev, idx++, tseg_base + tseg_size, tolud);

src/northbridge/intel/ironlake/memmap.c

@@ -35,13 +35,11 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
 	 * above top of the ram. This satisfies MTRR alignment requirement
 	 * with different TSEG size configurations.
 	 */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	const uintptr_t  top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
 }

src/northbridge/intel/pineview/memmap.c

@@ -86,13 +86,11 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/*
 	 * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both
 	 * CBMEM and the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(),
 			       MTRR_TYPE_WRBACK);

src/northbridge/intel/pineview/northbridge.c

@@ -69,7 +69,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* Report the memory regions */
 	ram_range(dev, index++, 0, 0xa0000);
-	ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+	ram_from_to(dev, index++, 1 * MiB, cbmem_top());
 	uintptr_t tseg_base;
 	size_t tseg_size;
 	smm_region(&tseg_base, &tseg_size);
@@ -77,8 +77,8 @@ static void mch_domain_read_resources(struct device *dev)
 	mmio_range(dev, index++, gtt_base,  gsm_size);
 	mmio_range(dev, index++, igd_base,  gms_size);
 	printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n",
-	       tseg_base - (uintptr_t)cbmem_top());
-	reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), tseg_base);
+	       tseg_base - cbmem_top());
+	reserved_ram_from_to(dev, index++, cbmem_top(), tseg_base);
 
 	/*
 	 * If > 4GB installed then memory from TOLUD to 4GB

src/northbridge/intel/sandybridge/memmap.c

@@ -67,7 +67,7 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 
 	/*
 	 * Cache 8MiB below the top of ram. On sandybridge systems the top of

src/northbridge/intel/x4x/memmap.c

@@ -84,12 +84,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
 	 * RAM to cover both cbmem as the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
 			MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),

src/northbridge/intel/x4x/northbridge.c

@@ -45,7 +45,7 @@ static void mch_domain_read_resources(struct device *dev)
 	ram_from_to(dev, index++, 0, 0xa0000);
 	mmio_from_to(dev, index++, 0xa0000, 0xc0000);
 	reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
-	ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+	ram_from_to(dev, index++, 1 * MiB, cbmem_top());
 
 	/*
 	 * If >= 4GB installed then memory from TOLUD to 4GB
@@ -57,7 +57,7 @@ static void mch_domain_read_resources(struct device *dev)
 	size_t tseg_size;
 	smm_region(&tseg_base, &tseg_size);
 	mmio_from_to(dev, index++, tseg_base, tolud);
-	reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), tseg_base);
+	reserved_ram_from_to(dev, index++, cbmem_top(), tseg_base);
 
 	/* Reserve high memory where the NB BARs are up to 4GiB */
 	mmio_from_to(dev, index++, DEFAULT_HECIBAR, 4ull * GiB);

src/soc/amd/common/block/cpu/noncar/memmap.c

@@ -42,7 +42,7 @@ static const struct memmap_early_dram *memmap_get_early_dram_usage(void)
 /* report SoC memory map up to cbmem_top */
 void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx)
 {
-	const uint32_t mem_usable = (uintptr_t)cbmem_top();
+	const uint32_t mem_usable = cbmem_top();
 	const struct memmap_early_dram *e = memmap_get_early_dram_usage();
 	const uintptr_t early_reserved_dram_start = e->base;
 	const uintptr_t early_reserved_dram_end = e->base + e->size;
@@ -76,7 +76,7 @@ void smm_region(uintptr_t *start, size_t *size)
 	if (CONFIG(PLATFORM_USES_FSP2_0)) {
 		fsp_get_smm_region(start, size);
 	} else {
-		*start = (uintptr_t)cbmem_top();
+		*start = cbmem_top();
 		*size = CONFIG_SMM_TSEG_SIZE;
 	}
 

src/soc/amd/common/fsp/fsp_report_resources.c

@@ -9,7 +9,7 @@
 
 void read_fsp_resources(struct device *dev, unsigned long *idx)
 {
-	const uint32_t mem_usable = (uintptr_t)cbmem_top();
+	const uint32_t mem_usable = cbmem_top();
 	const struct hob_header *hob_iterator;
 	const struct hob_resource *res;
 

src/soc/amd/stoneyridge/memmap.c

@@ -22,7 +22,7 @@ uintptr_t cbmem_top_chipset(void)
 
 static uintptr_t smm_region_start(void)
 {
-	return (uintptr_t)cbmem_top();
+	return cbmem_top();
 }
 
 static size_t smm_region_size(void)

src/soc/amd/stoneyridge/northbridge.c

@@ -259,7 +259,7 @@ void domain_read_resources(struct device *dev)
 {
 	uint64_t uma_base = get_uma_base();
 	uint32_t uma_size = get_uma_size();
-	uint32_t mem_useable = (uintptr_t)cbmem_top();
+	uint32_t mem_useable = cbmem_top();
 	uint32_t tom = get_top_of_mem_below_4gb();
 	uint64_t high_tom = get_top_of_mem_above_4gb();
 	uint64_t high_mem_useable;

src/soc/amd/stoneyridge/romstage.c

@@ -125,7 +125,7 @@ void __noreturn romstage_main(void)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
 
 	/* Cache the TSEG region */

src/soc/intel/baytrail/memmap.c

@@ -29,13 +29,11 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
 	 * above top of the ram. This satisfies MTRR alignment requirement
 	 * with different TSEG size configurations.
 	 */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
 			       MTRR_TYPE_WRBACK);
 }

src/soc/intel/broadwell/memmap.c

@@ -47,13 +47,11 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
 	 * above top of the ram. This satisfies MTRR alignment requirement
 	 * with different TSEG size configurations.
 	 */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
 			MTRR_TYPE_WRBACK);
 }

src/soc/intel/common/block/systemagent/memmap.c

@@ -60,7 +60,7 @@ void smm_region(uintptr_t *start, size_t *size)
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
 	/* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */
-	uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB);
+	const uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 8 * MiB);
 
 	/*
 	 * We need to make sure ramstage will be run cached. At this

src/soc/intel/common/block/systemagent/systemagent.c

@@ -188,10 +188,9 @@ static void sa_get_mem_map(struct device *dev, uint64_t *values)
 static void sa_add_dram_resources(struct device *dev, int *resource_count)
 {
 	uint64_t sa_map_values[MAX_MAP_ENTRIES];
-	uintptr_t top_of_ram;
 	int index = *resource_count;
 
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 
 	/* 0 - > 0xa0000 */
 	ram_from_to(dev, index++, 0, 0xa0000);

src/soc/intel/denverton_ns/acpi.c

@@ -56,7 +56,7 @@ static const acpi_cstate_t cstate_map[] = {
 void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	/* Top of Low Memory (start of resource allocation) */
-	gnvs->tolm = (uintptr_t)cbmem_top();
+	gnvs->tolm = cbmem_top();
 
 	/* MMIO Low/High & TSEG base and length */
 	gnvs->mmiob = (u32)get_top_of_low_memory();

src/soc/intel/denverton_ns/memmap.c

@@ -41,14 +41,12 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/*
 	 * We need to make sure ramstage will be run cached. At this point exact
 	 * location of ramstage in cbmem is not known. Instruct postcar to cache
 	 * 16 megs under cbmem top which is a safe bet to cover ramstage.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB,
 			       MTRR_TYPE_WRBACK);
 

src/soc/intel/denverton_ns/systemagent.c

@@ -240,10 +240,10 @@ static void mc_add_dram_resources(struct device *dev)
 	reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
 
 	/* 0x100000 -> cbmem_top() */
-	ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+	ram_from_to(dev, index++, 1 * MiB, cbmem_top());
 
 	/* cbmem_top() -> TSEG */
-	mmio_from_to(dev, index++, (uintptr_t)cbmem_top(), mc_values[TSEG_REG]);
+	mmio_from_to(dev, index++, cbmem_top(), mc_values[TSEG_REG]);
 
 	/* TSEG -> TOLUD */
 	reserved_ram_from_to(dev, index++, mc_values[TSEG_REG], mc_values[TOLUD_REG]);

src/soc/intel/xeon_sp/memmap.c

@@ -30,7 +30,7 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	const uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	uintptr_t cbmem_base;
 	size_t cbmem_size;
 

src/soc/intel/xeon_sp/uncore.c

@@ -139,7 +139,7 @@ static void mc_report_map_entries(struct device *dev, uint64_t *values)
 
 static void configure_dpr(struct device *dev)
 {
-	const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB;
+	const uintptr_t cbmem_top_mb = ALIGN_UP(cbmem_top(), MiB) / MiB;
 	union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
 
 	/* The DPR lock bit has to be set sufficiently early. It looks like
@@ -245,7 +245,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
 	LOG_RESOURCE("low_ram", dev, res);
 
 	/* top_of_ram -> cbmem_top */
-	res = ram_from_to(dev, index++, top_of_ram, (uintptr_t)cbmem_top());
+	res = ram_from_to(dev, index++, top_of_ram, cbmem_top());
 	LOG_RESOURCE("cbmem_ram", dev, res);
 
 	/* Mark TSEG/SMM region as reserved */
@@ -261,7 +261,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
 		 * DPR has a 1M granularity so it's possible if cbmem_top is not 1M
 		 * aligned that some memory does not get marked as assigned.
 		 */
-		res = reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(),
+		res = reserved_ram_from_to(dev, index++, cbmem_top(),
 			(dpr.top - dpr.size) * MiB);
 		LOG_RESOURCE("unused_dram", dev, res);
 

src/soc/sifive/fu740/chip.c

@@ -8,7 +8,7 @@
 static void fu740_init(struct device *dev)
 {
 	int index = 0;
-	ram_from_to(dev, index++, FU740_DRAM, (uintptr_t)cbmem_top());
+	ram_from_to(dev, index++, FU740_DRAM, cbmem_top());
 }
 
 struct chip_operations soc_sifive_fu740_ops = {

src/vendorcode/amd/opensil/genoa_poc/memmap.c

@@ -87,7 +87,7 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, print_memory_holes, NULL);
 void add_opensil_memmap(struct device *dev, unsigned long *idx)
 {
 	// Account for UMA and TSEG
-	const uint32_t mem_usable = (uintptr_t)cbmem_top();
+	const uint32_t mem_usable = cbmem_top();
 	const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB);
 	if (mem_usable != top_mem)
 		reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem);