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soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility

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This patch refactors the handling of CSE CBMEM IDs to enable platforms
to choose whether to perform CSE sync operations within coreboot or
defer it to the payload. This separation improves code organization,
ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks.

Now, platforms can select:
  * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot
  * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync

This change ensures mutually exclusive options, avoiding unnecessary
SPI flash size increases.

BUG=b:305898363
TEST=Builds and boots successfully:
    * google/rex0 with SOC_INTEL_CSE_LITE_SKU
    * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD

Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2024-07-09 23:00:50 +05:30
parent 91d2f5d5e0
commit ea6b6acd01
4 changed files with 32 additions and 25 deletions
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2
payloads/libpayload/libc/coreboot.c
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@ -262,12 +262,14 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
case CBMEM_ID_MEM_CHIP_INFO:
info->mem_chip_base = cbmem_entry->address;
break;
#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)
case CBMEM_ID_CSE_BP_INFO:
info->cse_bp_info = cbmem_entry->address;
break;
case CBMEM_ID_CSE_INFO:
info->cse_info = cbmem_entry->address;
break;
#endif
default:
break;
}