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soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility

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This patch refactors the handling of CSE CBMEM IDs to enable platforms
to choose whether to perform CSE sync operations within coreboot or
defer it to the payload. This separation improves code organization,
ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks.

Now, platforms can select:
  * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot
  * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync

This change ensures mutually exclusive options, avoiding unnecessary
SPI flash size increases.

BUG=b:305898363
TEST=Builds and boots successfully:
    * google/rex0 with SOC_INTEL_CSE_LITE_SKU
    * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD

Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2024-07-09 23:00:50 +05:30
parent 91d2f5d5e0
commit ea6b6acd01
4 changed files with 32 additions and 25 deletions
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2
payloads/libpayload/libc/coreboot.c
View File

@ -262,12 +262,14 @@ static void cb_parse_cbmem_entry(void *ptr, struct sysinfo_t *info)
case CBMEM_ID_MEM_CHIP_INFO:
info->mem_chip_base = cbmem_entry->address;
break;
#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)
case CBMEM_ID_CSE_BP_INFO:
info->cse_bp_info = cbmem_entry->address;
break;
case CBMEM_ID_CSE_INFO:
info->cse_info = cbmem_entry->address;
break;
#endif
default:
break;
}

2
src/soc/intel/common/block/cse/Makefile.mk
View File

@ -11,6 +11,8 @@ smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c
romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) += cse_sync_payload.c
ifeq ($(CONFIG_STITCH_ME_BIN),y)
CSE_BP1_BIN := $(objcse)/cse_bp1.bin

25
src/soc/intel/common/block/cse/cse_lite.c
View File

@ -1542,31 +1542,6 @@ static void store_ish_version(void)
}
}
static void preram_create_cbmem_cse_info(int is_recovery)
{
if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD))
return;
/*
* CBMEM_ID_CSE_INFO will be used by the payload to -
* 1. Avoid reading ISH firmware version on consecutive boots.
* 2. Track state of PSR data during CSE downgrade operation.
*/
void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info));
if (!temp)
printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n");
/*
* CBMEM_ID_CSE_BP_INFO will be used by the payload to avoid reading CSE
* boot partition information on consecutive boots.
*/
temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp));
if (!temp)
printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n");
}
CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info);
static void ramstage_cse_misc_ops(void *unused)
{
if (acpi_get_sleep_type() == ACPI_S3)

28
src/soc/intel/common/block/cse/cse_sync_payload.c Normal file
View File

@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cbmem.h>
#include <console/console.h>
#include <intelblocks/cse.h>
#include <intelblocks/cse_lite.h>
static void preram_create_cbmem_cse_info_for_payload(int is_recovery)
{
/*
* CBMEM_ID_CSE_INFO will be used by the payload to -
* 1. Keep ISH firmware version on consecutive boots.
* 2. Track state of PSR data during CSE downgrade operation.
*/
void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info));
if (!temp)
printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n");
/*
* CBMEM_ID_CSE_BP_INFO will be used by the payload to keep CSE
* boot partition information on consecutive boots.
*/
temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp));
if (!temp)
printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n");
}
CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info_for_payload);