sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

bonw14: fix TBT

Browse Source
This commit is contained in:
Jeremy Soller 2020-08-19 11:38:00 -06:00
parent d928cd856b
commit eb1110c8d0
No known key found for this signature in database
GPG Key ID: E988B49EE78A7FB1
3 changed files with 7 additions and 406 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

403
src/mainboard/system76/bonw14/acpi/dgpu.asl
View File

@ -60,411 +60,12 @@ Device (\_SB.PCI0.PEG0) {
}
If (Arg2 == 0) {
Printf(" Arg2 == 0x00, return some buffer")
Printf(" Arg2 == 0x00, return supported functions")
Return (Buffer (4) {
0x01, 0x00, 0x11, 0x00
0x01, 0x00, 0x10, 0x00
})
}
If (Arg2 == 0x10) {
CreateWordField (Arg3, 0x02, BFF0)
Printf(" Arg2 = 0x10, return buffer %o", ToHexString(BFF0))
If (BFF0 == 0x564B) { // 'VK'
Printf(" Return GVK")
Return (Buffer (0xD5) {
0xA6,
0x92,
0x17,
0xE2,
0x85,
0x2A,
0xED,
0x48,
0x4B,
0x56,
0xD5,
0x00,
0x00,
0x00,
0x01,
0x00,
0x37,
0x35,
0x31,
0x31,
0x31,
0x35,
0x38,
0x37,
0x39,
0x38,
0x34,
0x39,
0x47,
0x65,
0x6E,
0x75,
0x69,
0x6E,
0x65,
0x20,
0x4E,
0x56,
0x49,
0x44,
0x49,
0x41,
0x20,
0x43,
0x65,
0x72,
0x74,
0x69,
0x66,
0x69,
0x65,
0x64,
0x20,
0x47,
0x53,
0x79,
0x6E,
0x63,
0x20,
0x52,
0x65,
0x61,
0x64,
0x79,
0x20,
0x50,
0x6C,
0x61,
0x74,
0x66,
0x6F,
0x72,
0x6D,
0x20,
0x66,
0x6F,
0x72,
0x20,
0x43,
0x4C,
0x45,
0x56,
0x4F,
0x20,
0x32,
0x30,
0x30,
0x35,
0x39,
0x30,
0x38,
0x38,
0x30,
0x20,
0x20,
0x20,
0x20,
0x20,
0x20,
0x2D,
0x20,
0x31,
0x39,
0x27,
0x3B,
0x36,
0x28,
0x53,
0x5E,
0x26,
0x2B,
0x35,
0x39,
0x55,
0x56,
0x32,
0x30,
0x58,
0x44,
0x26,
0x32,
0x44,
0x5C,
0x23,
0x2E,
0x31,
0x39,
0x32,
0x49,
0x3E,
0x25,
0x3B,
0x41,
0x57,
0x50,
0x5A,
0x56,
0x2C,
0x3E,
0x5F,
0x38,
0x20,
0x2D,
0x20,
0x43,
0x6F,
0x70,
0x79,
0x72,
0x69,
0x67,
0x68,
0x74,
0x20,
0x32,
0x30,
0x31,
0x34,
0x20,
0x4E,
0x56,
0x49,
0x44,
0x49,
0x41,
0x20,
0x43,
0x6F,
0x72,
0x70,
0x6F,
0x72,
0x61,
0x74,
0x69,
0x6F,
0x6E,
0x20,
0x41,
0x6C,
0x6C,
0x20,
0x52,
0x69,
0x67,
0x68,
0x74,
0x73,
0x20,
0x52,
0x65,
0x73,
0x65,
0x72,
0x76,
0x65,
0x64,
0x2D,
0x35,
0x38,
0x39,
0x36,
0x38,
0x34,
0x30,
0x32,
0x39,
0x33,
0x38,
0x35,
0x28,
0x52,
0x29,
})
}
If (BFF0 == 0x4452) { // 'DR'
Printf(" Return GDK")
Return (Buffer (0xAA) {
0xB4,
0x6B,
0x02,
0x49,
0x41,
0x16,
0x1C,
0xD2,
0x52,
0x44,
0xAA,
0x00,
0x00,
0x00,
0x00,
0x01,
0x00,
0x00,
0x00,
0x00,
0xDE,
0x10,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x09,
0x00,
0x00,
0x00,
0x00,
0x00,
0x34,
0x00,
0x00,
0x00,
0x01,
0x00,
0x47,
0x00,
0x00,
0x00,
0x02,
0x00,
0x45,
0x00,
0x00,
0x00,
0x03,
0x00,
0x5A,
0x00,
0x00,
0x00,
0x04,
0x00,
0x58,
0x00,
0x00,
0x00,
0x05,
0x00,
0x56,
0x00,
0x00,
0x00,
0x06,
0x00,
0x54,
0x00,
0x00,
0x00,
0x07,
0x00,
0x52,
0x00,
0x00,
0x00,
0x08,
0x00,
0x50,
0x00,
0x00,
0x00,
0x01,
0x00,
0x00,
0x00,
0xD9,
0x1C,
0x04,
0x00,
0x00,
0x00,
0x02,
0x00,
0x00,
0x00,
0x41,
0x5D,
0xC9,
0x00,
0x01,
0x24,
0x2E,
0x00,
0x02,
0x00,
0xFF,
0x00,
0x00,
0x00,
0x00,
0x01,
0x00,
0x00,
0x00,
0xD9,
0x1C,
0x04,
0x00,
0x00,
0x00,
0x03,
0x00,
0x00,
0x00,
0xE0,
0x7C,
0x97,
0x01,
0xC1,
0x3D,
0x9C,
0x1B,
0x41,
0x60,
0x68,
0x9E,
0x35,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
})
}
}
If (Arg2 == 0x14) {
Printf(" Arg2 == 0x14, return backlight package")
Return (Package (9) {

2
src/mainboard/system76/bonw14/devicetree.cb
View File

@ -123,7 +123,7 @@ chip soc/intel/cannonlake
register "PcieRpEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
register "PcieRpHotPlug[0]" = "1"
register "PcieClkSrcUsage[6]" = "0"
register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
# PCI Express root port #5 x4, Clock 10 (USB 3.2)
register "PcieRpEnable[4]" = "1"

8
src/mainboard/system76/bonw14/gpio.h
View File

@ -141,7 +141,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N
PAD_CFG_TERM_GPO(GPP_F2, 0, UP_20K, PLTRST), // GPP_F2_TBT_RST#
PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), // GPP_F2_TBT_RST#
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2),
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
@ -200,7 +200,7 @@ static const struct pad_config gpio_table[] = {
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP),
PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP), // GPIO_TBT_RESET
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
@ -238,14 +238,14 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_K16, 0, UP_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_K16, 1, UP_20K, DEEP), // TBT_FORCE_PWR_R
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP),
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN
PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
PAD_CFG_TERM_GPO(GPP_K23, 0, NONE, PLTRST),
PAD_CFG_TERM_GPO(GPP_K23, 1, NONE, PLTRST), // TBT_RTD3_PWR_EN_R
};
#endif