mb/aopen/dxplplusu: Remove board
This board use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: Idf37ade31ddb55697df1a65062c092a0a485e175 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69114 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans
@@ -1,15 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config NORTHBRIDGE_INTEL_E7505
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bool
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if NORTHBRIDGE_INTEL_E7505
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config NORTHBRIDGE_SPECIFIC_OPTIONS
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def_bool y
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select NO_ECAM_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select NO_CBFS_MCACHE
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select LEGACY_SMP_INIT
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endif
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@@ -1,10 +0,0 @@
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
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ramstage-y += northbridge.c
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ramstage-y += memmap.c
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romstage-y += romstage.c
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romstage-y += raminit.c
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romstage-y += memmap.c
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endif
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@@ -1,78 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* e7505.h: PCI configuration space for the Intel E7501 memory controller
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*/
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#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H
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#define NORTHBRIDGE_INTEL_E7505_E7505_H
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/************ D0:F0 ************/
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// Register offsets
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#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */
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#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */
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#define PAM_0 0x59
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#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */
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#define DRB_ROW_1 0x61
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#define DRB_ROW_2 0x62
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#define DRB_ROW_3 0x63
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#define DRB_ROW_4 0x64
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#define DRB_ROW_5 0x65
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#define DRB_ROW_6 0x66
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#define DRB_ROW_7 0x67
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#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */
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#define DRT 0x78 /* DRAM Timing register, 32 bit */
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#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */
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#define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
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#define CKDIS 0x8C /* Clock disable register, 8 bit */
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#define SMRAMC 0x9D
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#define ESMRAMC 0x9E
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#define APSIZE 0xB4
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#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */
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#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */
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#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */
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#define SKPD 0xDE /* Scratchpad register, 16 bit */
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#define DVNP 0xE0 /* Device Not Present, 16 bit */
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#define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */
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// CAS# Latency bits in the DRAM Timing (DRT) register
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#define DRT_CAS_2_5 (0<<4)
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#define DRT_CAS_2_0 (1<<4)
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#define DRT_CAS_MASK (3<<4)
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// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register
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#define RAM_COMMAND_NOP (1<<4)
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#define RAM_COMMAND_PRECHARGE (2<<4)
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#define RAM_COMMAND_MRS (3<<4)
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#define RAM_COMMAND_EMRS (4<<4)
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#define RAM_COMMAND_CBR (6<<4)
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#define RAM_COMMAND_NORMAL (7<<4)
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#define DRC_DONE (1 << 29)
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// RCOMP Memory Map offsets
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// Conjecture based on apparent similarity between E7501 and 855PM
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// Intel doc. 252613-003 describes these for 855PM
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#define SMRCTL 0x20 /* System Memory RCOMP Control Register? */
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#define DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */
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#define CKESTR 0x31 /* Strength control for CKE signal group? */
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#define CSBSTR 0x32 /* Strength control for CS# signal group? */
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#define CKSTR 0x33 /* Strength control for CK signal group? */
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#define RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */
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/************ D0:F1 ************/
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// Register offsets
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#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */
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#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */
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#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */
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#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */
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/************ D1:F0 ************/
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#define APSIZE1 0x74
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#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */
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@@ -1,53 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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// Use simple device model for this file even in ramstage
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#define __SIMPLE_DEVICE__
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#include <device/pci_ops.h>
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <cpu/x86/mtrr.h>
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#include <program_loading.h>
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#include "e7505.h"
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void *cbmem_top_chipset(void)
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{
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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uintptr_t tolm;
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/* This is at 128 MiB boundary. */
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tolm = pci_read_config16(mch, TOLM) >> 11;
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tolm <<= 27;
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return (void *)tolm;
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}
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void northbridge_write_smram(u8 smram);
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void northbridge_write_smram(u8 smram)
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{
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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pci_write_config8(mch, SMRAMC, smram);
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/*
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* Choose to NOT set ROM as WP cacheable here.
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* Timestamps indicate the CPU this northbridge code is
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* connected to, performs better for memcpy() and un-lzma
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* operations when source is left as UC.
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*/
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pcf->skip_common_mtrr = 1;
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache CBMEM region as WB. */
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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}
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@@ -1,87 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <cpu/cpu.h>
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#include "e7505.h"
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static void mch_domain_read_resources(struct device *dev)
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{
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int idx;
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unsigned long tolmk;
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uint64_t tom, remapbase, remaplimit;
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struct device *mc_dev;
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pci_domain_read_resources(dev);
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mc_dev = pcidev_on_root(0, 0);
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if (!mc_dev)
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die("Could not find MCH device\n");
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tolmk = pci_read_config16(mc_dev, TOLM) >> 11;
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tolmk <<= 17;
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tom = pci_read_config8(mc_dev, DRB_ROW_7);
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tom <<= 26;
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/* Remapped region with a 64 MiB granularity in register
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definition. Limit is inclusive, so add one. */
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remapbase = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff;
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remapbase <<= 26;
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remaplimit = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff;
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remaplimit += 1;
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remaplimit <<= 26;
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/* Report the memory regions */
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idx = 10;
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ram_resource_kb(dev, idx++, 0, tolmk);
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mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
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ASSERT(tom == remapbase);
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upper_ram_end(dev, idx++, remaplimit);
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}
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static void mch_domain_set_resources(struct device *dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = mch_domain_read_resources,
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.set_resources = mch_domain_set_resources,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci = &pci_dev_ops_pci,
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};
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static void cpu_bus_init(struct device *dev)
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{
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initialize_cpus(dev->link_list);
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}
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static struct device_operations cpu_bus_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.init = cpu_bus_init,
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};
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static void enable_dev(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN) {
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dev->ops = &pci_domain_ops;
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}
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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}
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struct chip_operations northbridge_intel_e7505_ops = {
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CHIP_NAME("Intel E7505 Northbridge")
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.enable_dev = enable_dev,
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};
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File diff suppressed because it is too large
Load Diff
@@ -1,24 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef RAMINIT_H
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#define RAMINIT_H
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#include <stdint.h>
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#define MAX_DIMM_SOCKETS_PER_CHANNEL 4
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#define MAX_NUM_CHANNELS 2
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#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
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struct mem_controller {
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pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
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// SMBus addresses of DIMM slots for each channel,
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// in order from closest to MCH to furthest away
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// 0 == not present
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uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL];
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uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
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};
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void sdram_initialize(void);
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#endif /* RAMINIT_H */
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@@ -1,19 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cbmem.h>
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#include <arch/romstage.h>
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#include <southbridge/intel/i82801dx/i82801dx.h>
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#include <northbridge/intel/e7505/raminit.h>
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void mainboard_romstage_entry(void)
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{
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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i82801dx_early_init();
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sdram_initialize();
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cbmem_recovery(0);
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}
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