soc/intel/common/pch: Decouple CLIENT from BASE

In preparation to add a third option, have "Client" platforms select a
dedicated Kconfig option instead of the common "_BASE" option. Rewrite
the help texts to clarify what "Client" and "Server" mean, because the
terms refer to the type of silicon and not to the market segment. Some
uniprocessor (single-socket) servers are actually client platforms and
there are some multi-socket workstations based on a server platform.

Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This commit is contained in:
Angel Pons
2022-07-18 14:41:24 +02:00
committed by Felix Held
parent 9f45f06e0e
commit eb90c512ab
10 changed files with 28 additions and 27 deletions

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@@ -112,7 +112,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CSE_SEND_EOP_EARLY
select SOC_INTEL_CSE_SET_EOP

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@@ -105,7 +105,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2

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@@ -1,28 +1,32 @@
config SOC_INTEL_COMMON_PCH_CLIENT
bool
select SOC_INTEL_COMMON_PCH_BASE
help
Selected by "Client" platforms, i.e. desktops, workstations,
laptops, tablets... This also includes uniprocessor servers
based on the same silicon as desktops and workstations. The
"Client" platforms include additional IP blocks that are of
little to no use on servers.
config SOC_INTEL_COMMON_PCH_SERVER
bool
select SOC_INTEL_COMMON_PCH_BASE
help
Selected by "Server" platforms, i.e. multi-socket capable
platforms used in large servers and workstations, such as
those using the Lewisburg (C620) PCH.
config SOC_INTEL_COMMON_PCH_BASE
bool
depends on SOC_INTEL_COMMON_BLOCK
help
All common PCH code blocks between Gen-6 till latest-PCH should be
part of this directory. A SoC Kconfig might select this option to include
base PCH package while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Addition to that SoC
code now having option to select required base PCH block to include
common IP block.
config SOC_INTEL_COMMON_PCH_SERVER
def_bool n
depends on SOC_INTEL_COMMON_PCH_BASE
help
SERVER is a subset of the COMMON_PCH_BASE and limits support to
server PCH devices (ex:, Intel C620 - Lewisburg).
This option is meant to be selected by the specific options above.
if SOC_INTEL_COMMON_PCH_BASE
source "src/soc/intel/common/pch/*/Kconfig"
config PCH_SPECIFIC_BASE_OPTIONS
# Always include the BASE (SERVER) subset of devices
def_bool y
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CSE
@@ -48,9 +52,7 @@ config PCH_SPECIFIC_BASE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
config PCH_SPECIFIC_CLIENT_OPTIONS
# Include the CLIENT devices if this is not a SERVER
def_bool n if SOC_INTEL_COMMON_PCH_SERVER
def_bool y if !SOC_INTEL_COMMON_PCH_SERVER
def_bool SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_BLOCK_DSP
select SOC_INTEL_COMMON_BLOCK_GRAPHICS
select SOC_INTEL_COMMON_BLOCK_I2C

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@@ -56,7 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2

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@@ -54,7 +54,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2

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@@ -57,7 +57,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION

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@@ -77,7 +77,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_IOC
select SOC_INTEL_CSE_SET_EOP

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@@ -76,7 +76,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT

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@@ -76,7 +76,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_CSE_SET_EOP

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@@ -53,7 +53,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_ACPI
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_PCH_SERVER
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER