soc/intel/common/pch: Decouple CLIENT from BASE
In preparation to add a third option, have "Client" platforms select a dedicated Kconfig option instead of the common "_BASE" option. Rewrite the help texts to clarify what "Client" and "Server" mean, because the terms refer to the type of silicon and not to the market segment. Some uniprocessor (single-socket) servers are actually client platforms and there are some multi-socket workstations based on a server platform. Change-Id: I646729d709f60ca2b5e74df18c2b4e52f9b10e6b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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@@ -112,7 +112,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_BASECODE
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_CSE_SEND_EOP_EARLY
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select SOC_INTEL_CSE_SET_EOP
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@@ -105,7 +105,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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select SSE2
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@@ -1,28 +1,32 @@
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config SOC_INTEL_COMMON_PCH_CLIENT
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bool
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select SOC_INTEL_COMMON_PCH_BASE
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help
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Selected by "Client" platforms, i.e. desktops, workstations,
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laptops, tablets... This also includes uniprocessor servers
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based on the same silicon as desktops and workstations. The
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"Client" platforms include additional IP blocks that are of
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little to no use on servers.
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config SOC_INTEL_COMMON_PCH_SERVER
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bool
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select SOC_INTEL_COMMON_PCH_BASE
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help
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Selected by "Server" platforms, i.e. multi-socket capable
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platforms used in large servers and workstations, such as
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those using the Lewisburg (C620) PCH.
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config SOC_INTEL_COMMON_PCH_BASE
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bool
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depends on SOC_INTEL_COMMON_BLOCK
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help
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All common PCH code blocks between Gen-6 till latest-PCH should be
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part of this directory. A SoC Kconfig might select this option to include
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base PCH package while building new SOC block. Currently majority of
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common IP code blocks are part of soc/intel/common/block/ and
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SoC Kconfig just select those Kconfig option. Addition to that SoC
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code now having option to select required base PCH block to include
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common IP block.
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config SOC_INTEL_COMMON_PCH_SERVER
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def_bool n
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depends on SOC_INTEL_COMMON_PCH_BASE
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help
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SERVER is a subset of the COMMON_PCH_BASE and limits support to
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server PCH devices (ex:, Intel C620 - Lewisburg).
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This option is meant to be selected by the specific options above.
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if SOC_INTEL_COMMON_PCH_BASE
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source "src/soc/intel/common/pch/*/Kconfig"
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config PCH_SPECIFIC_BASE_OPTIONS
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# Always include the BASE (SERVER) subset of devices
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def_bool y
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CSE
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@@ -48,9 +52,7 @@ config PCH_SPECIFIC_BASE_OPTIONS
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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config PCH_SPECIFIC_CLIENT_OPTIONS
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# Include the CLIENT devices if this is not a SERVER
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def_bool n if SOC_INTEL_COMMON_PCH_SERVER
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def_bool y if !SOC_INTEL_COMMON_PCH_SERVER
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def_bool SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_BLOCK_DSP
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select SOC_INTEL_COMMON_BLOCK_GRAPHICS
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select SOC_INTEL_COMMON_BLOCK_I2C
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@@ -56,7 +56,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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select SSE2
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@@ -54,7 +54,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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select SSE2
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@@ -57,7 +57,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_CSE_SET_EOP
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select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
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@@ -77,7 +77,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_BASECODE
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_BLOCK_IOC
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select SOC_INTEL_CSE_SET_EOP
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@@ -76,7 +76,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_NHLT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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@@ -76,7 +76,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
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select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
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select SOC_INTEL_COMMON_FSP_RESET
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_CLIENT
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select SOC_INTEL_COMMON_RESET
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_CSE_SET_EOP
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@@ -53,7 +53,6 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_PCH_BASE
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select SOC_INTEL_COMMON_PCH_SERVER
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_MONOTONIC_TIMER
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