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Correct darp7 PL2

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Change-Id: I51f047b62a8a2eadcaf89a4c6e6041d5bb9d1331
This commit is contained in:
Jeremy Soller
2021-01-21 09:01:11 -07:00
parent 53ff179883
commit edd97f35bd
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/system76/darp7/devicetree.cb
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@@ -25,13 +25,13 @@ chip soc/intel/tigerlake
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 28, .tdp_pl1_override = 28,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 51, .tdp_pl2_override = 40,
}" }"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
.tdp_pl1_override = 28, .tdp_pl1_override = 28,
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
.tdp_pl2_override = 51, .tdp_pl2_override = 40,
}" }"
# Finalize (soc/intel/tigerlake/finalize.c) # Finalize (soc/intel/tigerlake/finalize.c)