sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add AMD SB900 CIMx code

Browse Source 
This code is added to support the AMD SB900 southbridge.

Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/41
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
efdesign98
2011-06-16 16:39:30 -07:00
committed by Marc Jones
parent b0969d65e6
commit ee39ea7e7e
38 changed files with 15237 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

179
src/vendorcode/amd/cimx/sb900/AcpiLib.c Executable file
View File

@ -0,0 +1,179 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
//
//
// Routine Description:
//
// Locate ACPI table
//
// Arguments:
//
// Signature - table signature
//
//Returns:
//
// pointer to ACPI table
//
//
VOID*
ACPI_LocateTable (
IN unsigned int Signature
)
{
UINT32 i;
UINT32* RsdPtr;
UINT32* Rsdt;
UINTN tableOffset;
DESCRIPTION_HEADER* CurrentTable;
RsdPtr = (UINT32*) (UINTN)0xe0000;
Rsdt = NULL;
do {
// if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) {
// if ( (*RsdPtr == 0x52534420) && (*(RsdPtr + 1) == 0x50545220) ) {
if ( (*RsdPtr == 0x20445352) && (*(RsdPtr + 1) == 0x20525450) ) {
Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress;
break;
}
RsdPtr += 4;
} while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 );
if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) {
for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) {
tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4);
CurrentTable = (DESCRIPTION_HEADER*)tableOffset;
if ( CurrentTable->Signature == Signature ) {
return CurrentTable;
}
}
}
return NULL;
}
//
//
// Routine Description:
//
// Update table checksum
//
// Arguments:
//
// TablePtr - table pointer
//
// Returns:
//
// none
//
//
VOID
ACPI_SetTableChecksum (
IN VOID* TablePtr
)
{
UINT8 Checksum;
Checksum = 0;
((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
Checksum = ACPI_GetTableChecksum (TablePtr);
((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8) (0x100 - Checksum);
}
//
//
// Routine Description:
//
// Get table checksum
//
// Arguments:
//
// TablePtr - table pointer
//
// Returns:
//
// none
//
//
UINT8
ACPI_GetTableChecksum (
IN VOID* TablePtr
)
{
return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
}
UINT8
GetByteSum (
IN VOID* pData,
IN UINT32 Length
)
{
UINT32 i;
UINT8 Checksum;
Checksum = 0;
for ( i = 0; i < Length; i++ ) {
Checksum = Checksum + (*((UINT8*)pData + i));
}
return Checksum;
}
VOID
GetSbAcpiMmioBase (
OUT UINT32* AcpiMmioBase
)
{
UINT32 Value16;
ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16);
*AcpiMmioBase = Value16 << 16;
}
VOID
GetSbAcpiPmBase (
OUT UINT16* AcpiPmBase
)
{
ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);
}
VOID
SetAcpiPma (
IN UINT8 pmaControl
)
{
UINT16 pmaBase;
UINT16 dwValue;
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
dwValue &= ~BIT6;
WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74, AccWidthUint16, &dwValue);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, &pmaBase);
WriteIo8 (pmaBase, pmaControl);
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, ~BIT7, pmaControl << 7);
}

62
src/vendorcode/amd/cimx/sb900/AcpiLib.h Executable file
View File

@ -0,0 +1,62 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
/**
* RSDP - ACPI 2.0 table RSDP
*/
typedef struct _RSDP {
unsigned long long Signature; ///< RSDP signature "RSD PTR"
unsigned char Checksum; ///< checksum of the first 20 bytes
unsigned char OEMID[6]; ///< OEM ID, "LXBIOS"
unsigned char Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
unsigned int RsdtAddress; ///< physical address of RSDT
unsigned int Length; ///< total length of RSDP (including extended part)
unsigned long long XsdtAddress; ///< physical address of XSDT
unsigned char ExtendedChecksum; ///< chechsum of whole table
unsigned char Reserved[3]; ///< Reserved
} RSDP;
/// DESCRIPTION_HEADER - ACPI common table header
typedef struct _DESCRIPTION_HEADER {
unsigned int Signature; ///< ACPI signature (4 ASCII characters)
unsigned int Length; ///< Length of table, in bytes, including header
unsigned char Revision; ///< ACPI Specification minor version #
unsigned char Checksum; ///< To make sum of entire table == 0
unsigned char OEMID[6]; ///< OEM identification
unsigned char OEMTableID[8]; ///< OEM table identification
unsigned int OEMRevision; ///< OEM revision number
unsigned int CreatorID; ///< ASL compiler vendor ID
unsigned int CreatorRevision; ///< ASL compiler revision number
} DESCRIPTION_HEADER;
void* ACPI_LocateTable (IN unsigned int Signature);
void ACPI_SetTableChecksum (IN void* TablePtr);
unsigned char ACPI_GetTableChecksum (IN void* TablePtr);
unsigned char GetByteSum (IN void* pData, IN unsigned int Length);

89
src/vendorcode/amd/cimx/sb900/AmdLib.c Executable file
View File

@ -0,0 +1,89 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
UINT8
getNumberOfCpuCores (
OUT VOID
)
{
UINT8 Result;
Result = 1;
Result = ReadNumberOfCpuCores ();
return Result;
}
UINT32
readAlink (
IN UINT32 Index
)
{
UINT32 Data;
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data);
//Clear Index
Index = 0;
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
return Data;
}
VOID
writeAlink (
IN UINT32 Index,
IN UINT32 Data
)
{
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data);
//Clear Index
Index = 0;
WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);
}
VOID
rwAlink (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 AccessType;
AccessType = Index & 0xE0000000;
if (AccessType == (AXINDC << 29)) {
writeAlink ((SB_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF);
Index = (SB_AX_DATAC_REG34 | AccessType);
} else if (AccessType == (AXINDP << 29)) {
writeAlink ((SB_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF);
Index = (SB_AX_DATAP_REG3C | AccessType);
}
writeAlink (Index, ((readAlink (Index) & AndMask) | OrMask) );
}

336
src/vendorcode/amd/cimx/sb900/AmdSbLib.c Executable file
View File

@ -0,0 +1,336 @@
/**
* @file
*
* Southbridge IO access common routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
/**< SbStall - Reserved */
VOID
SbStall (
IN UINT32 uSec
)
{
UINT16 timerAddr;
UINT32 startTime;
UINT32 elapsedTime;
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
if ( timerAddr == 0 ) {
uSec = uSec / 2;
while ( uSec != 0 ) {
ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime));
uSec--;
}
} else {
ReadIO (timerAddr, AccWidthUint32, &startTime);
for ( ;; ) {
ReadIO (timerAddr, AccWidthUint32, &elapsedTime);
if ( elapsedTime < startTime ) {
elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
} else {
elapsedTime = elapsedTime - startTime;
}
if ( (elapsedTime * 28 / 100) > uSec ) {
break;
}
}
}
}
/**< cimSbStall - Reserved */
VOID
cimSbStall (
IN UINT32 uSec
)
{
UINT16 timerAddr;
UINT32 startTime;
UINT32 elapsedTime;
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);
if ( timerAddr == 0 ) {
uSec = uSec / 2;
while ( uSec != 0 ) {
ReadIo8 (0x80);
uSec--;
}
} else {
startTime = ReadIo32 (timerAddr);
for ( ;; ) {
elapsedTime = ReadIo32 (timerAddr);
if ( elapsedTime < startTime ) {
elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;
} else {
elapsedTime = elapsedTime - startTime;
}
if ( (elapsedTime * 28 / 100) > uSec ) {
break;
}
}
}
}
/**< SbReset - Reserved */
VOID
SbReset ()
{
RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);
}
/**< outPort80 - Reserved */
VOID
outPort80 (
IN UINT32 pcode
)
{
WriteIO (0x80, AccWidthUint8, &pcode);
return;
}
/**< outPort1080 - Reserved */
VOID
outPort1080 (
IN UINT32 pcode
)
{
WriteIo32 (0x1080, pcode);
return;
}
/**< AmdSbCopyMem - Reserved */
VOID
AmdSbCopyMem (
IN VOID* pDest,
IN VOID* pSource,
IN UINTN Length
)
{
UINTN i;
UINT8 *Ptr;
UINT8 *Source;
Ptr = (UINT8*)pDest;
Source = (UINT8*)pSource;
for (i = 0; i < Length; i++) {
*Ptr = *Source;
Source++;
Ptr++;
}
}
/** GetRomSigPtr - Reserved **/
VOID*
GetRomSigPtr (
IN UINTN* RomSigPtr
)
{
UINTN RomPtr;
UINT32 RomSig;
RomPtr = 0xFFF20000; // 1M
ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
if ( RomSig != 0x55AA55AA ) {
RomPtr = 0xFFE20000; //2M
ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
if ( RomSig != 0x55AA55AA ) {
RomPtr = 0xFFC20000; //4M
ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
if ( RomSig != 0x55AA55AA ) {
RomPtr = 0xFF820000; //8M
ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
if ( RomSig != 0x55AA55AA ) {
RomPtr = 0xFF020000; //16M
ReadMEM ((UINT32)RomPtr, AccWidthUint32, &RomSig);
if ( RomSig != 0x55AA55AA ) {
RomPtr = 0x0; // not found
}
}
}
}
}
*RomSigPtr = RomPtr;
return RomSigPtr;
}
VOID
RWXhciIndReg (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 IndReg;
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
IndReg &= AndMask;
IndReg |= OrMask;
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
#ifndef XHCI_SUPPORT_ONE_CONTROLLER
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
IndReg &= AndMask;
IndReg |= OrMask;
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
#endif
}
VOID
RWXhci0IndReg (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 IndReg;
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
IndReg &= AndMask;
IndReg |= OrMask;
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
}
VOID
RWXhci1IndReg (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 IndReg;
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x48, AccWidthUint32, &Index);
ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
IndReg &= AndMask;
IndReg |= OrMask;
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x4C, AccWidthUint32, &IndReg);
}
VOID
AcLossControl (
IN UINT8 AcLossControlValue
)
{
AcLossControlValue &= 0x03;
AcLossControlValue |= BIT2;
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG5B, AccWidthUint8, 0xF0, AcLossControlValue);
}
VOID
SbVgaInit (
VOID
)
{
// OBS194249 Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
//
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xff, BIT5 );
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0x00, 0x17 );
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3)));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0x00, 0x16 );
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0x0f, ((DACADJ & 0x0f) << 4));
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff);
*((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08;
*((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01;
//RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, ~(BIT5), 0 );
}
VOID
RecordSbConfigPtr (
IN UINT32 SbConfigPtr
)
{
RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 0) & 0xFF) );
RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 8) & 0xFF) );
RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 16) & 0xFF) );
RWMEM (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccWidthUint8, 0, (UINT8) ((SbConfigPtr >> 24) & 0xFF) );
}
VOID
SbGpioInit (
IN SB_GPIO_INIT_ENTRY *SbGpioInitTable
)
{
while ( SbGpioInitTable->GpioPin < 0xFF ) {
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SbGpioInitTable->GpioPin, AccWidthUint8, 0, SbGpioInitTable->GpioMux );
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpioInitTable->GpioPin, AccWidthUint8, ~ (BIT5 + BIT6), ((SbGpioInitTable->GpioOutEnB + (SbGpioInitTable->GpioOut << 1)) << 5) );
SbGpioInitTable ++;
}
}
VOID
SbGpioControl (
IN SB_GPIO_CONTROL_ENTRY *SbGpio
)
{
UINT8 GpioCurrent;
ReadMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpio->GpioPin, AccWidthUint8, &GpioCurrent );
if ((GpioCurrent & BIT5) == 0) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SbGpio->GpioPin, AccWidthUint8, ~ BIT6, (SbGpio->GpioControl << 6) );
}
GpioCurrent &= BIT7;
SbGpio->GpioControl = GpioCurrent >> 7;
}
VOID
SbFlashUsbSmi (
VOID
)
{
if ( ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) & (BIT4) ) {
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) &= ~ (BIT4);
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) |= (BIT4);
}
}
VOID
SbEnableUsbIrq1Irq12ToPicApic (
VOID
)
{
ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED) |= (BIT1);
}

112
src/vendorcode/amd/cimx/sb900/AmdSbLib.h Executable file
View File

@ -0,0 +1,112 @@
/**
* @file
*
* Southbridge IO access common routine define file
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
//AMDSBLIB Routines
/*--------------------------- Documentation Pages ---------------------------*/
/**< SbStall - Reserved */
void SbStall (IN unsigned int uSec);
/**< cimSbStall - Reserved */
void cimSbStall (IN unsigned int uSec);
/**< SbReset - Reserved */
void SbReset (void);
/**< outPort80 - Reserved */
void outPort80 (IN unsigned int pcode);
/**< outPort80 - Reserved */
void outPort1080 (IN unsigned int pcode);
/**< getEfuseStatue - Reserved */
void getEfuseStatus (IN void* Value);
/**< getEfuseByte - Reserved */
unsigned char getEfuseByte (IN unsigned char Index);
/**< AmdSbDispatcher - Reserved */
AGESA_STATUS AmdSbDispatcher (IN void *pConfig);
/**< AmdSbCopyMem - Reserved */
void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length);
/**< GetRomSigPtr - Reserved */
void* GetRomSigPtr (IN unsigned int* RomSigPtr);
/**< RWXhciIndReg - Reserved */
void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
/**< RWXhciIndReg - Reserved */
void RWXhci0IndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
/**< RWXhciIndReg - Reserved */
void RWXhci1IndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
/**< AcLossControl - Reserved */
void AcLossControl (IN unsigned char AcLossControlValue);
/**< SbVgaInit - Reserved */
void SbVgaInit (void);
/**< RecordSbConfigPtr - Reserved */
void RecordSbConfigPtr (IN unsigned int SbConfigPtr);
/**< SbGpioInit - Reserved */
void
SbGpioInit (
IN SB_GPIO_INIT_ENTRY *SbGpioInitTable
);
/**< SbGpioControl - Reserved */
void
SbGpioControl (
IN SB_GPIO_CONTROL_ENTRY *SbGpio
);
/**< SbFlashUsbSmi - Reserved */
void SbFlashUsbSmi (void);
/**< SbEnableUsbIrq1Irq12ToPicApic - Reserved */
void SbEnableUsbIrq1Irq12ToPicApic (void);

517
src/vendorcode/amd/cimx/sb900/Azalia.c Executable file
View File

@ -0,0 +1,517 @@
/**
* @file
*
* Config Southbridge HD Audio Controller
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
//
// Declaration of local functions
//
VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum);
VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0);
/**
* Pin Config for ALC880, ALC882 and ALC883.
*
*
*
*/
CODECENTRY AzaliaCodecAlc882Table[] =
{
{0x14, 0x01014010},
{0x15, 0x01011012},
{0x16, 0x01016011},
{0x17, 0x01012014},
{0x18, 0x01A19030},
{0x19, 0x411111F0},
{0x1a, 0x01813080},
{0x1b, 0x411111F0},
{0x1C, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x01441150},
{0x1f, 0x01C46160},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0262.
*
*
*
*/
CODECENTRY AzaliaCodecAlc262Table[] =
{
{0x14, 0x01014010},
{0x15, 0x411111F0},
{0x16, 0x411111F0},
{0x18, 0x01A19830},
{0x19, 0x02A19C40},
{0x1a, 0x01813031},
{0x1b, 0x02014C20},
{0x1c, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x0144111E},
{0x1f, 0x01C46150},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0269.
*
*
*
*/
CODECENTRY AzaliaCodecAlc269Table[] =
{
{0x12, 0x99A308F0},
{0x14, 0x99130010},
{0x15, 0x0121101F},
{0x16, 0x99036120},
{0x18, 0x01A19850},
{0x19, 0x99A309F0},
{0x1a, 0x01813051},
{0x1b, 0x0181405F},
{0x1d, 0x40134601},
{0x1e, 0x01442130},
{0x11, 0x99430140},
{0x20, 0x0030FFFF},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0861.
*
*
*
*/
CODECENTRY AzaliaCodecAlc861Table[] =
{
{0x01, 0x8086C601},
{0x0B, 0x01014110},
{0x0C, 0x01813140},
{0x0D, 0x01A19941},
{0x0E, 0x411111F0},
{0x0F, 0x02214420},
{0x10, 0x02A1994E},
{0x11, 0x99330142},
{0x12, 0x01451130},
{0x1F, 0x411111F0},
{0x20, 0x411111F0},
{0x23, 0x411111F0},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0889.
*
*
*
*/
CODECENTRY AzaliaCodecAlc889Table[] =
{
{0x11, 0x411111F0},
{0x14, 0x01014010},
{0x15, 0x01011012},
{0x16, 0x01016011},
{0x17, 0x01013014},
{0x18, 0x01A19030},
{0x19, 0x411111F0},
{0x1a, 0x411111F0},
{0x1b, 0x411111F0},
{0x1C, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x01442150},
{0x1f, 0x01C42160},
{0xff, 0xffffffff}
};
/**
* Pin Config for ADI1984.
*
*
*
*/
CODECENTRY AzaliaCodecAd1984Table[] =
{
{0x11, 0x0221401F},
{0x12, 0x90170110},
{0x13, 0x511301F0},
{0x14, 0x02A15020},
{0x15, 0x50A301F0},
{0x16, 0x593301F0},
{0x17, 0x55A601F0},
{0x18, 0x55A601F0},
{0x1A, 0x91F311F0},
{0x1B, 0x014511A0},
{0x1C, 0x599301F0},
{0xff, 0xffffffff}
};
/**
* FrontPanel Config table list
*
*
*
*/
CODECENTRY FrontPanelAzaliaCodecTableList[] =
{
{0x19, 0x02A19040},
{0x1b, 0x02214020},
{0xff, 0xffffffff}
};
/**
* Current HD Audio support codec list
*
*
*
*/
CODECTBLLIST azaliaCodecTableList[] =
{
{0x010ec0880, &AzaliaCodecAlc882Table[0]},
{0x010ec0882, &AzaliaCodecAlc882Table[0]},
{0x010ec0883, &AzaliaCodecAlc882Table[0]},
{0x010ec0885, &AzaliaCodecAlc882Table[0]},
{0x010ec0889, &AzaliaCodecAlc889Table[0]},
{0x010ec0262, &AzaliaCodecAlc262Table[0]},
{0x010ec0269, &AzaliaCodecAlc269Table[0]},
{0x010ec0861, &AzaliaCodecAlc861Table[0]},
{0x011d41984, &AzaliaCodecAd1984Table[0]},
{ (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}
};
/**
* azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
if ( pConfig->AzaliaController == 1 ) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0);
if ( pConfig->BuildParameters.HdAudioMsi) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8);
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16);
}
}
}
/**
* azaliaInitAfterPciEnum - Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
azaliaInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 Data;
UINT8 i;
UINT8 dbEnableAzalia;
UINT8 dbPinRouting;
UINT8 dbChannelNum;
UINT8 dbTempVariable;
UINT16 dwTempVariable;
UINT32 ddBAR0;
UINT32 ddTempVariable;
dbEnableAzalia = 0;
dbChannelNum = 0;
dbTempVariable = 0;
dwTempVariable = 0;
ddBAR0 = 0;
ddTempVariable = 0;
if ( pConfig->AzaliaController == 1 ) {
return;
}
if ( pConfig->AzaliaController != 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
}
ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
if ( ddBAR0 != 0 ) {
if ( ddBAR0 != 0xFFFFFFFF ) {
ddBAR0 &= ~(0x03FFF);
dbEnableAzalia = 1;
TRACE ((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
}
}
}
if ( dbEnableAzalia ) {
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 0);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 2);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 4);
pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 = 0x03 & (pConfig->AZALIACONFIG.AzaliaSdinPin >> 6);
// Get SDIN Configuration
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);
}
if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);
}
// INT#A Azalia resource
Data = 0x93; // Azalia APIC index
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
Data = 0x10; // IRQ16 (INTA#)
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
i = 11;
do {
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable |= BIT0;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
SbStall (1000);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
i--;
} while ((! (dbTempVariable & BIT0)) && (i > 0) );
if ( i == 0 ) {
TRACE ((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
return;
}
SbStall (1000);
ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
if ( dwTempVariable & 0x0F ) {
TRACE ((DMSG_SB_TRACE, "CIMxSB - At least One Azalia CODEC found \n"));
//atleast one azalia codec found
dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;
do {
if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {
configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);
}
dbPinRouting >>= 2;
dbChannelNum++;
} while ( dbChannelNum != 4 );
} else {
TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
//No Azalia codec found
if ( pConfig->AzaliaController != 2 ) {
dbEnableAzalia = 0; //set flag to disable Azalia
}
}
}
if ( dbEnableAzalia ) {
//redo clear reset
do {
dwTempVariable = 0;
WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
dbTempVariable &= ~(BIT0);
WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
} while ( dbTempVariable & BIT0 );
if ( pConfig->AzaliaSnoop == 1 ) {
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0);
}
} else {
//disable Azalia controller
RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);
}
}
/**
* configureAzaliaPinCmd - Configuration HD Audio PIN Command
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] ddBAR0 HD Audio BAR0 base address.
* @param[in] dbChannelNum Channel Number.
*
*/
VOID
configureAzaliaPinCmd (
IN AMDSBCFG* pConfig,
IN UINT32 ddBAR0,
IN UINT8 dbChannelNum
)
{
UINT32 ddTempVariable;
UINT32 ddChannelNum;
CODECTBLLIST* ptempAzaliaOemCodecTablePtr;
CODECENTRY* tempAzaliaCodecEntryPtr;
if ( (pConfig->AzaliaPinCfg) != 1 ) {
return;
}
ddChannelNum = dbChannelNum << 28;
ddTempVariable = 0xF0000;
ddTempVariable |= ddChannelNum;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
SbStall (600);
ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) {
ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]);
} else {
ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;
}
TRACE ((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %X \n", ptempAzaliaOemCodecTablePtr));
while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {
break;
} else {
++ptempAzaliaOemCodecTablePtr;
}
}
if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {
TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
TRACE ((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %X \n", tempAzaliaCodecEntryPtr));
if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {
tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);
}
configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
if ( pConfig->AzaliaFrontPanel != 1 ) {
if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) {
if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]);
} else {
tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr;
}
configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
}
}
}
}
/**
* configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
*
*
* @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer.
* @param[in] ddChannelNum HD Audio Channel Number.
* @param[in] ddBAR0 HD Audio BAR0 base address.
*
*/
VOID
configureAzaliaSetConfigD4Dword (
IN CODECENTRY* tempAzaliaCodecEntryPtr,
IN UINT32 ddChannelNum,
IN UINT32 ddBAR0
)
{
UINT8 dbtemp1;
UINT8 dbtemp2;
UINT8 i;
UINT32 ddtemp;
UINT32 ddtemp2;
ddtemp = 0;
ddtemp2 = 0;
while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
dbtemp1 = 0x20;
if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
dbtemp1 = 0x24;
}
ddtemp = tempAzaliaCodecEntryPtr->Nid;
ddtemp &= 0xff;
ddtemp <<= 20;
ddtemp |= ddChannelNum;
ddtemp |= (0x700 << 8);
for ( i = 4; i > 0; i-- ) {
do {
ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
} while ( ddtemp2 & BIT0 );
dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff);
ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2;
WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
SbStall (60);
}
++tempAzaliaCodecEntryPtr;
}
}

203
src/vendorcode/amd/cimx/sb900/Debug.c Executable file
View File

@ -0,0 +1,203 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#define COM_BASE_ADDRESS 0x3f8
#define DIVISOR 115200
#define LF 0x0a
#define CR 0x0d
#ifdef CIM_DEBUG
VOID SendBytePort (IN UINT8 Data);
VOID SendStringPort (IN CHAR8* pstr);
VOID ItoA (IN UINT32 Value, IN UINT32 Radix, IN CHAR8* pstr);
#ifndef CIM_DEBUG_LEVEL
#define CIM_DEBUG_LEVEL 0xf
#endif
VOID
TraceCode (
IN UINT32 Level,
IN UINT32 Code
)
{
if ( ! (Level & CIM_DEBUG_LEVEL) ) {
return;
}
#if CIM_DEBUG & 1
if ( Code != 0xFF ) {
WriteIO (0x80, AccWidthUint8, &Code);
}
#endif
}
VOID
TraceDebug (
IN UINT32 Level,
IN CHAR8 *Format,
)
{
CHAR8 temp[16];
va_list ArgList;
UINT32 Radix;
if ( ! (Level & CIM_DEBUG_LEVEL) ) {
return;
}
#if CIM_DEBUG & 2
ArgList = va_start (ArgList, Format);
Format = (CHAR8*) (Format);
while ( 1 ) {
if ( *Format == 0 ) {
break;
}
if ( *Format == ' % ' ) {
Radix = 0;
if ( *(Format + 1) == 's' || *(Format + 1) == 'S' ) {
SendStringPort ((CHAR8*) (va_arg (ArgList, CHAR8*)));
Format += 2;
continue;
}
if ( *(Format + 1) == 'd' || *(Format + 1) == 'D' ) {
Radix = 10;
}
if ( *(Format + 1) == 'x' || *(Format + 1) == 'X' ) {
Radix = 16;
}
if ( Radix ) {
ItoA (va_arg (ArgList, intqq), Radix, temp);
SendStringPort (temp);
Format += 2;
continue;
}
}
SendBytePort (*Format);
if ( *(Format) == 0x0a ) {
SendBytePort (0x0d);
}
Format++;
}
va_end (ArgList);
#endif
}
VOID
ItoA (
IN UINT32 Value,
IN UINT32 Radix,
IN CHAR8* pstr
)
{
CHAR8* tsptr;
CHAR8* rsptr;
CHAR8 ch1;
CHAR8 ch2;
UINT32 Reminder;
tsptr = pstr;
rsptr = pstr;
//Create String
do {
Reminder = Value % Radix;
Value = Value / Radix;
if ( Reminder < 0xa ) {
*tsptr = Reminder + '0';
} else {
*tsptr = Reminder - 0xa + 'a';
}
tsptr++;
} while ( Value );
//Reverse String
*tsptr = 0;
tsptr--;
while ( tsptr > rsptr ) {
ch1 = *tsptr;
ch2 = *rsptr;
*rsptr = ch1;
*tsptr = ch2;
tsptr--;
rsptr++;
}
}
VOID
InitSerialOut (
)
{
UINT8 Data;
UINT16 Divisor;
Data = 0x87;
WriteIO (COM_BASE_ADDRESS + 0x3, AccWidthUint8, &Data);
Divisor = 115200 / DIVISOR;
Data = Divisor & 0xFF;
WriteIO (COM_BASE_ADDRESS + 0x00, AccWidthUint8, &Data);
Data = Divisor >> 8;
WriteIO (COM_BASE_ADDRESS + 0x01, AccWidthUint8, &Data);
Data = 0x07;
WriteIO (COM_BASE_ADDRESS + 0x3, AccWidthUint8, &Data);
}
VOID
SendStringPort (
IN CHAR8* pstr
)
{
while ( *pstr! = 0 ) {
SendBytePort (*pstr);
pstr++;
}
}
VOID
SendBytePort (
IN UINT8 Data
)
{
INT8 Count;
UINT8 Status;
Count = 80;
do {
ReadIO ((COM_BASE_ADDRESS + 0x05), AccWidthUint8, &Status);
if ( Status == 0xff ) {
break;
}
// Loop port is ready
} while ( (Status & 0x20) == 0 && (--Count) != 0 );
WriteIO (COM_BASE_ADDRESS + 0x00, AccWidthUint8, &Data);
}
#endif

261
src/vendorcode/amd/cimx/sb900/Dispatcher.c Executable file
View File

@ -0,0 +1,261 @@
/**
* @file
*
* Function dispatcher.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
//
// Declaration of local functions
//
VOID saveConfigPointer (IN AMDSBCFG* pConfig);
VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);
VOID* LocateImage (IN UINT64 Signature);
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/**
* AmdSbDispatcher - Dispatch Southbridge function
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
AGESA_STATUS
AmdSbDispatcher (
IN VOID *pConfig
)
{
AGESA_STATUS Status;
UINT64 tdValue;
#ifdef B1_IMAGE
VOID *pAltImagePtr;
CIM_IMAGE_ENTRY AltImageEntry;
pAltImagePtr = NULL;
#endif
Status = AGESA_UNSUPPORTED;
tdValue = 0x313141324E4448ull;
//#if CIM_DEBUG
// InitSerialOut ();
//#endif
Status = AGESA_UNSUPPORTED;
TRACE ((DMSG_SB_TRACE, "CIM - Hudson-2 Entry\n"));
#ifdef B1_IMAGE
if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {
if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {
pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);
}
if ( pAltImagePtr == NULL ) {
pAltImagePtr = LocateImage ( tdValue );
}
if ( pAltImagePtr != NULL ) {
((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;
AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));
(*AltImageEntry) (pConfig);
return Status;
}
}
#endif
saveConfigPointer (pConfig);
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
sbPowerOnInit ((AMDSBCFG*) pConfig);
}
#ifndef B1_IMAGE
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
sbBeforePciInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
sbAfterPciInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) {
sbMidPostInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
sbLatePost ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
sbSmmService ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
sbSmmAcpiOn ((AMDSBCFG*)pConfig);
}
if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {
sbECfancontrolservice ((AMDSBCFG*)pConfig);
}
#endif
TRACE ((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
return Status;
}
/**
* LocateImage - Locate Southbridge CIMx module
*
*
*
* @param[in] Signature Southbridge CIMx image signature.
*
*/
VOID*
LocateImage (
IN UINT64 Signature
)
{
VOID *Result;
UINT32 ImagePtr;
ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);
while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {
#ifdef x64
12346789
#else
Result = VerifyImage (Signature, (VOID*) (__int64)ImagePtr);
#endif
if ( Result != NULL ) {
return Result;
}
ImagePtr -= IMAGE_ALIGN;
}
return NULL;
}
/**
* VerifyImage - Verify Southbridge CIMx module
*
*
* @param[in] Signature Southbridge CIMx image signature.
* @param[in] ImagePtr Southbridge CIMx image address.
*
*/
VOID*
VerifyImage (
IN UINT64 Signature,
IN VOID* ImagePtr
)
{
UINT16 *TempImagePtr;
UINT16 Sum;
UINT32 i;
Sum = 0;
// if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
if ( (*((UINT32*)ImagePtr) == Int32FromChar('D', 'M', 'A', '$') && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {
//GetImage Image size
TempImagePtr = (UINT16*)ImagePtr;
for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {
Sum = Sum + *TempImagePtr;
TempImagePtr++;
}
if ( Sum == 0 ) {
return ImagePtr;
}
}
return NULL;
}
/**
* saveConfigPointer - Verify Southbridge CIMx module
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
saveConfigPointer (
IN AMDSBCFG* pConfig
)
{
UINT8 dbReg;
UINT8 i;
UINT32 ddValue;
ddValue = (UINT32) (UINTN)pConfig;
dbReg = SB_ECMOS_REG08;
for ( i = 0; i <= 3; i++ ) {
WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue);
ddValue = (ddValue >> 8);
dbReg++;
}
}

128
src/vendorcode/amd/cimx/sb900/Ec.c Executable file
View File

@ -0,0 +1,128 @@
/**
* @file
*
* Config Southbridge EC Controller
*
* Init EC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#ifndef NO_EC_SUPPORT
/**
* Config EC controller during power-on
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
ecPowerOnInit (
IN AMDSBCFG* pConfig
)
{
//Enable config mode
EnterEcConfig ();
//Do settings for mailbox - logical device 0x09
RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port
RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port
RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
if ( pConfig->BuildParameters.EcKbd == ENABLED) {
//Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
//Disable LPC Decoding of port 60/64
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);
//Enable logical device 0x07 (Keyboard controller)
RWEC8 (0x07, 0x00, 0x07);
RWEC8 (0x30, 0x00, 0x01);
}
if (isImcEnabled () && ( pConfig->BuildParameters.EcChannel0 == ENABLED)) {
//Logical device 0x03
RWEC8 (0x07, 0x00, 0x03);
RWEC8 (0x60, 0x00, 0x00);
RWEC8 (0x61, 0x00, 0x62);
RWEC8 (0x30, 0x00, 0x01); //;Enable Device 3
}
//Enable EC (IMC) to generate SMI to BIOS
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);
ExitEcConfig ();
}
/**
* Config EC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
ecInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
AMDSBCFG* pTmp; // dummy code
pTmp = pConfig;
}
/**
* Prepare EC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
ecInitLatePost (
IN AMDSBCFG* pConfig
)
{
AMDSBCFG* pTmp; // dummy code
pTmp = pConfig;
}
#endif

66
src/vendorcode/amd/cimx/sb900/EcFan.h Executable file
View File

@ -0,0 +1,66 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
void WriteECmsg (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
void WaitForEcLDN9MailboxCmdAck (void);
void ReadECmsg (IN unsigned char Address, IN unsigned char OpFlag, OUT void* Value);
// IMC Message Register Software Interface
#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
#define MSG_SYS_TO_IMC 0x80
#define Fun_80 0x80
#define Fun_81 0x81
#define Fun_82 0x82
#define Fun_83 0x83
#define Fun_84 0x84
#define Fun_85 0x85
#define Fun_86 0x86
#define Fun_87 0x87
#define Fun_88 0x88
#define Fun_89 0x89
#define Fun_90 0x90
#define MSG_IMC_TO_SYS 0x81
#define MSG_REG0 0x82
#define MSG_REG1 0x83
#define MSG_REG2 0x84
#define MSG_REG3 0x85
#define MSG_REG4 0x86
#define MSG_REG5 0x87
#define MSG_REG6 0x88
#define MSG_REG7 0x89
#define MSG_REG8 0x8A
#define MSG_REG9 0x8B
#define MSG_REGA 0x8C
#define MSG_REGB 0x8D
#define MSG_REGC 0x8E
#define MSG_REGD 0x8F

285
src/vendorcode/amd/cimx/sb900/EcFanLib.c Executable file
View File

@ -0,0 +1,285 @@
/**
* @file
*
* Southbridge EC IO access common routine
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
VOID
ReadECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
OUT VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if (OpFlag == 0x02) OpFlag = 0x03;
WriteIo8((UINT16) (0x3E), Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
i = ReadIo8((UINT16) (0x3F)); // EC_LDN9_MAILBOX_BASE_ADDRESS
*((UINT8*) (Value)) = i;
}
VOID
WriteECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if (OpFlag == 0x02) OpFlag = 0x03;
WriteIo8(0x3E, Address); // EC_LDN9_MAILBOX_BASE_ADDRESS
i = *(UINT8*)Value;
WriteIo8(0x3F, i); // EC_LDN9_MAILBOX_BASE_ADDRESS
}
VOID
WaitForEcLDN9MailboxCmdAck (
VOID
)
{
UINT8 Msgdata;
UINT16 Delaytime;
Msgdata = 0;
for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
if ( Msgdata == 0xfa) {
break;
}
cimSbStall (1000); // Wait for 1ms
}
}
/**
* imcDisableSurebootTimer - IMC Disable Sureboot Timer.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
imcDisableSurebootTimer (
IN AMDSBCFG* pConfig
)
{
UINT8 Msgdata;
if (!(isImcEnabled ()) ) {
return; //IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
Msgdata = 0x94;
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
WaitForEcLDN9MailboxCmdAck ();
}
/**
* imcDisarmSurebootTimer - IMC Disarm Sureboot Timer.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
imcDisarmSurebootTimer (
IN AMDSBCFG* pConfig
)
{
imcDisableSurebootTimer (pConfig);
pConfig->imc.imcSureBootTimer = 0;
}
/**
* imcEnableSurebootTimer - IMC Enable Sureboot Timer.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
imcEnableSurebootTimer (
IN AMDSBCFG* pConfig
)
{
UINT8 Msgdata;
imcDisableSurebootTimer (pConfig);
Msgdata = 0x00;
if (!(isImcEnabled ()) || (pConfig->imc.imcSureBootTimer == 0)) {
return; //IMC is not enabled
}
WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
Msgdata = ( (pConfig->imc.imcSureBootTimer) << 6) -1;
WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
Msgdata = 0x94;
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
WaitForEcLDN9MailboxCmdAck ();
}
/**
* imcSleep - IMC Sleep.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
imcSleep (
IN AMDSBCFG* pConfig
)
{
UINT8 Msgdata;
if (!(isImcEnabled ()) ) {
return; //IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
Msgdata = 0xB4;
WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
Msgdata = 0x96;
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
WaitForEcLDN9MailboxCmdAck ();
}
/**
* imcWakeup - IMC Wakeup.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
imcWakeup (
IN AMDSBCFG* pConfig
)
{
UINT8 Msgdata;
if (!(isImcEnabled ()) ) {
return; //IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
Msgdata = 0xB5;
WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
Msgdata = 0x96;
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
WaitForEcLDN9MailboxCmdAck ();
}
/**
* imcIdle - IMC Idle.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
imcIdle (
IN AMDSBCFG* pConfig
)
{
UINT8 Msgdata;
if (!(isImcEnabled ()) ) {
return; //IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
Msgdata = 0x98;
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
WaitForEcLDN9MailboxCmdAck ();
}
VOID
imcThermalZoneEnable (
IN AMDSBCFG* pConfig
)
{
UINT8 Msgdata;
UINT8 ZoneNum;
BOOLEAN IsSendEcMsg;
if (!(isImcEnabled ()) ) {
return; //IMC is not enabled
}
for ( ZoneNum = 0; ZoneNum < 4; ZoneNum++ ) {
IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, 0, ZoneNum);
if (IsSendEcMsg) {
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
Msgdata = ZoneNum;
WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
Msgdata = 0x80;
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
WaitForEcLDN9MailboxCmdAck ();
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccWidthUint8, &Msgdata);
Msgdata = ZoneNum;
WriteECmsg (MSG_REG1, AccWidthUint8, &Msgdata);
ReadECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
Msgdata |= BIT0;
WriteECmsg (MSG_REG2, AccWidthUint8, &Msgdata);
Msgdata = 0x81;
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Msgdata);
WaitForEcLDN9MailboxCmdAck ();
}
}
}

189
src/vendorcode/amd/cimx/sb900/EcFanc.c Executable file
View File

@ -0,0 +1,189 @@
/*;********************************************************************************
;
;Copyright (c) 2011, Advanced Micro Devices, Inc.
;All rights reserved.
;
;Redistribution and use in source and binary forms, with or without
;modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
;THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
;ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
;DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
;(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
;LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
;ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
;SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
/**
* Table for Function Number
*
*
*
*
*/
UINT8 FunctionNumber[] =
{
Fun_81,
Fun_83,
Fun_85,
Fun_89,
};
/**
* Table for Max Thermal Zone
*
*
*
*
*/
UINT8 MaxZone[] =
{
4,
4,
4,
4,
};
/**
* Table for Max Register
*
*
*
*
*/
UINT8 MaxRegister[] =
{
MSG_REG9,
MSG_REGB,
MSG_REG9,
MSG_REGA,
};
/*-------------------------------------------------------------------------------
;Procedure: IsZoneFuncEnable
;
;Description: This routine will check every zone support function with BitMap from user define
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
BOOLEAN
IsZoneFuncEnable (
IN UINT16 Flag,
IN UINT8 func,
IN UINT8 Zone
)
{
return (BOOLEAN) (((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));
}
/*-------------------------------------------------------------------------------
;Procedure: sbECfancontrolservice
;
;Description: This routine service EC fan policy
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
VOID
sbECfancontrolservice (
IN AMDSBCFG* pConfig
)
{
UINT8 ZoneNum;
UINT8 FunNum;
UINT8 RegNum;
UINT8 * CurPoint;
UINT8 FunIndex;
BOOLEAN IsSendEcMsg;
if (!isImcEnabled ()) {
return; //IMC is not enabled
}
CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
if (IsSendEcMsg) {
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
CurPoint += 1;
}
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
WaitForEcLDN9MailboxCmdAck ();
} else {
CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
}
}
}
CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0;
for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);
if (IsSendEcMsg) {
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
if (RegNum == MSG_REG2) {
*CurPoint &= 0xFE;
}
WriteECmsg (RegNum, AccWidthUint8, CurPoint); //
CurPoint += 1;
}
WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number
WaitForEcLDN9MailboxCmdAck ();
} else {
CurPoint += (MaxRegister[FunIndex] - MSG_REG0 + 1);
}
}
}
}
/*-------------------------------------------------------------------------------
;Procedure: hwmImcInit
;
;Description: This routine Init EC fan policy
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
VOID
hwmImcInit (
IN AMDSBCFG* pConfig
)
{
imcWakeup ( pConfig);
if ( pConfig->hwm.hwmSbtsiAutoPoll == FALSE ) {
sbECfancontrolservice (pConfig);
}
}

153
src/vendorcode/amd/cimx/sb900/EcLib.c Executable file
View File

@ -0,0 +1,153 @@
/**
* @file
*
* Southbridge EC IO access common routine
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
// #ifndef NO_EC_SUPPORT
/*----------------------------------------------------------------------------------------*/
/**
* EnterEcConfig - Force EC into Config mode
*
*
*
*
*/
VOID
EnterEcConfig (
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
}
/*----------------------------------------------------------------------------------------*/
/**
* ExitEcConfig - Force EC exit Config mode
*
*
*
*
*/
VOID
ExitEcConfig (
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
}
/*----------------------------------------------------------------------------------------*/
/**
* ReadEC8 - Read EC register data
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Read Data Buffer
*
*/
VOID
ReadEC8 (
IN UINT8 Address,
IN UINT8* Value
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
/*----------------------------------------------------------------------------------------*/
/**
* WriteEC8 - Write date into EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Write Data Buffer
*
*/
VOID
WriteEC8 (
IN UINT8 Address,
IN UINT8* Value
)
{
UINT16 dwEcIndexPort;
ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
dwEcIndexPort &= ~(BIT0);
WriteIO (dwEcIndexPort, AccWidthUint8, &Address);
WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);
}
/*----------------------------------------------------------------------------------------*/
/**
* RWEC8 - Read/Write EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] AndMask - Data And Mask 8 bits
* @param[in] OrMask - Data OR Mask 8 bits
*
*/
VOID
RWEC8 (
IN UINT8 Address,
IN UINT8 AndMask,
IN UINT8 OrMask
)
{
UINT8 Result;
ReadEC8 (Address, &Result);
Result = (Result & AndMask) | OrMask;
WriteEC8 (Address, &Result);
}
// #endif

141
src/vendorcode/amd/cimx/sb900/Gec.c Executable file
View File

@ -0,0 +1,141 @@
/**
* @file
*
* Config Southbridge GEC controller
*
* Init GEC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
/**
* gecInitBeforePciEnum - Config GEC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
gecInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 cimSBGecDebugBus;
UINT8 cimSBGecPwr;
cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus;
cimSBGecPwr = (UINT8) pConfig->SBGecPwr;
#if (SB_CIMx_PARAMETER == 0 )
cimSBGecDebugBus = cimSBGecDebugBusDefault;
cimSBGecPwr = cimSBGecPwrDefault;
#endif
if ( pConfig->Cg2Pll == 1 ) {
pConfig->GecConfig = 1;
}
if ( pConfig->GecConfig == 0) {
// GEC Enabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5));
if ( cimSBGecDebugBus == 1) {
// GEC Debug Bus Enabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3);
} else {
// GEC Debug Bus Disabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00);
}
} else {
// GEC Disabled
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0);
//return; //return if GEC controller is disabled.
}
}
/**
* gecInitAfterPciEnum - Config GEC controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
gecInitAfterPciEnum (
IN AMDSBCFG* pConfig
)
{
VOID* GecRomAddress;
VOID* GecShadowRomAddress;
UINT32 ddTemp;
if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);
ddTemp = ddTemp & 0xFFFFFFF0;
RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29);
}
TRACE ((DMSG_SB_TRACE, "Exiting gec Init after PCI emulation\n"));
}
/**
* gecInitLatePost - Prepare GEC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
gecInitLatePost (
IN AMDSBCFG* pConfig
)
{
if ( !pConfig->GecConfig == 0) {
return; //return if GEC controller is disabled.
}
TRACE ((DMSG_SB_TRACE, "Exiting Prepare GEC controller to boot to OS\n"));
}

1109
src/vendorcode/amd/cimx/sb900/Gpp.c Executable file
View File

File diff suppressed because it is too large Load Diff

165
src/vendorcode/amd/cimx/sb900/GppHp.c Executable file
View File

@ -0,0 +1,165 @@
/**
* @file
*
* Config Southbridge GPP controller
*
* Init GPP features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************
*/
#include "SbPlatform.h"
#include "cbtypes.h"
//
// Declaration of external functions
//
VOID sbGppDynamicPowerSaving (IN AMDSBCFG* pConfig );
VOID sbGppForceGen1 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
VOID sbGppForceGen2 (IN AMDSBCFG* pConfig, IN CONST UINT8 ActivePorts);
UINT8 GppPortPollingLtssm (IN AMDSBCFG* pConfig, IN UINT8 ActivePorts, IN BOOLEAN IsGen2);
/**
* GPP hot plug handler
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] HpPort The hot plug port number.
*
*/
VOID
sbGppHotPlugSmiProcess (
IN AMDSBCFG* pConfig,
IN UINT32 HpPort
)
{
UINT8 FailedPort;
// First restore GPP pads if needed
if (pConfig->GppDynamicPowerSaving && pConfig->AlinkPhyPllPowerDown && pConfig->GppPhyPllPowerDown) {
rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0);
rwAlink (RC_INDXC_REG65, ~(UINT32) (0x101 << HpPort), 0);
SbStall (1000);
}
FailedPort = (UINT8) (1 << HpPort);
if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
if (GppPortPollingLtssm (pConfig, FailedPort, TRUE)) {
sbGppForceGen1 (pConfig, FailedPort);
FailedPort = GppPortPollingLtssm (pConfig, FailedPort, FALSE);
}
} else {
sbGppForceGen1 (pConfig, FailedPort);
FailedPort = GppPortPollingLtssm (pConfig, FailedPort, FALSE);
}
}
/**
* GPP hot-unplug handler
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] HpPort The hot plug port number.
*
*/
VOID
sbGppHotUnplugSmiProcess (
IN AMDSBCFG* pConfig,
IN UINT32 HpPort
)
{
pConfig->PORTCONFIG[HpPort].PortCfg.PortDetected = FALSE;
if (pConfig->GppGen2 && pConfig->GppGen2Strap) {
sbGppForceGen2 (pConfig, (UINT8) (1 << HpPort));
}
// 5.19.1 GPP Power Saving with Hot Unplug
if (pConfig->GppDynamicPowerSaving && pConfig->AlinkPhyPllPowerDown && pConfig->GppPhyPllPowerDown) {
rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17);
rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8);
rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)));
rwAlink (SB_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0);
// Finally re-configure GPP pads if needed
sbGppDynamicPowerSaving (pConfig);
}
}
/**
* SMI handler for GPP hot-plug
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] IsPlugged Is a card currently plugged in the GPP port?
*
*/
VOID
sbGppHotplugSmiCallback (
IN AMDSBCFG* pConfig,
IN BOOLEAN IsPlugged
)
{
UINT32 portNum;
UINT32 HpPort;
if (!pConfig->GppFunctionEnable) {
return;
}
HpPort = 0xff;
for (portNum = 0; portNum < MAX_GPP_PORTS; portNum++) {
if (pConfig->PORTCONFIG[portNum].PortCfg.PortHotPlug == TRUE) {
HpPort = portNum;
break;
}
}
if (HpPort == 0xff) {
return;
}
if (IsPlugged) {
outPort80 (0x9C);
sbGppHotPlugSmiProcess (pConfig, HpPort);
} else {
outPort80 (0x9D);
sbGppHotUnplugSmiProcess (pConfig, HpPort);
}
}

2068
src/vendorcode/amd/cimx/sb900/Hudson-2.h Executable file
View File

File diff suppressed because it is too large Load Diff

578
src/vendorcode/amd/cimx/sb900/Hwm.c Executable file
View File

@ -0,0 +1,578 @@
/**
* @file
*
* Southbridge Initial routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
//
// Declaration of local functions
//
VOID
hwmInitRegister (
IN AMDSBCFG* pConfig
);
VOID
hwmGetRawData (
IN AMDSBCFG* pConfig
);
VOID
hwmCaculate (
IN AMDSBCFG* pConfig
);
VOID
hwmGetCalibrationFactor (
IN AMDSBCFG* pConfig
);
VOID
hwmProcessParameter (
IN AMDSBCFG* pConfig
);
VOID
hwmSetRegister (
IN AMDSBCFG* pConfig
);
HWM_temp_par_struct tempParDefault[] = {
{ 5219, 27365 , 0 },
{ 5222, 27435 , 0 },
{ 5219, 27516 , BIT0 }, //High Ratio
{ 5221, 27580 , BIT1 }, //High Current
{ 5123, 27866 , 0 }
};
//#ifndef NO_HWM_SUPPORT
/**
* hwmInitRegister - Init Hardware Monitor Register.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmInitRegister (
IN AMDSBCFG* pConfig
)
{
UINT32 LinearRangeOutLimit;
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8, 0, 0x55);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8, 0, 0x55);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8, 0, 0x55);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8, 0, 0x55);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8, 0, 0x06);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8, 0, 0x06);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8, 0, 0x06);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8, 0, 0x06);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8, 0, 0x06);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8, 0, 0x01);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccWidthUint8, 0xff, 0x02);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8, 0, 0x05);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8, 0, 0x06);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8, 0, 0x42);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8, 0, 0xFF);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8, 0, 0x1F);
//2.13 HWM Sensor Clk
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8, 0, 0x0A);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8, 0, 0x00);
//2.9 Enhancement of FanOut0 Control
//check for fanLinearEnhanceEn
if (pConfig->hwm.fanLinearEnhanceEn == 0) {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT11, BIT11);
LinearRangeOutLimit = (UINT32) (pConfig->hwm.fanLinearRangeOutLimit);
LinearRangeOutLimit = LinearRangeOutLimit << 20;
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4, AccWidthUint32, 0xFF0FFFFF, LinearRangeOutLimit);
} else {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT11, 0);
}
//check for fanLinearHoldFix
if (pConfig->hwm.fanLinearHoldFix == 0) {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT20, BIT20);
} else {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG50, AccWidthUint32, ~ BIT20, 0);
}
}
/**
* hwmSbtsiAutoPolling - Hardware Monitor Auto Poll SB-TSI.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmSbtsiAutoPolling (
IN AMDSBCFG* pConfig
)
{
UINT8 dbValue;
UINT16 smbusBase;
smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
if (pConfig->hwm.hwmSbtsiAutoPoll == 1) {
hwmSbtsiAutoPollingPause (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), BIT2);
dbValue = 0xff;
WriteIO (smbusBase, AccWidthUint8, &dbValue);
dbValue = 0x08;
WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
dbValue = 0x09;
WriteIO (smbusBase + 3, AccWidthUint8, &dbValue);
dbValue = 0x98;
WriteIO (smbusBase + 4, AccWidthUint8, &dbValue);
if ( IsSbA11 () ) {
dbValue = 0x00;
} else {
dbValue = 0x20;
}
WriteIO (smbusBase + 5, AccWidthUint8, &dbValue);
dbValue = 0x48;
WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
ReadIO (smbusBase + 0, AccWidthUint8, &dbValue);
while ( dbValue & BIT0 ) {
ReadIO (smbusBase + 0, AccWidthUint8, &dbValue);
}
if ( IsSbA11 () ) {
dbValue = 0x09;
} else {
dbValue = 0x08;
}
WriteIO (smbusBase + 2, AccWidthUint8, &dbValue);
if ( IsSbA11 () ) {
dbValue = 0x01;
} else {
dbValue = 0x10;
}
WriteIO (smbusBase + 3, AccWidthUint8, &dbValue);
dbValue = 0x99;
WriteIO (smbusBase + 4, AccWidthUint8, &dbValue);
if ( IsSbA11 () ) {
dbValue = 0x0f;
WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
}
if ( IsSbA12Plus () ) {
dbValue = 0x80;
WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
dbValue = 0x01;
WriteIO (smbusBase + 0x17, AccWidthUint8, &dbValue);
dbValue = 0x81;
WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
}
//map SB-TSI to tempin0
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + SB_PMIO2_REG92, AccWidthUint8, ~BIT3, BIT3);
dbValue = 0x00;
WriteIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
pConfig->hwm.hwmSbtsiAutoPollStarted = TRUE;
} else {
hwmSbtsiAutoPollingOff (pConfig);
}
}
/**
* hwmSbtsiAutoPollingOff - Hardware Monitor Auto Poll SB-TSI
* Off.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmSbtsiAutoPollingOff (
IN AMDSBCFG* pConfig
)
{
UINT8 dbValue;
UINT16 smbusBase;
if ( pConfig->hwm.hwmEnable ) {
smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
dbValue = 0x00;
WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
hwmSbtsiAutoPollingPause (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0);
RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + SB_PMIO2_REG92, AccWidthUint8, ~BIT3, 0x00);
pConfig->hwm.hwmSbtsiAutoPollStarted = FALSE;
}
}
/**
* hwmSbtsiAutoPollingPause - Pause Hardware Monitor Auto Poll
* SB-TSI Off.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmSbtsiAutoPollingPause (
IN AMDSBCFG* pConfig
)
{
UINT8 dbValue;
UINT16 smbusBase;
if ( pConfig->hwm.hwmEnable && (pConfig->hwm.hwmSbtsiAutoPoll == 1) ) {
smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
dbValue = 0x01;
WriteIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
dbValue = 0x00;
while ( dbValue == 0x00 ) {
ReadIO (smbusBase + 0x16, AccWidthUint8, &dbValue);
}
}
}
/**
* hwmGetRawData - Hardware Monitor Get Raw Data.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmGetRawData (
IN AMDSBCFG* pConfig
)
{
UINT8 i;
UINT16 dwValue;
//_asm { jmp $ };
//fan speed
for ( i = 0; i < 5 ; i++ ) {
ReadPMIO2 (SB_PMIO2_REG69 + i * 5, AccWidthUint16, &dwValue);
if ( (dwValue & 0xFFC0) != 0xFFC0 ) {
pConfig->hwm.hwmCurrentRaw.fanSpeed[i] = dwValue;
} else {
pConfig->hwm.hwmCurrentRaw.fanSpeed[i] = 0xFFFF;
}
}
//temperatue
for ( i = 0; i < 5 ; i++ ) {
ReadPMIO2 (SB_PMIO2_REG95 + i * 4, AccWidthUint16, &dwValue);
if ( ( i == 1 ) || (dwValue > 0x4000) ) {
pConfig->hwm.hwmCurrentRaw.temperature[i] = dwValue;
}
}
//voltage
for ( i = 0; i < 8 ; i++ ) {
ReadPMIO2 (SB_PMIO2_REGB8 + i * 4, AccWidthUint16, &dwValue);
if ( (dwValue & 0xFFC0) != 0xFFC0 ) {
pConfig->hwm.hwmCurrentRaw.voltage[i] = dwValue;
}
}
}
/**
* hwmCaculate - Hardware Monitor Caculate Raw Data to Display Data.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmCaculate (
IN AMDSBCFG* pConfig
)
{
UINT8 i;
UINT16 dwValue;
//UINT32 ddValue;
//fan speed
for ( i = 0; i < 5 ; i++ ) {
dwValue = pConfig->hwm.hwmCurrentRaw.fanSpeed[i];
if ((dwValue == 0xffff) || (dwValue == 0x0000)) {
pConfig->hwm.hwmCurrent.fanSpeed[i] = 0;
} else {
pConfig->hwm.hwmCurrent.fanSpeed[i] = ( 22720 >> pConfig->hwm.fanSampleFreqDiv ) * 60 / dwValue / 2;
}
}
//temperatue
for ( i = 0; i < 5 ; i++ ) {
dwValue = pConfig->hwm.hwmCurrentRaw.temperature[i];
if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 1)) {
if ( IsSbA11 () ) {
dwValue = (dwValue >> 8) * 10;
} else {
dwValue = ((dwValue & 0xff00) >> 8) * 10 + (((dwValue & 0x00ff) * 10 ) >> 8);
}
} else {
dwValue = ((dwValue << 3) * pConfig->hwm.hwmTempPar[i].At / pConfig->hwm.hwmCalibrationFactor / 100 - pConfig->hwm.hwmTempPar[i].Ct) / 10 ;
}
if ( pConfig->hwm.hwmCurrentRaw.temperature[i] == 0 ) {
dwValue = 0;
}
if ( dwValue < 10000 ) {
pConfig->hwm.hwmCurrent.temperature[i] = dwValue;
} else {
pConfig->hwm.hwmCurrent.temperature[i] = 0;
}
}
//voltage
for ( i = 0; i < 8 ; i++ ) {
dwValue = pConfig->hwm.hwmCurrentRaw.voltage[i];
pConfig->hwm.hwmCurrent.voltage[i] = (dwValue >> 6) * 512 / pConfig->hwm.hwmCalibrationFactor;
}
}
/**
* hwmGetCalibrationFactor - Hardware Monitor Get Calibration
* Factor
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmGetCalibrationFactor (
IN AMDSBCFG* pConfig
)
{
UINT8 dbValue;
// UINT16 dwValue;
// UINT32 ddValue;
//temperatue parameter
ReadPMIO2 (SB_PMIO2_REGEA, AccWidthUint8, &dbValue);
if ( dbValue & BIT7 ) {
if ( dbValue & BIT6 ) {pConfig->hwm.hwmCalibrationFactor = 0x100 + dbValue;
} else {pConfig->hwm.hwmCalibrationFactor = 0x200 + (dbValue & 0x3f ); }
} else {
pConfig->hwm.hwmCalibrationFactor = 0x200;
}
}
/**
* hwmProcessParameter - Hardware Monitor process Parameter
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmProcessParameter (
IN AMDSBCFG* pConfig
)
{
UINT8 i;
UINT8 tempChannel;
UINT8 dbValue;
UINT16 dwValue;
// UINT32 ddValue;
hwmGetCalibrationFactor (pConfig);
//temperatue parameter
for ( i = 0; i < 5 ; i++ ) {
if ( pConfig->hwm.hwmTempPar[i].At == 0 ) {
pConfig->hwm.hwmTempPar[i] = tempParDefault[i];
}
}
for ( i = 0; i < 5 ; i++ ) {
if ( pConfig->hwm.hwmFanControl[i].LowDuty_reg03 == 100 ) {
pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03 = 255;
} else {
pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03 = (pConfig->hwm.hwmFanControl[i].LowDuty_reg03 << 8) / 100;
}
if ( pConfig->hwm.hwmFanControl[i].MedDuty_reg04 == 100 ) {
pConfig->hwm.hwmFanControlCooked[i].MedDuty_reg04 = 255;
} else {
pConfig->hwm.hwmFanControlCooked[i].MedDuty_reg04 = (pConfig->hwm.hwmFanControl[i].MedDuty_reg04 << 8) / 100;
}
if ( pConfig->hwm.hwmFanControl[i].HighTemp_reg0A > pConfig->hwm.hwmFanControl[i].MedTemp_reg08 ) {
dbValue = (UINT8) ((256 - pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03) / (pConfig->hwm.hwmFanControl[i].HighTemp_reg0A - pConfig->hwm.hwmFanControl[i].MedTemp_reg08));
} else {
dbValue = (UINT8) ((256 - pConfig->hwm.hwmFanControlCooked[i].LowDuty_reg03));
}
dwValue = pConfig->hwm.hwmFanControl[i].LowTemp_reg06;
if (pConfig->hwm.hwmFanControl[i].InputControl_reg00 > 4) {
tempChannel = 0;
} else {
tempChannel = pConfig->hwm.hwmFanControl[i].InputControl_reg00;
}
if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
dwValue = dwValue << 8;
} else {
dbValue = (UINT8) (dbValue * 10000 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At / 512);
dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
}
pConfig->hwm.hwmFanControlCooked[i].LowTemp_reg06 = dwValue;
pConfig->hwm.hwmFanControlCooked[i].Multiplier_reg05 = dbValue & 0x3f;
dwValue = pConfig->hwm.hwmFanControl[i].MedTemp_reg08;
if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
dwValue = dwValue << 8;
} else {
dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
}
pConfig->hwm.hwmFanControlCooked[i].MedTemp_reg08 = dwValue;
dwValue = pConfig->hwm.hwmFanControl[i].HighTemp_reg0A;
if ((pConfig->hwm.hwmSbtsiAutoPoll == 1) && (i == 0)) {
dwValue = dwValue << 8;
} else {
dwValue = ((dwValue * 100 + pConfig->hwm.hwmTempPar[tempChannel].Ct ) * 100 * pConfig->hwm.hwmCalibrationFactor / pConfig->hwm.hwmTempPar[tempChannel].At) >> 3;
}
pConfig->hwm.hwmFanControlCooked[i].HighTemp_reg0A = dwValue;
}
}
/**
* hwmSetRegister - Hardware Monitor Set Parameter
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmSetRegister (
IN AMDSBCFG* pConfig
)
{
UINT8 *pDbValue;
UINT8 i;
UINT8 registerN;
UINT8 registerPM2RegF8;
UINT8 registerPM2RegF9;
//UINT16 dwValue;
// UINT32 ddValue;
//Configure Fans
for ( i = 0; i < 5 ; i++ ) {
pDbValue = &(pConfig->hwm.hwmFanControlCooked[i].InputControl_reg00);
for ( registerN = 0; registerN < 0x0E ; registerN++ ) {
WritePMIO2 (i * 0x10 + registerN, AccWidthUint8, pDbValue);
pDbValue ++;
}
}
//Configure Sample Frequency Divider
WritePMIO2 (SB_PMIO2_REG63, AccWidthUint8, &(pConfig->hwm.fanSampleFreqDiv));
//Configure Mode
ReadPMIO2 (0xF8, AccWidthUint8, &registerPM2RegF8);
ReadPMIO2 (0xF9, AccWidthUint8, &registerPM2RegF9);
for ( i = 0; i < 5 ; i++ ) {
if (pConfig->hwm.hwmTempPar[i].Mode == BIT0) {
registerPM2RegF8 |= 1 << (i + 3);
} else if (pConfig->hwm.hwmTempPar[i].Mode == BIT1) {
registerPM2RegF9 |= 1 << (i + 3);
}
}
WritePMIO2 (0xF8, AccWidthUint8, &registerPM2RegF8);
WritePMIO2 (0xF9, AccWidthUint8, &registerPM2RegF9);
}
/**
* hwmUpdateData - Hardware Monitor Update Data.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmUpdateData (
IN AMDSBCFG* pConfig
)
{
if ( pConfig->hwm.hwmEnable ) {
hwmSbtsiAutoPolling (pConfig);
hwmGetRawData (pConfig);
hwmCaculate (pConfig);
}
}
/**
* hwmCopyFanControl - Hardware Monitor Copy Fan Control Data.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmCopyFanControl (
IN AMDSBCFG* pConfig
)
{
UINT8 *fanControl;
UINT8 *fanControlCooked;
if ( pConfig->hwm.hwmEnable ) {
fanControl = & pConfig->hwm.hwmFanControl[0].InputControl_reg00;
fanControlCooked = & pConfig->hwm.hwmFanControlCooked[0].InputControl_reg00;
MemoryCopy (fanControlCooked, fanControl, (sizeof (HWM_fan_ctl_struct) * 5));
}
}
/**
* hwmInit - Init Hardware Monitor.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
hwmInit (
IN AMDSBCFG* pConfig
)
{
hwmInitRegister (pConfig);
if ( pConfig->hwm.hwmEnable ) {
hwmCopyFanControl (pConfig);
hwmProcessParameter (pConfig);
hwmSetRegister (pConfig);
hwmSbtsiAutoPolling (pConfig);
}
}
//#endif

92
src/vendorcode/amd/cimx/sb900/IoLib.c Executable file
View File

@ -0,0 +1,92 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
VOID
ReadIO (
IN UINT16 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8:
*(UINT8*)Value = ReadIo8 (Address);
break;
case AccWidthUint16:
*(UINT16*)Value = ReadIo16 (Address);
break;
case AccWidthUint32:
*(UINT32*)Value = ReadIo32 (Address);
break;
default:
break;
}
}
VOID
WriteIO (
IN UINT16 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8:
WriteIo8 (Address, *(UINT8*)Value);
break;
case AccWidthUint16:
WriteIo16 (Address, *(UINT16*)Value);
break;
case AccWidthUint32:
WriteIo32 (Address, *(UINT32*)Value);
break;
default:
break;
}
}
VOID
RWIO (
IN UINT16 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
ReadIO (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WriteIO (Address, OpFlag, &Result);
}

44
src/vendorcode/amd/cimx/sb900/Legacy.c Executable file
View File

@ -0,0 +1,44 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
UINT32
GetFixUp (
OUT VOID
)
{
AMD_CONFIG_PARAMS* Result;
Result = (AMD_CONFIG_PARAMS*) getConfigPointer ();
if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) {
return 0;
}
return Result->ImageBasePtr;
}

88
src/vendorcode/amd/cimx/sb900/Makefile.inc Executable file
View File

@ -0,0 +1,88 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
# CIMX Root directory
CIMX_ROOT = $(src)/vendorcode/amd/cimx
CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
CIMX_INC += -I$(src)/southbridge/amd/cimx/sb900
CIMX_INC += -I$(CIMX_ROOT)/sb900
romstage-y += AcpiLib.c
romstage-y += Azalia.c
romstage-y += Dispatcher.c
romstage-y += EcFanc.c
romstage-y += EcFanLib.c
romstage-y += Gec.c
romstage-y += Gpp.c
romstage-y += Pmio2Lib.c
romstage-y += Sata.c
romstage-y += SbCmn.c
romstage-y += SbMain.c
romstage-y += SbPor.c
romstage-y += MemLib.c
romstage-y += PciLib.c
romstage-y += IoLib.c
romstage-y += PmioLib.c
romstage-y += AmdLib.c
romstage-y += SbPeLib.c
romstage-y += AmdSbLib.c
romstage-y += EcLib.c
romstage-y += Ec.c
romstage-y += Smm.c
romstage-y += Usb.c
romstage-y += Hwm.c
ramstage-y += AcpiLib.c
ramstage-y += Azalia.c
ramstage-y += Dispatcher.c
ramstage-y += EcFanc.c
ramstage-y += EcFanLib.c
ramstage-y += Gec.c
ramstage-y += Gpp.c
ramstage-y += Pmio2Lib.c
ramstage-y += Sata.c
ramstage-y += SbCmn.c
ramstage-y += SbMain.c
ramstage-y += SbPor.c
ramstage-y += MemLib.c
ramstage-y += PciLib.c
ramstage-y += IoLib.c
ramstage-y += PmioLib.c
ramstage-y += AmdLib.c
ramstage-y += SbPeLib.c
ramstage-y += AmdSbLib.c
ramstage-y += EcLib.c
ramstage-y += Ec.c
ramstage-y += Smm.c
ramstage-y += Usb.c
#ramstage-y += Legacy.c
#ramstage-y += SbModInf.c
ramstage-y += Debug.c
ramstage-y += GppHp.c
ramstage-y += Hwm.c
CIMX_CFLAGS =
export CIMX_ROOT
export CIMX_INC
export CIMX_CFLAGS
CC := $(CC) $(CIMX_INC)
#######################################################################

93
src/vendorcode/amd/cimx/sb900/MemLib.c Executable file
View File

@ -0,0 +1,93 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
VOID
ReadMEM (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8:
*((UINT8*)Value) = *((UINT8*) ((UINTN)Address));
break;
case AccWidthUint16:
*((UINT16*)Value) = *((UINT16*) ((UINTN)Address));
break;
case AccWidthUint32:
*((UINT32*)Value) = *((UINT32*) ((UINTN)Address));
break;
default:
break;
}
}
VOID
WriteMEM (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccWidthUint8 :
*((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);
break;
case AccWidthUint16:
*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value);
break;
case AccWidthUint32:
*((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);
break;
default:
break;
}
}
VOID
RWMEM (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
ReadMEM (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WriteMEM (Address, OpFlag, &Result);
}

229
src/vendorcode/amd/cimx/sb900/Oem.h Executable file
View File

@ -0,0 +1,229 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#define BIOS_SIZE 0x04 //04 - 1MB
#define LEGACY_FREE 0x00
#define ACPI_SLEEP_TRAP 0x01
//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
/**
* Module Specific Defines for platform BIOS
*
*/
/**
* PCIEX_BASE_ADDRESS - Define PCIE base address
*
* @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
*/
#ifdef MOVE_PCIEBAR_TO_F0000000
#define PCIEX_BASE_ADDRESS 0xF7000000
#else
#define PCIEX_BASE_ADDRESS 0xE0000000
#endif
/**
* SMBUS0_BASE_ADDRESS - Smbus base address
*
*/
#ifndef SMBUS0_BASE_ADDRESS
#define SMBUS0_BASE_ADDRESS 0xB00
#endif
/**
* SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
*
*/
#ifndef SMBUS1_BASE_ADDRESS
#define SMBUS1_BASE_ADDRESS 0xB20
#endif
/**
* SIO_PME_BASE_ADDRESS - Super IO PME base address
*
*/
#ifndef SIO_PME_BASE_ADDRESS
#define SIO_PME_BASE_ADDRESS 0xE00
#endif
/**
* SPI_BASE_ADDRESS - SPI controller (ROM) base address
*
*/
#ifndef SPI_BASE_ADDRESS
#define SPI_BASE_ADDRESS 0xFEC10000
#endif
/**
* WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
*
*/
#ifndef WATCHDOG_TIMER_BASE_ADDRESS
#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
#endif
/**
* HPET_BASE_ADDRESS - HPET base address
*
*/
#ifndef HPET_BASE_ADDRESS
#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
#endif
/**
* ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
*
*/
#ifdef ALT_ADDR_400
#define ACPI_BLK_BASE 0x400
#else
#define ACPI_BLK_BASE 0x800
#endif
#define PM1_STATUS_OFFSET 0x00
#define PM1_ENABLE_OFFSET 0x02
#define PM1_CONTROL_OFFSET 0x04
#define PM_TIMER_OFFSET 0x08
#define CPU_CONTROL_OFFSET 0x10
#define EVENT_STATUS_OFFSET 0x20
#define EVENT_ENABLE_OFFSET 0x24
/**
* PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
*
*/
#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
/**
* PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
*
*/
#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
/**
* PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
*
*/
#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
/**
* CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
*
*/
#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
/**
* GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
*
*/
#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
/**
* SMI_CMD_PORT - ACPI SMI Command block base address
*
*/
#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
/**
* ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
*
*/
#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
/**
* SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
* Define value for SSID while SATA controller set to IDE mode.
*/
#define SATA_IDE_MODE_SSID 0x78001022
/**
* SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
* Define value for SSID while SATA controller set to RAID mode.
*/
#define SATA_RAID_MODE_SSID 0x78021022
/**
* SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
* Define value for SSID while SATA controller set to RAID5 mode.
*/
#define SATA_RAID5_MODE_SSID 0x78031022
/**
* SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
* Define value for SSID while SATA controller set to AHCI mode.
*/
#define SATA_AHCI_SSID 0x78011022
/**
* OHCI_SSID - All SB OHCI controllers SSID value.
*
*/
#define OHCI_SSID 0x78071022
/**
* EHCI_SSID - All SB EHCI controllers SSID value.
*
*/
#define EHCI_SSID 0x78081022
/**
* OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
*
*/
#define OHCI4_SSID 0x78091022
/**
* SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
*
*/
#define SMBUS_SSID 0x780B1022
/**
* IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
*
*/
#define IDE_SSID 0x780C1022
/**
* AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
*
*/
#define AZALIA_SSID 0x780D1022
/**
* LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
*
*/
#define LPC_SSID 0x780E1022
/**
* PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
*
*/
#define PCIB_SSID 0x780F1022

83
src/vendorcode/amd/cimx/sb900/PciLib.c Executable file
View File

@ -0,0 +1,83 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
VOID
ReadPCI (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
if ( (UINT16)Address < 0xff ) {
//Normal Config Access
UINT32 AddrCf8;
AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
}
}
VOID
WritePCI (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
OpFlag = OpFlag & 0x7f;
if ( (UINT16)Address < 0xff ) {
//Normal Config Access
UINT32 AddrCf8;
AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
}
}
VOID
RWPCI (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
Result = 0;
OpFlag = OpFlag & 0x7f;
ReadPCI (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WritePCI (Address, OpFlag, &Result);
}

127
src/vendorcode/amd/cimx/sb900/Pmio2Lib.c Executable file
View File

@ -0,0 +1,127 @@
/**
* @file
*
* Southbridge PMIO2 access common routine
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
VOID
ReadPMIO2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
Address++;
ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO 2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
VOID
WritePMIO2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
Address++;
WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RWPMIO2 - Read/Write PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
VOID
RWPMIO2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 Result;
OpFlag = OpFlag & 0x7f;
ReadPMIO2 (Address, OpFlag, &Result);
Result = (Result & AndMask) | OrMask;
WritePMIO2 (Address, OpFlag, &Result);
}

126
src/vendorcode/amd/cimx/sb900/PmioLib.c Executable file
View File

@ -0,0 +1,126 @@
/**
* @file
*
* Southbridge PMIO access common routine
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
VOID
ReadPMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
Address++;
ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
VOID
WritePMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID* Value
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
if ( OpFlag == 0x02 ) {
OpFlag = 0x03;
}
for ( i = 0; i <= OpFlag; i++ ) {
WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
Address++;
WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RWPMIO - Read/Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
VOID
RWPMIO (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask
)
{
UINT32 Result;
OpFlag = OpFlag & 0x7f;
ReadPMIO (Address, OpFlag, &Result);
Result = (Result & AndMask) | OrMask;
WritePMIO (Address, OpFlag, &Result);
}

1042
src/vendorcode/amd/cimx/sb900/Sata.c Executable file
View File

File diff suppressed because it is too large Load Diff

53
src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h Executable file
View File

@ -0,0 +1,53 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#ifndef _BIOS_RAM_USAGE_H_
#define _BIOS_RAM_USAGE_H_
#define RESTORE_MEMORY_CONTROLLER_START 0
#define XHCI_REGISTER_BAR00 0xD0
#define XHCI_REGISTER_BAR01 0xD1
#define XHCI_REGISTER_BAR02 0xD2
#define XHCI_REGISTER_BAR03 0xD3
#define XHCI_REGISTER_04H 0xD4
#define XHCI_REGISTER_0CH 0xD5
#define XHCI_REGISTER_3CH 0xD6
#define XHCI1_REGISTER_BAR00 0xE0
#define XHCI1_REGISTER_BAR01 0xE1
#define XHCI1_REGISTER_BAR02 0xE2
#define XHCI1_REGISTER_BAR03 0xE3
#define XHCI1_REGISTER_04H 0xE4
#define XHCI1_REGISTER_0CH 0xE5
#define XHCI1_REGISTER_3CH 0xE6
#define RTC_WORKAROUND_DATA_START 0xF0
#define BOOT_TIME_FLAG_SEC 0xF8
#define BOOT_TIME_FLAG_INT19 0xFC
#endif

1544
src/vendorcode/amd/cimx/sb900/SbCmn.c Executable file
View File

File diff suppressed because it is too large Load Diff

422
src/vendorcode/amd/cimx/sb900/SbDef.h Executable file
View File

@ -0,0 +1,422 @@
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
//AMD Library Routines (AMDLIB.C)
void InitSerialOut (void);
unsigned char getNumberOfCpuCores (OUT void);
unsigned int readAlink (IN unsigned int Index);
void writeAlink (IN unsigned int Index, IN unsigned int Data);
void rwAlink (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask);
//AMD Library Routines (LEGACY.C)
unsigned int GetFixUp (OUT void);
//AMD Library Routines (IOLIB.C)
void ReadIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
void WriteIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value);
void RWIO (IN unsigned short Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
/// CPUID data received registers format
typedef struct _SB_CPUID_DATA {
IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX
IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX
IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX
IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX
} SB_CPUID_DATA;
//AMD Library Routines (AMDLIB32.ASM)
unsigned char ReadIo8 (IN unsigned short Address);
unsigned short ReadIo16 (IN unsigned short Address);
unsigned int ReadIo32 (IN unsigned short Address);
void WriteIo8 (IN unsigned short Address, IN unsigned char Data);
void WriteIo16 (IN unsigned short Address, IN unsigned short Data);
void WriteIo32 (IN unsigned short Address, IN unsigned int Data);
unsigned char ReadNumberOfCpuCores (void);
unsigned long long ReadTSC (void);
void CpuidRead (IN unsigned int CpuidFcnAddress, OUT SB_CPUID_DATA *Value);
//AMD Library Routines (MEMLIB.C)
void ReadMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
void WriteMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value);
void RWMEM (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
void
MemoryCopy (
IN unsigned char *Dest,
IN unsigned char *Source,
IN unsigned int Size
);
//AMD Library Routines (PCILIB.C)
void ReadPCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
void WritePCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value);
void RWPCI (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data);
//AMD Library Routines (SBPELIB.C)
/**
* Read Southbridge Revision ID cie Base
*
*
* @retval 0xXXXXXXXX Revision ID
*
*/
unsigned char getRevisionID (OUT void);
//AMD Library Routines (SBPELIB.C)
/**
* Is SB A11?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char IsSbA11 (OUT void);
//AMD Library Routines (SBPELIB.C)
/**
* Is SB A12?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char IsSbA12 (OUT void);
//AMD Library Routines (SBPELIB.C)
/**
* Is SB A12 Plus?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char IsSbA12Plus (OUT void);
//AMD Library Routines (SBPELIB.C)
/**
* Is SB A13 Plus?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char IsSbA13Plus (OUT void);
/**
* Is LPC Rom?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char IsExternalClockMode (OUT void);
/**
* Is External Clock Mode?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char IsLpcRom (OUT void);
/**
* Is GCPU?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char
IsGCPU (
OUT void
);
//AMD Library Routines (SBPELIB.C)
/**
* Assert/deassert Hudson-2 pins used to toggle SB GPP reset or NB PCIE reset
*
*
* @param[in] ResetBlock - PCIE reset for SB GPP or NB PCIE
* @param[in] ResetOp - Assert or deassert PCIE reset
*
*/
void SbResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp);
/**
* sbGppTogglePcieReset - Toggle PCIE_RST2#
*
*
* @param[in] pConfig
*
*/
void sbGppTogglePcieReset (IN AMDSBCFG* pConfig);
/**
* sbSpiUnlock - Sb SPI Unlock
*
*
* @param[in] pConfig
*
*/
void sbSpiUnlock (IN AMDSBCFG* pConfig);
/**
* sbSpilock - Sb SPI lock
*
*
* @param[in] pConfig
*
*/
void sbSpilock (IN AMDSBCFG* pConfig);
/**
* programPciByteTable - Program PCI register by table (8 bits data)
*
*
*
* @param[in] pPciByteTable - Table data pointer
* @param[in] dwTableSize - Table length
*
*/
void programPciByteTable (IN REG8MASK* pPciByteTable, IN unsigned short dwTableSize);
/**
* programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
*
*
*
* @param[in] pAcpiTbl - Table data pointer
*
*/
void programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl);
/**
* getChipSysMode - Get Chip status
*
*
* @param[in] Value - Return Chip strap status
* StrapStatus [15.0] - Hudson-2 chip Strap Status
* @li <b>0001</b> - Not USED FWH
* @li <b>0002</b> - Not USED LPC ROM
* @li <b>0004</b> - EC enabled
* @li <b>0008</b> - Reserved
* @li <b>0010</b> - Internal Clock mode
*
*/
void getChipSysMode (IN void* Value);
/**
* isImcEnabled - Is IMC Enabled
* @retval TRUE for IMC Enabled; FALSE for IMC Disabled
*/
unsigned char isImcEnabled (void);
/**
* Read Southbridge CIMx configuration structure pointer
*
*
*
* @retval 0xXXXXXXXX CIMx configuration structure pointer.
*
*/
AMDSBCFG* getConfigPointer (OUT void);
//AMD Library Routines (PMIOLIB.C)
/**
* Read PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
void ReadPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
/**
* Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
void WritePMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
/**
* RWPMIO - Read/Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
void RWPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
//AMD Library Routines (PMIO2LIB.C)
/**
* Read PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
*
*/
void ReadPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
/**
* Write PMIO 2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
*
*/
void WritePMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value);
/**
* RWPMIO2 - Read/Write PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
*
*/
void RWPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask);
//AMD Library Routines (ECLIB.C)
// ECLIB Routines
// #ifndef NO_EC_SUPPORT
/**
* EnterEcConfig - Force EC into Config mode
*
*
*
*
*/
void EnterEcConfig (void);
/**
* ExitEcConfig - Force EC exit Config mode
*
*
*
*
*/
void ExitEcConfig (void);
/**
* ReadEC8 - Read EC register data
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Read Data Buffer
*
*/
void ReadEC8 (IN unsigned char Address, IN unsigned char* Value);
/**
* WriteEC8 - Write date into EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Write Data Buffer
*
*/
void WriteEC8 (IN unsigned char Address, IN unsigned char* Value);
/**
* RWEC8 - Read/Write EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] AndMask - Data And Mask 8 bits
* @param[in] OrMask - Data OR Mask 8 bits
*
*/
void RWEC8 (IN unsigned char Address, IN unsigned char AndMask, IN unsigned char OrMask);
unsigned char IsZoneFuncEnable (IN unsigned short Flag, IN unsigned char func, IN unsigned char Zone);
void sbECfancontrolservice (IN AMDSBCFG* pConfig);
void hwmImcInit (IN AMDSBCFG* pConfig);
void GetSbAcpiMmioBase (OUT unsigned int* AcpiMmioBase);
void GetSbAcpiPmBase (OUT unsigned short* AcpiPmBase);
void SetAcpiPma (IN unsigned char pmaControl);
void imcEnableSurebootTimer (IN AMDSBCFG* pConfig);
void imcDisableSurebootTimer (IN AMDSBCFG* pConfig);
void imcDisarmSurebootTimer (IN AMDSBCFG* pConfig);
void hwmSbtsiAutoPolling (IN AMDSBCFG* pConfig);
void hwmSbtsiAutoPollingOff (IN AMDSBCFG* pConfig);
void hwmSbtsiAutoPollingPause (IN AMDSBCFG* pConfig);
void imcSleep (IN AMDSBCFG* pConfig);
void imcWakeup (IN AMDSBCFG* pConfig);
void imcIdle (IN AMDSBCFG* pConfig);
void imcThermalZoneEnable (IN AMDSBCFG* pConfig);
void ValidateFchVariant (IN AMDSBCFG* pConfig);
void CheckEfuse (IN AMDSBCFG* pConfig);
/**
* Is UMI One Lane GEN1 Mode?
*
*
* @retval TRUE or FALSE
*
*/
unsigned char IsUmiOneLaneGen1Mode ( OUT void );
/**
* Record SMI Status
*
*
* @retval Nothing
*
*/
void RecordSmiStatus ( OUT void );
// #endif

295
src/vendorcode/amd/cimx/sb900/SbMain.c Executable file
View File

@ -0,0 +1,295 @@
/**
* @file
*
* SB Initialization.
*
* Init IOAPIC/IOMMU/Misc NB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
#ifndef B1_IMAGE
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbBeforePciInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
RecordSbConfigPtr ( (UINT32) ((UINTN) (pConfig)));
CheckEfuse (pConfig);
ValidateFchVariant (pConfig);
imcEnableSurebootTimer (pConfig);
commonInitEarlyPost (pConfig);
commonInitEarlyBoot (pConfig);
#ifndef NO_EC_SUPPORT
ecInitBeforePciEnum (pConfig);
#endif
usbInitBeforePciEnum (pConfig); // USB POST TIME Only
sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY
gecInitBeforePciEnum (pConfig); // Init GEC
azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
sbPcieGppEarlyInit (pConfig); // Gpp port init
abSpecialSetBeforePciEnum (pConfig);
hwmInit (pConfig);
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
}
/**
* sbAfterPciInit - Config Southbridge after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
imcEnableSurebootTimer (pConfig);
usbInitAfterPciInit (pConfig); // Init USB MMIO
sataInitAfterPciEnum (pConfig); // SATA port enumeration
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hwmUpdateData (pConfig);
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
}
/**
* sbMidPostInit - Config Southbridge during middle of POST
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbMidPostInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbMidPostInit \n"));
imcEnableSurebootTimer (pConfig);
sataInitMidPost (pConfig);
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbMidPostInit \n"));
}
/*----------------------------------------------------------------------------------------*/
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbLatePost (
IN AMDSBCFG* pConfig
)
{
// UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
commonInitLateBoot (pConfig);
sataInitLatePost (pConfig);
gecInitLatePost (pConfig);
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
ecInitLatePost (pConfig);
#endif
sbPcieGppLateInit (pConfig);
hwmImcInit (pConfig);
// hwmSbtsiAutoPollingOff (pConfig);
imcDisarmSurebootTimer (pConfig);
usbInitLate (pConfig); // Init USB
StressResetModeLate (pConfig); //
}
/*----------------------------------------------------------------------------------------*/
/**
* sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbBeforePciRestoreInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pConfig->S3Resume = 1;
ValidateFchVariant (pConfig);
commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers
usbInitBeforePciEnum (pConfig); // USB POST TIME Only
sataInitBeforePciEnum (pConfig);
gecInitBeforePciEnum (pConfig); // Init GEC
azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio
sbPcieGppEarlyInit (pConfig); // Gpp port init
abSpecialSetBeforePciEnum (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
}
/*----------------------------------------------------------------------------------------*/
/**
* sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciRestoreInit (
IN AMDSBCFG* pConfig
)
{
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost (pConfig);
c3PopupSetting (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
hwmInit (pConfig);
hwmImcInit (pConfig);
}
/*----------------------------------------------------------------------------------------*/
/**
* sbSmmAcpiOn - Config Southbridge during ACPI_ON
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbSmmAcpiOn (
IN AMDSBCFG* pConfig
)
{
// Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
// recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows
AMDSBCFG* pTmp; //lx-dummy for /W4 build
pTmp = pConfig;
// Disable Power Button SMI
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6), 0);
// USB workaroud
// x00[0] = 1;
// x04[31] = 0, x04[0] = 1;
// x08[31] = 0, x08[7] = 0;
// x0C[31] = 0, x0C[7] = 0,
// x10[31] = 0, x10[0] = 1;
// x14[31] = 0, x14[0] = 1;
// x18[31] = 0, x18[7] = 0;
// x1C[31] = 0,
// x20[31] = 0,
//RWMEM (0x00, AccWidthUint32, 0, BIT0);
//RWMEM (0x04, AccWidthUint32, 0, BIT0);
//RWMEM (0x08, AccWidthUint32, 0, 0);
//RWMEM (0x0C, AccWidthUint32, 0, 0);
//RWMEM (0x10, AccWidthUint32, 0, BIT0);
//RWMEM (0x14, AccWidthUint32, 0, BIT0);
//RWMEM (0x18, AccWidthUint32, 0, 0);
//RWMEM (0x1C, AccWidthUint32, 0, 0);
//RWMEM (0x20, AccWidthUint32, 0, 0);
}
#endif
/*----------------------------------------------------------------------------------------*/
/**
* Call Back routine.
*
*
*
* @param[in] Func Callback ID.
* @param[in] Data Callback specific data.
* @param[in] pConfig Southbridge configuration structure pointer.
*/
UINTN
CallBackToOEM (
IN UINT32 Func,
IN UINT32 Data,
IN AMDSBCFG* pConfig
)
{
UINT32 Result;
Result = 0;
if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;
TRACE ((DMSG_SB_TRACE, "Calling %lx ( % x, % x, % x)\n", pConfig->StdHeader.CalloutPtr, Func, Data, pConfig));
Result = (*(SBCIM_HOOK_ENTRY*) (UINTN)&pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);
TRACE ((DMSG_SB_TRACE, "SB Hook Status [ % x]\n", Result));
return Result;
}

74
src/vendorcode/amd/cimx/sb900/SbModInf.c Executable file
View File

@ -0,0 +1,74 @@
/**
* @file
*
* Function dispatcher.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "SbPlatform.h"
#include "cbtypes.h"
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/// module header
VOLATILE AMD_MODULE_HEADER mNbModuleHeader = {
'DOM$', ///< Standard AMD module signature
CIMX_SB_ID, ///< Chipset ID
CIMX_SB_REVISION, ///< CIMx version
AmdSbDispatcher, ///< Pointer to the module entry
NULL ///< Pointer link to next module header
};

480
src/vendorcode/amd/cimx/sb900/SbPeLib.c Executable file
View File

@ -0,0 +1,480 @@
/**
* @file
*
* Southbridge IO access common routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
/**
* Read Southbridge Revision ID cie Base
*
*
* @retval 0xXXXXXXXX Revision ID
*
*/
UINT8
getRevisionID (
OUT VOID
)
{
UINT8 dbVar0;
ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0);
return dbVar0;
}
/**
* Is SB A11?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsSbA11 (
OUT VOID
)
{
return ( getRevisionID () == AMD_SB_A11 );
}
/**
* Is SB A12?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsSbA12 (
OUT VOID
)
{
return ( getRevisionID () == AMD_SB_A12 );
}
/**
* Is SB A12 Plus?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsSbA12Plus (
OUT VOID
)
{
return ( getRevisionID () >= AMD_SB_A12 );
}
/**
* Is SB A13 Plus?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsSbA13Plus (
OUT VOID
)
{
return ( getRevisionID () >= AMD_SB_A13 );
}
/**
* Is External Clock Mode?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsExternalClockMode (
OUT VOID
)
{
return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80) & BIT4) == 0) );
}
/**
* Is LPC Rom?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsLpcRom (
OUT VOID
)
{
return ( (BOOLEAN) ((ACPIMMIO32 (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80) & BIT1) == 0) );
}
/**
* Memory Copy
*
*
* @retval VOID
*
*/
VOID
MemoryCopy (
IN UINT8 *Dest,
IN UINT8 *Source,
IN UINTN Size
)
{
UINTN i;
for ( i = 0; i < Size; i++ ) {
*Dest = *Source;
Dest++;
Source++;
}
}
/*----------------------------------------------------------------------------------------*/
/**
* programPciByteTable - Program PCI register by table (8 bits data)
*
*
*
* @param[in] pPciByteTable - Table data pointer
* @param[in] dwTableSize - Table length
*
*/
VOID
programPciByteTable (
IN REG8MASK* pPciByteTable,
IN UINT16 dwTableSize
)
{
UINT8 i;
UINT8 dbBusNo;
UINT8 dbDevFnNo;
UINT32 ddBDFR;
dbBusNo = pPciByteTable->bRegIndex;
dbDevFnNo = pPciByteTable->bANDMask;
pPciByteTable++;
for ( i = 1; i < dwTableSize; i++ ) {
if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) {
pPciByteTable++;
dbBusNo = pPciByteTable->bRegIndex;
dbDevFnNo = pPciByteTable->bANDMask;
pPciByteTable++;
i++;
} else {
ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
TRACE ((DMSG_SB_TRACE, "PFA = %X AND = %X, OR = %X", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask));
RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
pPciByteTable++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)
*
*
*
* @param[in] pAcpiTbl - Table data pointer
*
*/
VOID
programSbAcpiMmioTbl (
IN AcpiRegWrite *pAcpiTbl
)
{
UINT8 i;
UINT32 ddtempVar;
if (pAcpiTbl != NULL) {
if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataANDMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
// Signature Checking
pAcpiTbl++;
for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask);
pAcpiTbl++;
}
}
}
}
/**
* getChipSysMode - Get Chip status
*
*
* @param[in] Value - Return Chip strap status
* StrapStatus [15.0] - Hudson-2 chip Strap Status
* @li <b>0001</b> - Not USED FWH
* @li <b>0002</b> - Not USED LPC ROM
* @li <b>0004</b> - EC enabled
* @li <b>0008</b> - Reserved
* @li <b>0010</b> - Internal Clock mode
*
*/
VOID
getChipSysMode (
IN VOID* Value
)
{
ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);
}
/**
* isImcEnabled - Is IMC Enabled
* @retval TRUE for IMC Enabled; FALSE for IMC Disabled
*/
BOOLEAN
isImcEnabled (
)
{
UINT8 dbSysConfig;
getChipSysMode (&dbSysConfig);
if (dbSysConfig & ChipSysEcEnable) {
return TRUE;
} else {
return FALSE;
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Read Southbridge CIMx configuration structure pointer
*
*
*
* @retval 0xXXXXXXXX CIMx configuration structure pointer.
*
*/
AMDSBCFG*
getConfigPointer (
OUT VOID
)
{
UINT8 dbReg;
UINT8 dbValue;
UINT8 i;
UINT32 ddValue;
ddValue = 0;
dbReg = SB_ECMOS_REG08;
for ( i = 0; i <= 3; i++ ) {
WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);
ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);
ddValue |= (dbValue << (i * 8));
dbReg++;
}
return ( (AMDSBCFG*) (UINTN)ddValue);
}
/**
* getEfuseStatue - Get Efuse status
*
*
* @param[in] Value - Return Chip strap status
*
*/
VOID
getEfuseStatus (
IN VOID* Value
)
{
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);
WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);
}
/**
* getEfuseByte - Get Efuse Byte
*
*
* @param[in] Index - Efuse Index value
*
*/
UINT8
getEfuseByte (
IN UINT8 Index
)
{
UINT8 Data;
WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, &Index);
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, &Data);
return Data;
}
/**
* SbResetGppDevice - Toggle GEVENT4 to assert/deassert GPP device reset
*
*
* @param[in] ResetBlock - PCIE reset for SB GPP or NB PCIE
* @param[in] ResetOp - Assert or deassert PCIE reset
*
*/
VOID
SbResetPcie (
IN RESET_BLOCK ResetBlock,
IN RESET_OP ResetOp
)
{
if (ResetBlock == NbBlock) {
if (ResetOp == AssertReset) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFF, BIT4);
} else if (ResetOp == DeassertReset) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, ~BIT4, 0);
}
} else if (ResetBlock == SbBlock) {
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG04, AccWidthUint8, ~(BIT1 + BIT0), 0x02);
if (ResetOp == AssertReset) {
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GEVENT_REG04, AccWidthUint8, ~BIT5, 0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, 0xFF, BIT4);
} else if (ResetOp == DeassertReset) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBF, AccWidthUint8, ~BIT4, 0);
RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GEVENT_REG04, AccWidthUint8, 0xff, BIT5);
}
}
}
/**
* sbGppTogglePcieReset - Toggle PCIE_RST2#
*
*
* @param[in] pConfig
*
*/
VOID
sbGppTogglePcieReset (
IN AMDSBCFG* pConfig
)
{
if (pConfig->GppToggleReset) {
SbResetPcie (SbBlock, AssertReset);
SbStall (500);
SbResetPcie (SbBlock, DeassertReset);
}
}
/**
* sbSpiUnlock - Sb SPI Unlock
*
*
* @param[in] pConfig
*
*/
VOID
sbSpiUnlock (
IN AMDSBCFG* pConfig
)
{
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG50, AccWidthUint32, ~(BIT0 + BIT1), 0);
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG54, AccWidthUint32, ~(BIT0 + BIT1), 0);
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG58, AccWidthUint32, ~(BIT0 + BIT1), 0);
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG5C, AccWidthUint32, ~(BIT0 + BIT1), 0);
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32, ~(BIT22 + BIT23), (BIT22 + BIT23));
}
/**
* sbSpilock - Sb SPI lock
*
*
* @param[in] pConfig
*
*/
VOID
sbSpilock (
IN AMDSBCFG* pConfig
)
{
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG50, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG54, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG58, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG5C, AccWidthUint32, ~(BIT0 + BIT1), (BIT0 + BIT1));
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32, ~(BIT22 + BIT23), 0);
}
/**
* TurnOffCG2
*
*
* @retval VOID
*
*/
VOID
TurnOffCG2 (
OUT VOID
)
{
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccWidthUint8, ~BIT6, 0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x0F, 0xA0);
RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccWidthUint8, ~(BIT1 + BIT0), (BIT1 + BIT0));
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~( BIT4), (BIT4));
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~(BIT6), (BIT6));
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccWidthUint8, ~BIT6, BIT6);
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint8, ~BIT6, BIT6);
}
/**
* BackUpCG2
*
*
* @retval VOID
*
*/
VOID
BackUpCG2 (
OUT VOID
)
{
UINT8 dByte;
ReadMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccWidthUint8, &dByte);
if (dByte & BIT6) {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccWidthUint8, ~(BIT6), (0));
}
}

737
src/vendorcode/amd/cimx/sb900/SbPor.c Executable file
View File

@ -0,0 +1,737 @@
/**
* @file
*
* Southbridge Init during POWER-ON
*
* Prepare Southbridge environment during power on stage.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
#include "Hudson-2.h"
/**
* sbPorInitPciTable - PCI device registers initial during the power on stage.
*
*
*
*
*/
REG8MASK sbPorInitPciTable[] =
{
// SATA device
{0x00, SATA_BUS_DEV_FUN, 0},
{SB_SATA_REG84 + 3, ~BIT2, 0},
{SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},
{0xFF, 0xFF, 0xFF},
// LPC Device (Bus 0, Dev 20, Func 3)
{0x00, LPC_BUS_DEV_FUN, 0},
{SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2
{SB_LPC_REG47, 0xFF, BIT5},
{SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},
{SB_LPC_REG7C, 0x00, BIT0 + BIT2},
{SB_LPC_REG78, 0xF0, BIT2 + BIT3}, // Enable LDRQ pin
{SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},
// A12 set 0xBB [5:3] = 111 to improve SPI timing margin.
// A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)
{SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},
{SB_LPC_REGBA, 0x9F, BIT5 + BIT6},
{SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined
{0xFF, 0xFF, 0xFF},
// P2P Bridge (Bus 0, Dev 20, Func 4)
{0x00, PCIB_BUS_DEV_FUN, 0},
{SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
// ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR
// ENH260809: Add PCI port 80 support in Hudson-2/3
#ifdef SB_PCIB_PORT_80_SUPPORT
{SB_PCIB_REG1C, 0x00, 0xF0},
{SB_PCIB_REG1D, 0x00, 0x00},
{SB_PCIB_REG04, 0x00, 0x21},
#endif
{SB_PCIB_REG40, 0xDF, 0x20},
{SB_PCIB_REG50, 0x02, 0x01},
{0xFF, 0xFF, 0xFF},
};
/**
* sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.
*
*
*
*
*/
AcpiRegWrite sbPmioPorInitTable[] =
{
{00, 00, 0xB0, 0xAC}, // Signature
{MISC_BASE >> 8, SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
//RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
{MISC_BASE >> 8, SB_MISC_REG40, 0xEF, 0x00},
// {MISC_BASE >> 8, 0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength
{PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
{SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0 + BIT2},
{PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer
{PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},
{PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},
{PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},
{PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},
{PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},
//{PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},
{PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},
{PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},
{PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
{PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},
{PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},
{PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},
// RPR GEC I/O Termination Setting
// PM_Reg 0xF6 = Power-on default setting
// PM_Reg 0xF7 = Power-on default setting
// PM_Reg 0xF8 = 0x6C
// PM_Reg 0xF9 = 0x21
// PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
{PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},
{PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07},
{PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},
// PRP GEC -end
{PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04}, // Release NB_PCIE_RST
{PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},
{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},
//OBS200280
//{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xFF, BIT1},
{0xFF, 0xFF, 0xFF, 0xFF},
};
/**
* sbPowerOnInit - Config Southbridge during power on stage.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbPowerOnInit (
IN AMDSBCFG* pConfig
)
{
UINT8 dbPortStatus;
//UINT8 dbSysConfig;
UINT32 abValue;
UINT32 abValue2;
UINT8 dbValue;
UINT8 dbEfuse;
UINT32 dbSpiMode;
UINT16 dwAsfPort;
UINT16 smbusBase;
UINT8 cimSataMode;
// UINT8 cimSpiFastReadEnable;
// UINT8 cimSpiFastReadSpeed;
UINT8 cimSataInternal100Spread;
UINT8 indexValue;
UINT32 ddValue;
UINT8 SataPortNum;
UINT8 XhciEfuse;
XhciEfuse = XHCI_EFUSE_LOCATION;
cimSataMode = pConfig->SATAMODE.SataModeReg;
// if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {
// cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;
// } else {
// cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
// }
// cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;
cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread;
#if SB_CIMx_PARAMETER == 0
cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);
cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault);
cimSpiFastReadEnable = cimSpiFastReadEnableDefault;
cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;
cimSataInternal100Spread = SataInternal100SpreadDefault;
#endif
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
// Hudson-2 Only Enabled (Mmio_mem_enablr) // Default value is correct
RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);
RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0);
RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4);
if ( pConfig->Cg2Pll == 1 ) {
TurnOffCG2 ();
pConfig->SATAMODE.SataMode.SataClkMode = 0x0a;
}
//enable CF9
RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0);
// Set A-Link bridge access address. This address is set at device 14h, function 0,
// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
writeAlink (0x80000004, 0x04); // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction
abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation
abValue = abValue | BIT0;
writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);
writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
writeAlink (0x34, readAlink (0x34) | BIT9);
rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00);
// Enable external Stickybit register reset feature
//writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30);
//abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));
//abValue |= BIT6 + BIT5;
//writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);
// Configure UMI target link speed
dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
getEfuseStatus (&dbEfuse);
if ( dbEfuse & BIT0 ) {
pConfig->NbSbGen2 = 0;
}
dbEfuse = FCH_Variant_EFUSE_LOCATION;
getEfuseStatus (&dbEfuse);
if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) {
pConfig->NbSbGen2 = 0;
}
if (pConfig->NbSbGen2) {
abValue = 2;
abValue2 = BIT0;
} else {
abValue = 1;
abValue2 = 0;
}
rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2);
rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue);
if (pConfig->sdbEnable) {
rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00);
RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00);
RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02);
RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04);
RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01);
RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03);
RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05);
}
// Set Build option into SB
WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1]
smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress);
dbValue = 0x00;
WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue);
dbEfuse = SATA_FIS_BASE_EFUSE_LOC;
getEfuseStatus (&dbEfuse);
programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));
//RPR 3.4 Enabling ClkRun Function
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2);
//BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0);
SataPortNum = 0;
for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);
SbStall (2);
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);
SbStall (2);
}
dbValue = 0x0A;
WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
dbValue &= 0xEF;
WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 );
if (pConfig->BuildParameters.SpiSpeed) {
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12));
}
if (pConfig->BuildParameters.SpiFastSpeed) {
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14));
}
//if (pConfig->BuildParameters.SpiBurstWrite) {
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10));
//}
dbSpiMode = pConfig->BuildParameters.SpiMode;
if (pConfig->BuildParameters.SpiMode) {
if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) {
// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e);
// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 );
// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000);
// SbStall (1000);
}
RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28));
}
// if ( cimSpiFastReadSpeed ) {
// RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
// }
//Program power on pci init table
programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0);
if (pConfig->SATAMODE.SataModeReg == 0) {
pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \
+ (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \
+ (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \
+ (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \
+ (pConfig->SATAMODE.SataMode.SataClkMode << 4);
}
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg);
if (dbEfuse & BIT0) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);
}
ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);
if ( ((dbPortStatus & 0xF0) == 0x10) ) {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);
}
if ( pConfig->BuildParameters.LegacyFree ) {
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
} else {
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
}
if ( cimSataInternal100Spread ) {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4);
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00);
} else {
RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00);
}
// Toggle GEVENT4 to reset all GPP devices
sbGppTogglePcieReset (pConfig);
if ( cimSataInternal100Spread ) {
RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04);
}
dbValue = 0x08;
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
if ( !pConfig->BuildParameters.EcKbd ) {
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
dbValue = dbValue | 0x0A;
}
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
dbValue = 0x09;
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);
ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
if ( !pConfig->BuildParameters.EcKbd ) {
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
dbValue = dbValue & 0xF9;
}
if ( pConfig->BuildParameters.LegacyFree ) {
// Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
dbValue = dbValue & 0x9F;
}
// Enabled IRQ input
dbValue = dbValue | BIT4;
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);
dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0);
if ( dwAsfPort != 0 ) {
RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70); // 0x70 will change to EQU ( Remote control address)
}
#ifndef NO_EC_SUPPORT
getChipSysMode (&dbPortStatus);
if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {
// EC is disabled by jumper setting or board config
RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);
ecPowerOnInit ( pConfig);
imcSleep ( pConfig);
}
#endif
ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
if ( ddValue == 0x78121022 ) {
//
// First Xhci controller.
//
ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
ddValue = 0;
indexValue = XHCI_REGISTER_BAR03;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue = (UINT32) dbValue;
indexValue = XHCI_REGISTER_BAR02;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue <<= 8;
ddValue |= (UINT32) dbValue;
indexValue = XHCI_REGISTER_BAR01;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue <<= 8;
ddValue |= (UINT32) dbValue;
indexValue = XHCI_REGISTER_BAR00;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue <<= 8;
ddValue |= (UINT32) dbValue;
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
indexValue = XHCI_REGISTER_04H;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
indexValue = XHCI_REGISTER_0CH;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
indexValue = XHCI_REGISTER_3CH;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
//
// Second Xhci controller.
//
ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue);
ddValue = 0;
indexValue = XHCI1_REGISTER_BAR03;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue = (UINT32) dbValue;
indexValue = XHCI1_REGISTER_BAR02;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue <<= 8;
ddValue |= (UINT32) dbValue;
indexValue = XHCI1_REGISTER_BAR01;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue <<= 8;
ddValue |= (UINT32) dbValue;
indexValue = XHCI1_REGISTER_BAR00;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
ddValue <<= 8;
ddValue |= (UINT32) dbValue;
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue);
indexValue = XHCI1_REGISTER_04H;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue);
indexValue = XHCI1_REGISTER_0CH;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue);
indexValue = XHCI1_REGISTER_3CH;
WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue);
ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue);
WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue);
}
// RPR 3.2 Enabling SPI ROM Prefetch
// Set LPC cfg 0xBA bit 8
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8);
if (IsSbA12Plus ()) {
// Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7);
}
#ifdef XHCI_SUPPORT
#ifdef XHCI_INIT_IN_ROM_SUPPORT
if ( pConfig->XhciSwitch == 1 ) {
if ( pConfig->S3Resume == 0 ) {
XhciEarlyInit ();
} else {
XhciInitIndirectReg ();
}
} else {
// for power saving.
// add Efuse checking for Xhci enable/disable
getEfuseStatus (&XhciEfuse);
if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
}
}
#endif
#endif
}
#ifdef XHCI_SUPPORT
VOID
XhciInitIndirectReg (
)
{
UINT32 ddDrivingStrength;
UINT32 port;
ddDrivingStrength = 0;
port = 0;
#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
#endif
//
// RPR SuperSpeed PHY Configuration (adaptation mode setting)
//
RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
//
// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
//
// RPR BLM Meaasge
//
RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
//
// RPR 8.13 xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
#ifdef USB3_EHCI_DRIVING_STRENGTH
for (port = 0; port < 4; port ++) {
ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
if (ddDrivingStrength & BIT3) {
ddDrivingStrength &= 0x07;
if (port < 2) {
RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
} else {
RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength);
RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
}
}
}
#endif
// Step 3
if (IsSbA11 ()) {
RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
} else {
RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
}
}
VOID
XhciEarlyInit (
)
{
UINT16 BcdAddress;
UINT16 BcdSize;
UINT16 AcdAddress;
UINT16 AcdSize;
UINT16 FwAddress;
UINT16 FwSize;
UINTN XhciFwStarting;
UINT32 SpiValidBase;
UINT32 RegData;
UINT16 i;
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
SbStall (20);
//
// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
//
GetRomSigPtr (&XhciFwStarting);
if (XhciFwStarting == 0) {
return;
}
XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
if (IsLpcRom ()) {
//XHCI firmware re-load
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
}
//
// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
//
// RPR SuperSpeed PHY Configuration (adaptation timer setting)
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
//RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
//
// Step 1. to enable Xhci IO and Firmware load mode
//
#ifdef XHCI_SUPPORT_ONE_CONTROLLER
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
#else
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
#endif
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
//
// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
//
// Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
//
for (i = 0; i < SPI_HEAD_LENGTH; i++) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
}
for (i = 0; i < BcdSize; i++) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
}
for (i = 0; i < AcdSize; i++) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
}
//
// Step 3. to enable the instruction RAM preload functionality.
//
FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
FwAddress += 2;
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
//
// Set the starting address offset for Instruction RAM preload.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
for (;;) {
ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
if (RegData & BIT30) break;
}
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
//
// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
for (;;) {
ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
if (RegData & U3PLL_LOCK) break;
}
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
if (IsSbA11 ()) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
}
XhciInitIndirectReg ();
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
//if (!(pConfig->S4Resume)) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
//}
//
// Step 5.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
}
#endif

607
src/vendorcode/amd/cimx/sb900/SbSubFun.h Executable file
View File

@ -0,0 +1,607 @@
/**
* @file
*
* Southbridge CIMx Function Support Define (All)
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
// Southbridge SBMAIN Routines
/**
* Southbridge Main Function Public Function
*
*/
/**
* sbBeforePciInit - Config Southbridge before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbBeforePciInit (IN AMDSBCFG* pConfig);
/**
* sbAfterPciInit - Config Southbridge after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbAfterPciInit (IN AMDSBCFG* pConfig);
/**
* sbMidPostInit - Config Southbridge during middle of POST
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbMidPostInit (IN AMDSBCFG* pConfig);
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbLatePost (IN AMDSBCFG* pConfig);
/**
* sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);
/**
* sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);
/**
* sbSmmAcpiOn - Config Southbridge during ACPI_ON
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbSmmAcpiOn (IN AMDSBCFG* pConfig);
/**
* CallBackToOEM - Call Back routine.
*
*
*
* @param[in] Func Callback ID.
* @param[in] Data Callback specific data.
* @param[in] pConfig Southbridge configuration structure pointer.
*/
unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig);
// Southbridge SBPOR Routines
/**
* Southbridge power-on initial Public Function
*
*/
/**
* sbPowerOnInit - Config Southbridge during power on stage.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbPowerOnInit (IN AMDSBCFG* pConfig);
/**
* XhciEarlyInit - XhciEarlyInit.
*
*
*
*
*
*/
void XhciEarlyInit (void);
/**
* XhciInitIndirectReg - XhciInitIndirectReg.
*
*
*
*
*
*/
void XhciInitIndirectReg (void);
// Southbridge Common Routines
/**
* Southbridge Common Public Function
*
*/
/**
* commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
*
* This settings should be done during S3 resume also
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void commonInitEarlyBoot (IN AMDSBCFG* pConfig);
/**
* commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
*
* This settings might not program during S3 resume
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void commonInitEarlyPost (IN AMDSBCFG* pConfig);
/**
* commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void commonInitLateBoot (IN AMDSBCFG* pConfig);
/**
* abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* hpetInit - Program Southbridge HPET function
*
* ** Eric
*
* @param[in] pConfig Southbridge configuration structure pointer.
* @param[in] pStaticOptions Platform build configuration table.
*
*/
void hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);
/**
* c3PopupSetting - Program Southbridge C state function
*
* ** Eric
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void c3PopupSetting (IN AMDSBCFG* pConfig);
/**
* GcpuRelatedSetting - Program GCPU C related function
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void GcpuRelatedSetting (IN AMDSBCFG* pConfig);
/**
* MtC1eEnable - Program Mt C1E Enable Function
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void MtC1eEnable (IN AMDSBCFG* pConfig);
/**
* Southbridge Common Private Function
*
*/
/**
* abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);
// Southbridge SATA Routines
/**
* Southbridge SATA Controller Public Function
*
*/
/**
* sataInitMidPost - Config SATA controller in Middle POST.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sataInitMidPost (IN AMDSBCFG* pConfig);
/**
* sataInitAfterPciEnum - Config SATA controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sataInitAfterPciEnum (IN AMDSBCFG* pConfig);
/**
* sataInitBeforePciEnum - Config SATA controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sataInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* sataInitLatePost - Prepare SATA controller to boot to OS.
*
* - Set class ID to AHCI (if set to AHCI * Mode)
* - Enable AHCI interrupt
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sataInitLatePost (IN AMDSBCFG* pConfig);
// Southbridge GEC Routines
/**
* Southbridge GEC Controller Public Function
*
*/
/**
* gecInitBeforePciEnum - Config GEC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void gecInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* gecInitAfterPciEnum - Config GEC controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void gecInitAfterPciEnum (IN AMDSBCFG* pConfig);
/**
* gecInitLatePost - Prepare GEC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void gecInitLatePost (IN AMDSBCFG* pConfig);
// Southbridge USB Routines
/**
* Southbridge USB Controller Public Function
*
*/
/**
* Config USB controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void usbInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* Config USB controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void usbInitAfterPciInit (IN AMDSBCFG* pConfig);
/**
* Config USB controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void usbInitLate (IN AMDSBCFG* pConfig);
/**
* Config USB1 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
void usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
void usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
void usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
void usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
void usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
void usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
// Southbridge SMI Service Routines (SMM.C)
/**
* Southbridge SMI Service Routines Public Function
*
*/
/**
* Southbridge SMI service module
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbSmmService (IN AMDSBCFG* pConfig);
/**
* softwareSMIservice - Software SMI service
*
* ** Eric
*
* @param[in] VOID Southbridge software SMI service ID.
*
*/
void softwareSMIservice (IN void);
// Southbridge GPP Controller Routines
/**
* Southbridge GPP Controller Routines Public Function
*
*/
/**
* GPP early programming and link training. On exit all populated EPs should be fully operational.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);
/**
* sbPcieGppLateInit - Late PCIE initialization for Hudson-2 GPP component
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void sbPcieGppLateInit (IN AMDSBCFG* pConfig);
// Southbridge HD Controller Routines (AZALIA.C)
/**
* Southbridge HD Controller Routines (AZALIA.C) Public Function
*
*/
/**
* Config HD Audio Before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* Config HD Audio after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
// Southbridge EC Routines
#ifndef NO_EC_SUPPORT
/**
* Southbridge EC Controller Public Function
*
*/
/**
* Config EC controller during power-on
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void ecPowerOnInit (IN AMDSBCFG* pConfig);
/**
* Config EC controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void ecInitBeforePciEnum (IN AMDSBCFG* pConfig);
/**
* Prepare EC controller to boot to OS.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void ecInitLatePost (IN AMDSBCFG* pConfig);
/**
* validateImcFirmware - Validate IMC Firmware.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
* @retval TRUE Pass
* @retval FALSE Failed
*/
unsigned char validateImcFirmware (IN AMDSBCFG* pConfig);
/**
* validateImcFirmware - Validate IMC Firmware.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void softwareToggleImcStrapping (IN AMDSBCFG* pConfig);
#endif
#ifndef NO_HWM_SUPPORT
/**
* hwmInit - Init Hardware Monitor.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void hwmInit (IN AMDSBCFG* pConfig);
/**
* hwmUpdateData - Hardware Monitor Update Data.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void hwmUpdateData (IN AMDSBCFG* pConfig);
/**
* hwmUpdateData - Hardware Monitor Update Data.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void hwmCopyFanControl (IN AMDSBCFG* pConfig);
/**
* hwmCopyFanControl - Copy Hardware Monitor Update Data.
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
#endif
/**
* Stress Reset Mode Late
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
void StressResetModeLate (IN AMDSBCFG* pConfig);
/**
* TurnOffCG2
*
*
* @retval VOID
*
*/
void TurnOffCG2 (OUT void);
/**
* BackUpCG2
*
*
* @retval VOID
*
*/
void BackUpCG2 (OUT void);

1389
src/vendorcode/amd/cimx/sb900/SbType.h Executable file
View File

File diff suppressed because it is too large Load Diff

88
src/vendorcode/amd/cimx/sb900/Smm.c Executable file
View File

@ -0,0 +1,88 @@
/**
* @file
*
* Southbridge SMM service function
*
* Prepare SMM service module for IBV call Southbridge SMI service routine.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
//
// Declaration of local functions
//
/**
* Southbridge SMI service module
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbSmmService (
IN AMDSBCFG* pConfig
)
{
AMDSBCFG* pTmp; //lx-dummy for /W4 build
pTmp = pConfig;
TRACE ((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
}
/**
* softwareSMIservice - Software SMI service
*
* @param[in] VOID Southbridge software SMI service ID.
*
*/
VOID
softwareSMIservice (
IN VOID
)
{
TRACE ((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
}

983
src/vendorcode/amd/cimx/sb900/Usb.c Executable file
View File

@ -0,0 +1,983 @@
/**
* @file
*
* Config Southbridge USB controller
*
* Init USB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: CIMx-SB
* @e sub-project:
* @e \$Revision:$ @e \$Date:$
*
*/
/*;********************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*********************************************************************************/
#include "SbPlatform.h"
#include "cbtypes.h"
#include "AmdSbLib.h"
#include "Hudson-2.h"
//
// Declaration of local functions
//
VOID
usbOverCurrentControl (
IN AMDSBCFG* pConfig
);
UINT32
SetEhciPllWr (
IN UINT32 Value,
IN AMDSBCFG* pConfig
);
/**
* EhciInitAfterPciInit - Config USB controller after PCI emulation
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] pConfig Southbridge configuration structure pointer.
*/
VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
/**
* OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation
*
* @param[in] Value Controller PCI config address (bus# + device# + function#)
* @param[in] pConfig Southbridge configuration structure pointer.
*/
VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);
#ifdef XHCI_SUPPORT
VOID XhciInitBeforePciInit (IN AMDSBCFG* pConfig);
VOID XhciInitAfterPciInit (IN AMDSBCFG* pConfig);
VOID XhciInitLate (IN AMDSBCFG* pConfig);
#endif
/**
* usbInitBeforePciEnum - Config USB controller before PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usbInitBeforePciEnum (
IN AMDSBCFG* pConfig
)
{
UINT8 XhciEfuse;
// add Efuse checking for Xhci enable/disable
XhciEfuse = XHCI_EFUSE_LOCATION;
TRACE ((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
// Disabled All USB controller
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0);
// Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
// Enable UsbResumeEnable (USB PME) * Default value
// In SB700 USB SleepCtrl set as BIT10+BIT9, but Hudson-2 default is BIT9+BIT8 (6 uframes)
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9);
// Overwrite EHCI bit by OHCI bit
pConfig->USBMODE.UsbModeReg = pConfig->USBMODE.UsbMode.Ohci1 \
+ (pConfig->USBMODE.UsbMode.Ohci1 << 1) \
+ (pConfig->USBMODE.UsbMode.Ohci2 << 2) \
+ (pConfig->USBMODE.UsbMode.Ohci2 << 3) \
+ (pConfig->USBMODE.UsbMode.Ohci3 << 4) \
+ (pConfig->USBMODE.UsbMode.Ohci3 << 5) \
+ (pConfig->USBMODE.UsbMode.Ohci4 << 6);
// Overwrite EHCI3/OHCI3 by XhciSwitch
if (pConfig->XhciSwitch) {
pConfig->USBMODE.UsbModeReg &= 0xCF;
pConfig->USBMODE.UsbModeReg |= 0x80;
} else {
pConfig->USBMODE.UsbModeReg &= 0x7F;
#ifdef USB_LOGO_SUPPORT
if (pConfig->USBMODE.UsbMode.Ohci3) {
RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_Usbwakup2, AccWidthUint8, 0, 0x0B);
}
#endif
}
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, (pConfig->USBMODE.UsbModeReg));
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEE, AccWidthUint8, ~(BIT2), 0 );
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, (pConfig->USBMODE.UsbModeReg & ~( 0x15 << 1 )) + (( pConfig->USBMODE.UsbModeReg & 0x15 ) << 1 ) );
// if ( pConfig->XhciSwitch == 1 && pConfig->S3Resume == 0 && pConfig->S4Resume == 0 ) {
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7) , BIT7);
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5) , 0);
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEE, AccWidthUint8, ~(BIT0 + BIT1 + BIT2), (BIT1 + BIT0 + BIT2) );
// }
// else {
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7) , ~(BIT7));
// }
// RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccWidthUint8, ~BIT6, 0);
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + 0xF3, AccWidthUint8, ~BIT4, BIT4);
// SbStall (500);
// RWMEM (ACPI_MMIO_BASE + PMIO_BASE + 0xF3, AccWidthUint8, ~BIT4, 0);
#ifdef XHCI_SUPPORT
#ifndef XHCI_INIT_IN_ROM_SUPPORT
if ( pConfig->XhciSwitch == 1 ) {
if ( pConfig->S3Resume == 0 ) {
XhciInitBeforePciInit (pConfig);
} else {
XhciInitIndirectReg ();
}
} else {
// for power saving.
// add Efuse checking for Xhci enable/disable
getEfuseStatus (&XhciEfuse);
if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0);
}
}
#endif
#endif
}
/**
* usbInitAfterPciInit - Config USB controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usbInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
if (IsSbA11 ()) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0x7F);
}
usb1EhciInitAfterPciInit (pConfig);
usb2EhciInitAfterPciInit (pConfig);
usb3EhciInitAfterPciInit (pConfig);
usb3OhciInitAfterPciInit (pConfig);
usb1OhciInitAfterPciInit (pConfig);
usb2OhciInitAfterPciInit (pConfig);
usb4OhciInitAfterPciInit (pConfig);
// Restore back
if (IsSbA11 ()) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, (pConfig->USBMODE.UsbModeReg));
}
#ifdef XHCI_SUPPORT
if ( pConfig->XhciSwitch == 1 ) {
XhciInitAfterPciInit (pConfig);
}
#endif
if ( pConfig->UsbPhyPowerDown ) {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0);
} else {
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0);
}
if (IsSbA13Plus ()) {
//SB02643
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4, AccWidthUint8, ~BIT7, BIT7);
//RPR7.27 SB02686
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT2, BIT2);
}
}
/**
* usbOverCurrentControl - Config USB Over Current Control
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usbOverCurrentControl (
IN AMDSBCFG* pConfig
)
{
#ifdef SB_USB1_OVER_CURRENT_CONTROL
RWPCI ((USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xfff00000, SB_USB1_OVER_CURRENT_CONTROL & 0x000FFFFF);
#endif
#ifdef SB_USB2_OVER_CURRENT_CONTROL
RWPCI ((USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xfff00000, SB_USB2_OVER_CURRENT_CONTROL & 0x000FFFFF);
#endif
#ifdef SB_USB3_OVER_CURRENT_CONTROL
RWPCI ((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xffff0000, SB_USB3_OVER_CURRENT_CONTROL & 0x0000FFFF);
#endif
#ifdef SB_USB4_OVER_CURRENT_CONTROL
RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG58, AccWidthUint32 | S3_SAVE, 0xffffff00, SB_USB4_OVER_CURRENT_CONTROL & 0x000000FF);
#endif
#ifdef SB_XHCI0_OVER_CURRENT_CONTROL
RWXhci0IndReg ( SB_XHCI_IND_REG04, 0xFF00FFFF, (SB_XHCI0_OVER_CURRENT_CONTROL & 0xFF) << 16);
#endif
#ifdef SB_XHCI1_OVER_CURRENT_CONTROL
RWXhci1IndReg ( SB_XHCI_IND_REG04, 0xFF00FFFF, (SB_XHCI1_OVER_CURRENT_CONTROL & 0xFF) << 16);
#endif
}
/**
* usbInitLate - Config USB controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usbInitLate (
IN AMDSBCFG* pConfig
)
{
if (pConfig->S4Resume) {
//RWPCI (0x9004, AccWidthUint8, 0, 0x10);
//RWPCI (0x9804, AccWidthUint8, 0, 0x10);
//RWPCI (0xA504, AccWidthUint8, 0, 0x10);
//RWPCI (0xB004, AccWidthUint8, 0, 0x10);
//RWPCI (0x903C, AccWidthUint8, 0, 0x12);
//RWPCI (0x983C, AccWidthUint8, 0, 0x12);
//RWPCI (0xA53C, AccWidthUint8, 0, 0x12);
//RWPCI (0xB03C, AccWidthUint8, 0, 0x12);
}
#ifdef XHCI_SUPPORT
if ( pConfig->XhciSwitch == 1 ) {
XhciInitLate (pConfig);
}
#endif
SbEnableUsbIrq1Irq12ToPicApic ();
usbOverCurrentControl (pConfig);
}
/**
* usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb1EhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);
EhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb2EhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);
EhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb3EhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);
EhciInitAfterPciInit (ddDeviceId, pConfig);
}
VOID
EhciInitAfterPciInit (
IN UINT32 Value,
IN AMDSBCFG* pConfig
)
{
UINT32 ddBarAddress;
UINT32 ddVar;
UINT32 ddDrivingStrength;
UINT32 ddPortDrivingStrength;
UINT32 portNumber;
UINT32 port;
ddDrivingStrength = 0;
portNumber = 0;
//Get BAR address
ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
//Enable Memory access
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
if (pConfig->BuildParameters.EhciSsid != NULL ) {
RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
}
//USB Common PHY CAL & Control Register setting
ddVar = 0x00020F00;
WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
// RPR IN AND OUT DATA PACKET FIFO THRESHOLD
// EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
// RPR EHCI Dynamic Clock Gating Feature
// RPR Enable Global Clock Gating (BIT14)
RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~(BIT12 + BIT14), BIT12 + BIT14);
RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16, ~BIT12, BIT12);
// RPR Enable adding extra flops to PHY rsync path
// Step 1:
// EHCI_BAR 0xB4 [6] = 1
// EHCI_BAR 0xB4 [7] = 0
// EHCI_BAR 0xB4 [12] = 0 ("VLoad")
// All other bit field untouched
// Step 2:
// EHCI_BAR 0xB4[12] = 1
//RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00);
//RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
// RPR7.8 USB 2.0 Ports Driving Strength
// Step1 is done by default
// Add support USBx_EHCI_DRIVING_STRENGTH port4 is at [19:16] and port0 is [3:0]; 4 bits for per port, [3] is enable,[2:0] is driving strength.
// For Cobia, USB3_EHCI_DRIVING_STRENGTH = 0x00CC
#ifdef USB1_EHCI_DRIVING_STRENGTH
if (Value == (USB1_EHCI_BUS_DEV_FUN << 16)) {
ddDrivingStrength = USB1_EHCI_DRIVING_STRENGTH;
portNumber = 5;
}
#endif
#ifdef USB2_EHCI_DRIVING_STRENGTH
if (Value == (USB2_EHCI_BUS_DEV_FUN << 16)) {
ddDrivingStrength = USB2_EHCI_DRIVING_STRENGTH;
portNumber = 5;
}
#endif
#ifdef USB3_EHCI_DRIVING_STRENGTH
if (Value == (USB3_EHCI_BUS_DEV_FUN << 16)) {
ddDrivingStrength = USB3_EHCI_DRIVING_STRENGTH;
portNumber = 4;
}
#endif
if (portNumber > 0) {
for (port = 0; port < portNumber; port ++) {
ddPortDrivingStrength = (ddDrivingStrength >> (port * 4)) & 0x0F;
if (ddPortDrivingStrength & BIT3) {
ddPortDrivingStrength &= 0x7;
RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~ (BIT16 + BIT15 + BIT14 + BIT13 + BIT12 + BIT2 + BIT1 + BIT0), (port << 13) + ddPortDrivingStrength);
RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
}
}
}
// Step2
RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);
// Step3
if (IsSbA11 ()) {
RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, (UINT32) (~ 0x00000f00), 0x00000000);
RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, (UINT32) (~ 0x0000ff00), 0x00001500);
} else {
RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, (UINT32) (~ 0x00000f00), 0x00000200);
RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, (UINT32) (~ 0x0000ff00), 0x00000f00);
}
//Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 6)), (0x01 << 6));
//RPR 7.13 EHCI Async Park Mode
//Set EHCI_pci_configx50[11:8]=0x1
//Set EHCI_pci_configx50[15:12]=0x1
//Set EHCI_pci_configx50[17]=0x1
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x0F << 8)), (0x01 << 8));
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x0F << 12)), (0x01 << 12));
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 17)), (0x01 << 17));
//RPR Enabling EHCI Async Stop Enhancement
//Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 29)), (0x01 << 29));
//RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFF7F0FFF, 0x20221140);
// RPR recommended setting "EHCI Advance PHY Power Savings"
// Set EHCI_pci_configx50[31]='1'
// Fix for EHCI controller driver yellow sign issue under device manager
// when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15);
// ENH246436: Disable USB data cache to resolve USB controller hang issue with Lan adaptor.
// EHCI PCI config register 50h bit 26 to `1'.
if (pConfig->EhciDataCacheDis) {
RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT10);
}
if (IsSbA13Plus ()) {
//RPR 7.25 SB02674
RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint16 | S3_SAVE, (UINT16)0x5FFF, BIT13 + BIT15);
//RPR 7.26 SB02684
RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, ~ (BIT3), BIT3);
//RPR 7.26 SB02687
RWPCI ((UINT32) Value + SB_EHCI_REG54 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFC, BIT0 + BIT1);
//RPR 7.28 SB02700
RWPCI ((UINT32) Value + SB_EHCI_REG54 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFB, BIT2);
//RPR 7.29 SB02703
RWPCI ((UINT32) Value + SB_EHCI_REG54 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFF7, BIT3);
}
// RPR USB Delay A-Link Express L1 State
// RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1
// RPR Enable empty list mode. x54[3]
// RPR Enable "L1 Early Exit" functionality. 0x54 [6:5] = 0x3 0x54 [9:7] = 0x4
// RPR EHCI PING Response Fix Enable 0x54 [1] = 0x1
RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, 0x0000026b);
if ( pConfig->BuildParameters.UsbMsi) {
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00);
}
if (IsSbA12Plus ()) {
// RPR 7.24 Long Delay on Framelist Read Causing EHCI DMA to Address 0 - Fix
// RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT13, BIT13);
// RPR 7.25 LS connection can't wake up system from S3/S4/S5 when EHCI owns the port - Fix
RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT4, BIT4);
// RPR 7.30 EHCI lMU Hangs when Run/Stop is Set First and PDC is Enabled Near End uFrame 7 - Fix Enable
RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT11, BIT11);
}
// ENH244924: Platform specific Hudson-2/3 settings for all Sabine Platforms
// EHCI_PCI_Config 0x50[21]=1
// EHCI_PCI_Config 0x54[9:7] = 0x4
if ( IsGCPU () ) {
RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x01 << 21)), (0x01 << 21));
RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~ ((UINT32) (0x07 << 7)), (0x04 << 7));
}
// RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
} else {
// Fake Bar
ddBarAddress = 0x58830000;
WritePCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);
//Enable Memory access
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
// RPR Enable Global Clock Gating (BIT14)
RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~(BIT12 + BIT14), BIT12 + BIT14);
RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, 0);
// RWMEM (ddBarAddress + SB_EHCI_BAR_REGB0, AccWidthUint32, ~BIT5, BIT5);
}
}
/**
* usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb1OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
RWPCI ((USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG78, AccWidthUint32 | S3_SAVE, 0xffffffff, BIT28 + BIT29);
}
/**
* usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb2OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb3OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
}
/**
* usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
usb4OhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
UINT32 ddDeviceId;
ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
OhciInitAfterPciInit (ddDeviceId, pConfig);
if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {
RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
}
}
VOID
OhciInitAfterPciInit (
IN UINT32 Value,
IN AMDSBCFG* pConfig
)
{
#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
RWPCI ((UINT32) Value + SB_OHCI_REG40 + 6, AccWidthUint8 | S3_SAVE, 0xFF, 0x1F);
#endif
// Disable the MSI capability of USB host controllers
RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
if ((IsSbA11 ()) || (IsSbA12 ())) {
RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT0 + BIT5 + BIT12), 0);
} else {
RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT0 + BIT5 + BIT12), BIT0);
}
// RPR USB SMI Handshake
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
if ( pConfig->BuildParameters.OhciSsid != NULL ) {
RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
}
}
//RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
//OHCI 0_PCI_Config 0x50[30] = 1
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);
// RPR L1 Early Exit
// RPR Set OHCI Arbiter Mode.
// RPR Set Enable Global Clock Gating.
RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint8 | S3_SAVE, ~(BIT0 + BIT4 + BIT5 + BIT6 + BIT7), BIT0 + BIT4 + BIT7);
// SB02698
RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT0, 0);
// RPR 7.21 OHCI Arbiter Mode
// A13 Remove Arbitor Reset
if ( IsSbA12Plus () ) {
RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint16 | S3_SAVE, ~(BIT4 + BIT5 + BIT8), (BIT4 + BIT5 + BIT8));
} else {
RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint16 | S3_SAVE, ~(BIT4 + BIT5), (BIT4));
}
// RPR Enable OHCI SOF Synchronization.
// RPR Enable OHCI Periodic List Advance.
RWPCI ((UINT32) Value + SB_OHCI_REG50 + 2, AccWidthUint8 | S3_SAVE, ~(BIT3 + BIT4), BIT3 + BIT4);
if ( pConfig->BuildParameters.UsbMsi) {
RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);
RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);
}
//7.23 USB1.1 full-speed false crc errors detected. Issue - fix enable
if ( IsSbA12Plus () ) {
RWPCI ((UINT32) Value + SB_OHCI_REG80, AccWidthUint32 | S3_SAVE, (UINT32) (~(0x01 << 10)), (UINT32) (0x01 << 10));
}
}
UINT32
SetEhciPllWr (
IN UINT32 Value,
IN AMDSBCFG* pConfig
)
{
UINT32 ddRetureValue;
UINT32 ddBarAddress;
UINT16 dwVar;
UINT16 dwData;
UINT8 portSC;
ddRetureValue = 0;
dwData = 0;
// Memory, and etc.
//_asm { jmp $};
RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00);
RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02);
// Get Bar address
ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress);
for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) {
// Get OHCI command registers
ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar);
if ( dwVar & BIT6 ) {
ddRetureValue = ddBarAddress + portSC;
RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0);
for (;;) {
SbStall (5);
ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData);
if (dwData == 0x1005) break;
}
dwData = 0;
}
}
return ddRetureValue;
}
#ifdef XHCI_SUPPORT
/*
VOID
XhciInitIndirectReg (
)
{
UINT32 ddDrivingStrength;
UINT32 port;
ddDrivingStrength = 0;
port = 0;
#ifdef SB_USB_BATTERY_CHARGE_SUPPORT
RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030);
#endif
//
// RPR SuperSpeed PHY Configuration (adaptation mode setting)
//
RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021);
RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021);
//
// RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings)
//
RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A);
RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A);
//
// RPR BLM Meaasge
//
RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000);
#ifdef USB3_EHCI_DRIVING_STRENGTH
//
// RPR 8.13 xHCI USB 2.0 PHY Settings
// Step 1 is done by hardware default
// Step 2
for (port = 0; port < 4; port ++) {
ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF;
if (ddDrivingStrength & BIT3) {
ddDrivingStrength &= 0x07;
if (port < 2) {
RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E78, (port << 13) + ddDrivingStrength);
RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
} else {
RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E78, ((port - 2) << 13) + ddDrivingStrength);
RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000);
}
}
}
#endif
#ifdef USB_LOGO_SUPPORT
//for D3 USB LOGO [6:0]= 4; [8:7] = 3; [12] = 0; [16:13] port;
for (port = 0; port < 4; port ++) {
if (port < 2) {
RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E00, (port << 13) + 0x184 );
} else {
RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0E00, ((port - 2) << 13) + 0x184 );
}
}
#endif
// Step 3
if (IsSbA11 ()) {
RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8)));
RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8)));
} else {
RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)));
RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8)));
}
}
*/
VOID
XhciA12Fix (
VOID
)
{
//
// 8.14 PLUG/UNPLUG of USB 2.0 devices make the XHCI USB 2.0 ports unfunctional - fix enable
// ACPI_USB3.0_REG 0x20[12:11] = 2'b11
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x3 << 11)), (UINT32) (0x3 << 11));
//
// 8.15 XHC 2 USB2 ports interactional issue - fix enable
// ACPI_USB3.0_REG 0x20[16] = 1'b1
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
//
// 8.16 xHCI USB 2.0 Ports Suspend Enhancement
// ACPI_USB3.0_REG 0x20[15] = 1'b1
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x1 << 15)), (UINT32) (0x1 << 15));
//
// 8.17 XHC HS/FS IN Data Buffer Underflow issue - fix enable
// ACPI_USB3.0_REG 0x20[20:18] = 0x7
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~((UINT32) (0x7 << 18)), (UINT32) (0x7 << 18));
//
// 8.18 Allow XHCI to Resume from S3 Enhancement
// ACPI_USB3.0_REG 0x98[19] = 1'b1
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG98, AccWidthUint32, ~((UINT32) (0x1 << 19)), (UINT32) (0x1 << 19));
//
// 8.19 Assign xHC1 ( Dev 16 function 1) Interrupt Pin register to INTB#
// ACPI_PMIO_F0[18] =1
//
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 18)), (UINT32) (0x1 << 18));
//
// 8.20 Allow B-Link Clock Gating when EHCI3/OHCI3 is only Controller Enabled
// ACPI_PMIO_F0[13] =1
//
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 13)), (UINT32) (0x1 << 13));
//
// 8.21 Access register through JTAG fail when switch from XHCI to EHCI/OHCI - Fix enable
// ACPI_PMIO_F0[17] =1
//
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 17)), (UINT32) (0x1 << 17));
//
// 8.22 USB leakage current on differential lines when ports are switched to XHCI - Fix enable
// ACPI_PMIO_F0[14] =1
//
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 14)), (UINT32) (0x1 << 14));
// RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_xHC0Pme, AccWidthUint16, 0, 0x0B0B);
//
// 8.26 Fix for Incorrect Gated Signals in xhc_to_s5
// ACPI_PMIO_F0[16] =1
//
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint32, ~((UINT32) (0x1 << 16)), (UINT32) (0x1 << 16));
}
VOID
XhciInitBeforePciInit (
IN AMDSBCFG* pConfig
)
{
UINT16 BcdAddress;
UINT16 BcdSize;
UINT16 AcdAddress;
UINT16 AcdSize;
UINT16 FwAddress;
UINT16 FwSize;
UINTN XhciFwStarting;
UINT32 SpiValidBase;
UINT32 RegData;
UINT16 i;
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700);
SbStall (20);
//
// Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address)
//
GetRomSigPtr (&XhciFwStarting);
if (XhciFwStarting == 0) {
return;
}
XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET);
if (IsLpcRom ()) {
//XHCI firmware re-load
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0));
RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting));
}
//
// RPR Enable SuperSpeed receive special error case logic. 0x20 bit8
// RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9
// Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700);
//
// RPR SuperSpeed PHY Configuration (adaptation timer setting)
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
//RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA);
//
// Step 1. to enable Xhci IO and Firmware load mode
//
#ifdef XHCI_SUPPORT_ONE_CONTROLLER
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001);
#else
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003);
#endif
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000);
//
// Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16));
BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET);
BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize);
AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET);
AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize);
SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD;
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase);
//
// Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0
//
for (i = 0; i < SPI_HEAD_LENGTH; i++) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i));
}
for (i = 0; i < BcdSize; i++) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i));
}
for (i = 0; i < AcdSize; i++) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i));
}
//
// Step 3. to enable the instruction RAM preload functionality.
//
FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress));
FwAddress += 2;
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress);
FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize);
//
// Set the starting address offset for Instruction RAM preload.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0);
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29);
for (;;) {
ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
if (RegData & BIT30) break;
}
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0);
//
// Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset
for (;;) {
ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData);
if (RegData & U3PLL_LOCK) break;
}
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset
// RPR 8.8 SuperSpeed PHY Configuration, it is only for A11.
if (IsSbA11 ()) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); //
}
XhciInitIndirectReg ();
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices
if (!(pConfig->S4Resume)) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
}
//
// Step 5.
//
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18);
// Step 5.
if (IsSbA12Plus ()) {
XhciA12Fix ();
}
//8.22 UMI Lane Configuration Information for XHCI Firmware to Calculate the Bandwidth for USB 3.0 ISOC Devices
if (!(IsUmiOneLaneGen1Mode ())) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~(BIT25 + BIT24), BIT24);
}
}
VOID
XhciInitAfterPciInit (
IN AMDSBCFG* pConfig
)
{
// RPR8.12 Block Write to DID & SID to pass DTM
RWXhciIndReg ( SB_XHCI_IND_REG04, ~BIT8, BIT8);
if (IsSbA13Plus ()) {
//8.23 FS/LS devices not functional after resume from S4 fix enable (SB02699)
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, ~(BIT22), BIT22);
}
//8.24 XHC USB2.0 Hub disable issue fix enable (SB02702)
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint32, ~(BIT20), BIT20);
}
VOID
XhciInitLate (
IN AMDSBCFG* pConfig
)
{
//OBS221599: USB 3.0 controller shows bang in Windows Device Manager
UINT8 Data;
if ( IsSbA11 () ) {
Data = 0xB5; //
WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);
Data = 0x12; //
WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);
}
if (pConfig->S4Resume) {
RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI
SbFlashUsbSmi ();
}
}
#endif