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mb/system76/gaze17: Add Gazelle 17

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The gaze17 comes in 2 variants due to differences in the discrete GPU
and network controller used.

- NVIDIA RTX 3050, using Realtek Ethernet Controller
- NVIDIA RTX 3060, using onboard I219-V Ethernet Controller

Tested with a custom TianoCore UefiPayloadPkg payload.

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- MicroSD card reader
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S0ix suspend/resume
- Booting to Pop!_OS Linux 22.04 with kernel 5.18.10
- Internal flashing with flashrom v1.2-703-g76118a7c10ed

Not working:

- Discrete/Hybrid graphics: Requires NVIDIA driver
- mDP/HDMI displays on 3060 variant: Requires NVIDIA driver
- Detection of devices in TBT slot on boot
- S3 suspend: MP init eventually fails

Not tested:

- Thunderbolt devices

Change-Id: Ib12ac47e8f34004f72e6234039823530511baea7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Jeremy Soller
2022-07-24 15:16:59 -06:00
committed by Tim Crawford
parent c6a45cdef5
commit ef3ef9b9b7
28 changed files with 1279 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/mainboard/index.md
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@ -207,6 +207,7 @@ The boards in this section are not real mainboards, but emulators.
- [Galago Pro 5](system76/galp5.md) - [Galago Pro 5](system76/galp5.md)
- [Gazelle 15](system76/gaze15.md) - [Gazelle 15](system76/gaze15.md)
- [Gazelle 16](system76/gaze16.md) - [Gazelle 16](system76/gaze16.md)
- [Gazelle 17](system76/gaze17.md)
- [Lemur Pro 9](system76/lemp9.md) - [Lemur Pro 9](system76/lemp9.md)
- [Lemur Pro 10](system76/lemp10.md) - [Lemur Pro 10](system76/lemp10.md)
- [Lemur Pro 11](system76/lemp11.md) - [Lemur Pro 11](system76/lemp11.md)

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Documentation/mainboard/system76/gaze17.md Normal file
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# System76 Gazelle 17 (gaze17)
The gaze17 comes in 2 variants: gaze17-3050 and gaze17-3060-b.
## Specs
- CPU
- Intel Core i5-12500H
- Intel Core i7-12700H
- EC
- ITE IT5570E running [System76 EC](https://github.com/system76/ec)
- Graphics
- dGPU options
- NVIDIA GeForce RTX 3050
- NVIDIA GeForce RTX 3050 Ti
- NVIDIA GeForce RTX 3060
- Memory
- Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MT/s
- Networking
- Gigabit Ethernet
- 3050: Realtek RTL8111H controller
- 3060: Onboard Intel I219-V
- M.2 PCIe/CNVi WiFi/Bluetooth
- Intel Wi-Fi 6 AX201
- Power
- 3050: 150W (20V, 7.5A) AC barrel adapter
- 3060: 180W (20V, 9A) AC barrel adapter
- Lite-On PA-1181-76, using a C5 power cord
- 54Wh 4-cell Li-ion battery (NP50BAT-4-54)
- Sound
- Realtek ALC256 codec
- Internal speakers and microphone
- Combined 3.5mm headphone/microphone jack
- Dedicated 3.5mm microphone jack
- Storage
- 1x M.2 PCIe NVMe Gen 4 SSD
- 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
- MicroSD card reader (Realtek RTS5227S/OZ711LV2)
## Flashing coreboot
```eval_rst
+---------------------+---------------------+
| Type | Value |
+=====================+=====================+
| Socketed flash | no |
+---------------------+---------------------+
| Vendor | GigaDevice |
+---------------------+---------------------+
| Model | GD25B256E |
+---------------------+---------------------+
| Size | 32 MiB |
+---------------------+---------------------+
| Package | WSON-8 |
+---------------------+---------------------+
| Internal flashing | yes |
+---------------------+---------------------+
| External flashing | yes |
+---------------------+---------------------+
```
The position of the flash chip depends on the variant:
- 3050: U24, below the bottom DIMM slot.
- 3060: U55, left of the PCIe 4.0 M.2 slot.

72
src/mainboard/system76/gaze17/Kconfig Normal file
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if BOARD_SYSTEM76_GAZE17_3050 || BOARD_SYSTEM76_GAZE17_3060_B
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select DRIVERS_I2C_HID
select EC_SYSTEM76_EC
select EC_SYSTEM76_EC_COLOR_KEYBOARD
select EC_SYSTEM76_EC_DGPU
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE17_3060_B
select MEMORY_MAPPED_TPM
select NO_UART_ON_SUPERIO
select PCIEXP_HOTPLUG
select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
select SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_CRASHLOG
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
select TPM_MEASURED_BOOT
select TPM_RDRESP_NEED_DELAY
config MAINBOARD_DIR
default "system76/gaze17"
config MAINBOARD_PART_NUMBER
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
config MAINBOARD_SMBIOS_PRODUCT_NAME
default "Gazelle"
config MAINBOARD_VERSION
default "gaze17-3050" if BOARD_SYSTEM76_GAZE17_3050
default "gaze17-3060-b" if BOARD_SYSTEM76_GAZE17_3060_B
config VARIANT_DIR
default "3050" if BOARD_SYSTEM76_GAZE17_3050
default "3060" if BOARD_SYSTEM76_GAZE17_3060_B
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config CBFS_SIZE
default 0xA00000
config CONSOLE_POST
default y
config DIMM_SPD_SIZE
default 512
config ONBOARD_VGA_IS_PRIMARY
default y
config POST_DEVICE
default n
config UART_FOR_CONSOLE
default 0
# PM Timer Disabled, saves power
config USE_PM_ACPI_TIMER
default n
endif

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src/mainboard/system76/gaze17/Kconfig.name Normal file
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config BOARD_SYSTEM76_GAZE17_3050
bool "gaze17 3050"
config BOARD_SYSTEM76_GAZE17_3060_B
bool "gaze17 3060-b"

12
src/mainboard/system76/gaze17/Makefile.inc Normal file
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## SPDX-License-Identifier: GPL-2.0-only
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
romstage-y += romstage.c
ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

31
src/mainboard/system76/gaze17/acpi/backlight.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/intel/gma/acpi/gma.asl>
Scope (GFX0)
{
Name (BRIG, Package (22) {
40, /* default AC */
40, /* default Battery */
5,
10,
15,
20,
25,
30,
35,
40,
45,
50,
55,
60,
65,
70,
75,
80,
85,
90,
95,
100
})
}

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src/mainboard/system76/gaze17/acpi/mainboard.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
}
}

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src/mainboard/system76/gaze17/acpi/sleep.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/gpio.h>
Method (PGPM, 1, Serialized)
{
For (Local0 = 0, Local0 < 6, Local0++)
{
\_SB.PCI0.CGPM (Local0, Arg0)
}
}
/*
* Method called from _PTS prior to system sleep state entry
* Enables dynamic clock gating for all 5 GPIO communities
*/
Method (MPTS, 1, Serialized)
{
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
}
/*
* Method called from _WAK prior to system sleep state wakeup
* Disables dynamic clock gating for all 5 GPIO communities
*/
Method (MWAK, 1, Serialized)
{
PGPM (0)
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
}
/*
* S0ix Entry/Exit Notifications
* Called from \_SB.PEPD._DSM
*/
Method (MS0X, 1, Serialized)
{
If (Arg0 == 1) {
/* S0ix Entry */
PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
} Else {
/* S0ix Exit */
PGPM (0)
}
}

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src/mainboard/system76/gaze17/board_info.txt Normal file
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@ -0,0 +1,8 @@
Vendor name: System76
Board name: gaze17
Category: laptop
Release year: 2022
ROM package: WSON-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y

9
src/mainboard/system76/gaze17/bootblock.c Normal file
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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <variant/gpio.h>
void bootblock_mainboard_init(void)
{
variant_configure_early_gpios();
}

3
src/mainboard/system76/gaze17/cmos.default Normal file
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@ -0,0 +1,3 @@
boot_option=Fallback
debug_level=Debug
me_state=Enable

39
src/mainboard/system76/gaze17/cmos.layout Normal file
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# SPDX-License-Identifier: GPL-2.0-only
entries
0 384 r 0 reserved_memory
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# RTC_CLK_ALTCENTURY
400 8 r 0 century
412 4 e 6 debug_level
416 1 e 2 me_state
417 3 h 0 me_state_counter
984 16 h 0 check_sum
enumerations
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
checksums
checksum 408 983 984

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src/mainboard/system76/gaze17/devicetree.cb Normal file
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chip soc/intel/alderlake
register "common_soc_config" = "{
// Touchpad I2C bus
.i2c[0] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
},
}"
# ACPI (soc/intel/alderlake/acpi.c)
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"
register "s0ix_enable" = "1"
# FSP Memory (soc/intel/alderlake/romstage/fsp_params.c)
# Enable C6 DRAM
register "enable_c6dram" = "1"
# FSP Silicon (soc/intel/alderlake/fsp_params.c)
# FIVR configuration
# Read EXT_RAIL_CONFIG to determine bitmaps
# sudo devmem2 0xfe0011b8
# 0x0
# Read EXT_V1P05_VR_CONFIG
# sudo devmem2 0xfe0011c0
# 0x1a42000
# Read EXT_VNN_VR_CONFIG0
# sudo devmem2 0xfe0011c4
# 0x1a42000
# TODO: v1p05 voltage and vnn icc max?
register "ext_fivr_settings" = "{
.configure_ext_fivr = 1,
.v1p05_enable_bitmap = 0,
.vnn_enable_bitmap = 0,
.v1p05_supported_voltage_bitmap = 0,
.vnn_supported_voltage_bitmap = 0,
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1050,
}"
# Thermal
register "tcc_offset" = "10"
# Enable CNVi BT
register "cnvi_bt_core" = "true"
# PM Util (soc/intel/alderlake/pmutil.c)
# GPE configuration
register "pmc_gpe0_dw0" = "PMC_GPP_R"
register "pmc_gpe0_dw1" = "PMC_GPP_B"
register "pmc_gpe0_dw2" = "PMC_GPP_D"
# Actual device tree
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
#From CPU EDS(TODO)
device ref system_agent on end
device ref pcie5 off
# PCIe PEG2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
device ref tcss_root_hub on
device ref tcss_usb3_port1 on end
end
end
device ref shared_sram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref i2c0 on
# Touchpad I2C bus
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN0412""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""FTCS1000""
register "generic.desc" = ""FocalTech Touchpad""
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)"
register "generic.detect" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 38 on end
end
end
device ref heci1 on end
device ref sata on
register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
end
device ref pch_espi on
register "gen1_dec" = "0x00040069" # EC PM channel
register "gen2_dec" = "0x00fc0E01" # AP/EC command
register "gen3_dec" = "0x00fc0F01" # AP/EC debug
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref p2sb on end
device ref pmc hidden end
device ref hda on
register "pch_hda_idisp_codec_enable" = "1"
register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T"
end
device ref smbus on end
device ref fast_spi on end
end
end

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src/mainboard/system76/gaze17/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/alderlake/acpi/southbridge.asl>
#include <soc/intel/alderlake/acpi/tcss.asl>
}
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
}
#include "acpi/mainboard.asl"
}

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src/mainboard/system76/gaze17/ramstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/ramstage.h>
#include <variant/gpio.h>
void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
params->CnviRfResetPinMux = 0x194CE404; // GPP_F4
params->CnviClkreqPinMux = 0x394CE605; // GPP_F5
params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6
params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7
params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12
params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
variant_configure_gpios();
}

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src/mainboard/system76/gaze17/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/util.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
static const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
.ddr_config = {
.dq_pins_interleaved = false,
},
};
static const struct mem_spd spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
[0] = { .addr_dimm[0] = 0x50, },
[1] = { .addr_dimm[0] = 0x52, },
},
};
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
const bool half_populated = false;
// Enable audio link
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
}

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src/mainboard/system76/gaze17/variants/3050/data.vbt Normal file
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src/mainboard/system76/gaze17/variants/3050/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
#include <variant/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_CFG_GPO(GPD7, 0, DEEP), // GPD7_REST
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LANPHYPC
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
PAD_NC(GPP_A6, NONE),
PAD_NC(GPP_A7, NONE),
PAD_CFG_GPO(GPP_A8, 1, PLTRST), // SATA_PWR_EN
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N
PAD_NC(GPP_A11, NONE),
PAD_NC(GPP_A12, NONE),
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
//PAD_CFG_GPO(GPP_A14, 0, DEEP), // GPP_A14
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2), // PCH_DP_HPD
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), // USB_OC3#
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWROK_PCH
PAD_CFG_GPO(GPP_A20, 0, DEEP), // PEX_WAKE#
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_CFG_GPO(GPP_B7, 1, DEEP), // CARD_PWR_EN
PAD_CFG_GPO(GPP_B8, 1, DEEP), // CARD_RTD3_RST#
//PAD_NC(GPP_B9, NONE),
//PAD_NC(GPP_B10, NONE),
PAD_NC(GPP_B11, NONE),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPO(GPP_B18, 0, DEEP), // GPP_B18_STRAP
//PAD_NC(GPP_B19, NONE),
//PAD_NC(GPP_B20, NONE),
//PAD_NC(GPP_B21, NONE),
//PAD_NC(GPP_B22, NONE),
PAD_CFG_GPO(GPP_B23, 0, DEEP), // GPP_B23_STRAP
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
PAD_NC(GPP_C3, NONE), // SML0_CLK
PAD_NC(GPP_C4, NONE), // SML0_DATA
PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C5_STRAP
PAD_NC(GPP_C6, NONE), // TBT_I2C_SCL
PAD_NC(GPP_C7, NONE), // TBT_I2C_SDA
//PAD_NC(GPP_C8, NONE),
//PAD_NC(GPP_C9, NONE),
//PAD_NC(GPP_C10, NONE),
//PAD_NC(GPP_C11, NONE),
//PAD_NC(GPP_C12, NONE),
//PAD_NC(GPP_C13, NONE),
//PAD_NC(GPP_C14, NONE),
//PAD_NC(GPP_C15, NONE),
//PAD_NC(GPP_C16, NONE),
//PAD_NC(GPP_C17, NONE),
//PAD_NC(GPP_C18, NONE),
//PAD_NC(GPP_C19, NONE),
//PAD_NC(GPP_C20, NONE),
//PAD_NC(GPP_C21, NONE),
//PAD_NC(GPP_C22, NONE),
//PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_NC(GPP_D2, NONE),
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // GPIO_LAN_EN
//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD1_CLKREQ#
//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2), // I_MDP_CLK
PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2), // I_MDP_DATA
PAD_NC(GPP_D13, NONE),
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
PAD_CFG_GPO(GPP_D15, 1, DEEP), // LANRTD3_WAKE#
PAD_CFG_GPO(GPP_D16, 1, PLTRST), // LAN_RTD3_EN#
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
PAD_NC(GPP_E4, NONE),
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPO(GPP_E6, 0, DEEP), // GPP_E6_STRAP
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_CFG_GPO(GPP_E10, 0, DEEP), // KBLED_DET
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_NC(GPP_E12, NONE),
PAD_CFG_GPO(GPP_E13, 0, DEEP), // BOARD_ID4
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_NC(GPP_E16, NONE),
PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
PAD_NC(GPP_E18, NONE),
PAD_NC(GPP_E19, NONE), // GPP_E19_STRAP
PAD_NC(GPP_E20, NONE),
PAD_NC(GPP_E21, NONE),
PAD_NC(GPP_E22, NONE), // GPP_E21_STRAP
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // CNVI_CLKREQ
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_NC(GPP_F7, NONE),
//PAD_NC(GPP_F8, NONE),
PAD_NC(GPP_F9, NONE),
PAD_CFG_GPO(GPP_F10, 1, DEEP), // PCIE_GLAN_RST#
PAD_NC(GPP_F11, NONE), // ADDS_CODE
PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R
PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_NC(GPP_F14, NONE), // LIGHT_KB_DET#
PAD_NC(GPP_F15, NONE),
PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
PAD_NC(GPP_F17, NONE),
PAD_CFG_GPO(GPP_F18, 0, DEEP), // DGPU_OVRM
//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // GLAN_CLKREQ#
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
PAD_NC(GPP_F21, NONE),
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), // VNN_CTRL
PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), // V1P05_CTRL
/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_CFG_GPO(GPP_H1, 1, DEEP), // M.2_PLT_RST_CNTRL2#
PAD_CFG_GPO(GPP_H2, 1, DEEP), // M.2_PLT_RST_CNTRL3#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_CFG_GPI(GPP_H6, NONE, DEEP), // PCH_I2C_SDA
PAD_CFG_GPI(GPP_H7, NONE, DEEP), // PCH_I2C_SCL
PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
PAD_NC(GPP_H12, NONE),
_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000), // DEVSLP1
//PAD_NC(GPP_H14, NONE),
PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK
//PAD_NC(GPP_H16, NONE),
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_H19, NONE),
PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), // PM_CLKRUN#
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT_L
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
PAD_NC(GPP_R5, NONE),
PAD_CFG_GPO(GPP_R6, 0, DEEP), // GPPR_DMIC_CLK
PAD_CFG_GPO(GPP_R7, 0, DEEP), // GPPR_DMIC_DATA
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void variant_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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src/mainboard/system76/gaze17/variants/3050/gpio_early.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
};
void variant_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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src/mainboard/system76/gaze17/variants/3050/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC256 */
0x10ec0256, /* Vendor ID */
0x1558866d, /* Subsystem ID */
11, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x1558866d),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
};
const u32 pc_beep_verbs[] = {
// Adjust mic coefficient
0x02050007,
0x02040202,
};
AZALIA_ARRAY_SIZES;

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src/mainboard/system76/gaze17/variants/3050/include/variant/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif

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src/mainboard/system76/gaze17/variants/3050/overridetree.cb Normal file
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chip soc/intel/alderlake
device domain 0 on
subsystemid 0x1558 0x866d inherit
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
register "ddi_ports_config" = "{
[DDI_PORT_A] = DDI_ENABLE_HPD,
[DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC,
}"
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
# FIXME: Breaks suspend with WD drives
#chip soc/intel/common/block/pcie/rtd3
# # XXX: Enable tied to 3.3VS?
# #register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
# register "reset_delay_ms" = "100"
# register "reset_off_delay_ms" = "100"
# register "srcclk_pin" = "0" # SSD0_CLKREQ#
# device generic 0 on end
#end
end
device ref xhci on
# USB2
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1
end
device ref pcie_rp5 on
# PCIe RP#5 x4, Clock 1 (SSD)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "disable_l23" = "true"
register "srcclk_pin" = "1" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp9 on
# PCIe RP#9 x1, Clock 6 (GLAN)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to VDD3?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "6" # GLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp10 on
# PCIe RP#10 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(10)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp11 on
# PCIe RP#11 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(11)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end
end
end
end
end

BIN
src/mainboard/system76/gaze17/variants/3060/data.vbt Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
#include <variant/gpio.h>
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap 16)
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0
PAD_NC(GPP_A6, NONE),
PAD_NC(GPP_A7, NONE),
PAD_NC(GPP_A8, NONE),
PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
PAD_NC(GPP_A11, NONE),
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), // SATAGP1
PAD_CFG_GPO(GPP_A13, 1, PLTRST), // BT_EN
//PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // DP_E_HPD
PAD_NC(GPP_A16, NONE), // USB_OC3#
PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN#
_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
PAD_CFG_GPI(GPP_A20, NONE, PLTRST), // PEG_WAKE#
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
//PAD_CFG_GPO(GPP_B9, 0, DEEP),
//PAD_CFG_GPO(GPP_B10, 0, DEEP),
PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000), // SATA_LED#
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_CFG_GPO(GPP_B18, 0, DEEP), // Strap 2 of 24
//PAD_CFG_GPO(GPP_B19, 0, DEEP),
//PAD_CFG_GPO(GPP_B20, 0, DEEP),
//PAD_CFG_GPO(GPP_B21, 0, DEEP),
//PAD_CFG_GPO(GPP_B22, 0, DEEP),
PAD_CFG_GPO(GPP_B23, 0, DEEP), // Strap 8 of 24
/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
PAD_CFG_GPO(GPP_C2, 1, PLTRST), // SATA_M2_PWR_EN1
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
PAD_CFG_GPO(GPP_C5, 0, DEEP), // Strap 4 of 24
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // SML1_CLK
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // SML1_DATA
//PAD_NC(GPP_C8, NONE),
//PAD_NC(GPP_C9, NONE),
//PAD_NC(GPP_C10, NONE),
//PAD_NC(GPP_C11, NONE),
//PAD_NC(GPP_C12, NONE),
//PAD_NC(GPP_C13, NONE),
//PAD_NC(GPP_C14, NONE),
//PAD_NC(GPP_C15, NONE),
//PAD_NC(GPP_C16, NONE),
//PAD_NC(GPP_C17, NONE),
//PAD_NC(GPP_C18, NONE),
//PAD_NC(GPP_C19, NONE),
//PAD_NC(GPP_C20, NONE),
//PAD_NC(GPP_C21, NONE),
//PAD_NC(GPP_C22, NONE),
//PAD_NC(GPP_C23, NONE),
/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPI(GPP_D4, NONE, DEEP), // PS8461_SW
//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // PEX4_SSD_CLKREQ#
//PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), // SSD_CLKREQ#
//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // PEQ_CLKREQ#
PAD_NC(GPP_D9, NONE),
PAD_CFG_GPO(GPP_D10, 0, DEEP), // Strap 6 of 24
PAD_NC(GPP_D11, NONE),
PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // Strap 7 of 24
PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SATA_M2_PWR_EN2
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),
/* ------- GPIO Group GPP_E ------- */
PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
//_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPO(GPP_E6, 0, DEEP), // Strap 12 of 24
PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
PAD_CFG_GPO(GPP_E8, 0, DEEP), // SLP_DRAM#
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
PAD_NC(GPP_E10, NONE),
PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
PAD_CFG_GPO(GPP_E12, 0, DEEP), // TP_ATTN#
PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // PCH_EDP_HPD
PAD_NC(GPP_E15, NONE),
PAD_NC(GPP_E16, NONE),
PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID3
PAD_NC(GPP_E18, NATIVE), // TBT_LSX0_TXD
PAD_NC(GPP_E19, NATIVE), // TBT_LSX0_RXD
PAD_NC(GPP_E20, NONE),
PAD_CFG_GPO(GPP_E21, 0, DEEP), // Strap 14 of 24
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),
/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RF_RST#
//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), // XTAL_CLKREQ
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
//PAD_CFG_GPO(GPP_F8, 0, DEEP),
PAD_NC(GPP_F9, NONE),
PAD_CFG_GPO(GPP_F10, 1, DEEP), // CARD_RTD3_RST#
PAD_NC(GPP_F11, NONE),
PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN
PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH
PAD_NC(GPP_F14, NONE),
PAD_NC(GPP_F15, NONE),
PAD_CFG_GPI(GPP_F16, NONE, PLTRST), // GPU_EVENT#
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // LAN_CLKREQ#
PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_CPU_SSD1_RST#
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),
/* ------- GPIO Group GPP_H ------- */
PAD_CFG_GPO(GPP_H0, 1, DEEP), // M2_PCH_SSD_RST#
PAD_CFG_GPO(GPP_H1, 0, DEEP), // Strap 22 of 24
PAD_CFG_GPO(GPP_H2, 1, DEEP), // M2_WLAN_RST#
PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA
PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL
PAD_CFG_GPO(GPP_H8, 0, DEEP), // CNVI_MFUART2_RXD
PAD_CFG_GPO(GPP_H9, 0, DEEP), // CNVI_MFUART2_TXD
PAD_CFG_GPI(GPP_H10, NONE, DEEP), // UART0_RXD
PAD_CFG_GPI(GPP_H11, NONE, DEEP), // UART0_TXD
PAD_NC(GPP_H12, NONE),
PAD_CFG_GPI(GPP_H13, NONE, DEEP), // DEVSLP1
//PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
//PAD_NC(GPP_H16, NONE),
PAD_NC(GPP_H17, NONE),
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
PAD_NC(GPP_H19, NONE),
PAD_CFG_GPI(GPP_H20, NONE, DEEP), // BL_PWW_EN_EC
PAD_CFG_GPI(GPP_H21, NONE, DEEP), // PLVDD_RST_EC
PAD_CFG_GPO(GPP_H22, 0, DEEP), // MUX_CTRL_BIOS
//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), // CARD_CLKREQ#
/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
PAD_NC(GPP_R5, NONE),
PAD_CFG_GPO(GPP_R6, 0, DEEP), // DMIC_CLK1
PAD_CFG_GPO(GPP_R7, 0, DEEP), // DMIC_DATA1
/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),
/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),
};
void variant_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}

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src/mainboard/system76/gaze17/variants/3060/gpio_early.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <variant/gpio.h>
#include <soc/gpio.h>
static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH
};
void variant_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}

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src/mainboard/system76/gaze17/variants/3060/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek, ALC256 */
0x10ec0256, /* Vendor ID */
0x1558867c, /* Subsystem ID */
11, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x1558867c),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
AZALIA_PIN_CFG(0, 0x21, 0x02211020),
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/system76/gaze17/variants/3060/include/variant/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
void variant_configure_early_gpios(void);
void variant_configure_gpios(void);
#endif

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chip soc/intel/alderlake
device domain 0 on
subsystemid 0x1558 0x867c inherit
device ref igpu on
# DDIA is eDP
register "ddi_portA_config" = "1"
register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
end
device ref pcie4_0 on
# PCIe PEG0 x4, Clock 0 (SSD2)
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_src = 0,
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
# FIXME: Breaks suspend with WD drives
#chip soc/intel/common/block/pcie/rtd3
# # XXX: Enable tied to 3.3VS?
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
# register "srcclk_pin" = "0" # PEX4_SSD_CLKREQ#
# device generic 0 on end
#end
end
device ref tbt_pcie_rp0 on end
device ref tcss_dma0 on end
device ref xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Type-C
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 Type-A audio board
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Thunderbolt Type-C
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-A audio board
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side A
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Type-C side B
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 2 (WLAN)
register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 2,
.clk_req = 2,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "2" # WLAN_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp6 on
# PCIe root port #6 x1, Clock 5 (CARD)
register "pch_pcie_rp[PCH_RP(6)]" = "{
.clk_src = 5,
.clk_req = 5,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: No enable_gpio = no D3cold?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "srcclk_pin" = "5" # CARD_CLKREQ#
device generic 0 on end
end
end
device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 6 (GLAN)
# Clock source is shared with LAN and hence marked as free running.
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 6,
.clk_req = 6,
.flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED,
}"
register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
end
device ref pcie_rp9 on
# PCIe root port #9 x4, Clock 1 (SSD1)
register "pch_pcie_rp[PCH_RP(9)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
# XXX: Enable tied to 3.3VS?
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
register "disable_l23" = "true" # Fixes suspend on WD drives
register "srcclk_pin" = "1" # SSD_CLKREQ#
device generic 0 on end
end
end
device ref gbe on end
end
end