mb/google/brox: Create jubilant variant
Create the jubilant variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:348543712 TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_JUBILANT. Change-Id: Ic54437697058f8bce2167093bd88c0880d1b7cac Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83212 Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
This commit is contained in:
Ren Kuo
committed by
Karthik Ramasubramanian
Karthik Ramasubramanian
parent
7e75d1ad26
commit
ef4d562d2f
@@ -78,6 +78,12 @@ config BOARD_GOOGLE_GREENBAYUPOC
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select MEMORY_SODIMM
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config BOARD_GOOGLE_JUBILANT
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select BOARD_GOOGLE_BASEBOARD_BROX
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select CHROMEOS_WIFI_SAR if CHROMEOS
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select DRIVERS_GENERIC_ALC1015
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select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
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if BOARD_GOOGLE_BROX_COMMON
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config BASEBOARD_DIR
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@@ -128,13 +134,15 @@ config MAINBOARD_FAMILY
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config MAINBOARD_PART_NUMBER
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default "Brox_Ec_Ish" if BOARD_GOOGLE_BROX_EC_ISH
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default "Brox" if BOARD_GOOGLE_BROX
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default "Lotso" if BOARD_GOOGLE_LOTSO
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default "Greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
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default "Jubilant" if BOARD_GOOGLE_JUBILANT
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default "Lotso" if BOARD_GOOGLE_LOTSO
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config VARIANT_DIR
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default "brox" if BOARD_GOOGLE_BROX || BOARD_GOOGLE_BROX_EC_ISH
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default "lotso" if BOARD_GOOGLE_LOTSO
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default "greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC
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default "jubilant" if BOARD_GOOGLE_JUBILANT
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config VBOOT
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select VBOOT_LID_SWITCH
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@@ -13,3 +13,6 @@ config BOARD_GOOGLE_LOTSO
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config BOARD_GOOGLE_GREENBAYUPOC
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bool "-> Greenbayupoc"
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config BOARD_GOOGLE_JUBILANT
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bool "-> Jubilant"
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10
src/mainboard/google/brox/variants/jubilant/Makefile.mk
Normal file
10
src/mainboard/google/brox/variants/jubilant/Makefile.mk
Normal file
@@ -0,0 +1,10 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-$(CONFIG_FW_CONFIG) += variant.c
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ramstage-y += gpio.c
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ramstage-y += ramstage.c
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BIN
src/mainboard/google/brox/variants/jubilant/data.vbt
Normal file
BIN
src/mainboard/google/brox/variants/jubilant/data.vbt
Normal file
Binary file not shown.
186
src/mainboard/google/brox/variants/jubilant/gpio.c
Normal file
186
src/mainboard/google/brox/variants/jubilant/gpio.c
Normal file
@@ -0,0 +1,186 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> EN_FP_PWR (active high) */
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PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG),
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/* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> IPCH_FP_BOOT0 (active high) */
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PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
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/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */
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PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
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/* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> FP GSPI INT */
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PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> FP GSPI CLK */
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PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG),
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/* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL
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NF6: USB_C_GPP_F12] ==> FP GSPI DO */
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PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG),
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/* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA
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NF6: USB_C_GPP_F13] ==> SFP GSPI DI */
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PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
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/* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> FP GSPI CS */
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PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
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/* GPP_F14 : [NF1: GSXDIN NF3: THC1_SPI2_IO2 NF6: USB_C_GPP_F14] ==> PCH_TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_F14, 0, DEEP),
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/* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> PCH_I2C_MISC_R_SDA (SAR, HP) */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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/* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> PCH_I2C_MISC_R_SCL (SAR, HP) */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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/* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> HP_INT_L (Headphone interrupt) */
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PAD_CFG_GPI_INT(GPP_S6, NONE, PLTRST, EDGE_BOTH),
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/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> I2S_MCLK_R (headphone MCLK) */
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PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
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/* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> I2S0_SCLK */
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PAD_CFG_NF(GPP_R0, NONE, PLTRST, NF2),
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/* GPP_R1 : [NF1: HDA_SYNC NF3: DMIC_CLK_B1] ==> I2S0_SFRM */
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PAD_CFG_NF(GPP_R1, NONE, PLTRST, NF2),
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/* GPP_R2 : [NF1: HDA_SDO NF2: I2S0_TXD NF4: HDAPROC_SDO] ==> I2S0_TXD */
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PAD_CFG_NF(GPP_R2, NONE, PLTRST, NF2),
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/* GPP_R3 : [NF1: HDA_SDI0 NF2: I2S0_RXD NF4: HDAPROC_SDI] ==> I2S0_RXD */
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PAD_CFG_NF(GPP_R3, NONE, PLTRST, NF2),
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/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> SPK enable (active high) */
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PAD_CFG_GPO(GPP_F20, 1, DEEP),
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/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> SPK I2S_CLK */
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PAD_CFG_NF(GPP_S0, NONE, PLTRST, NF4),
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/* GPP_S1 : SNDW0_DATA/I2S1_SFRM ==> SPK I2S_FRAME */
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PAD_CFG_NF(GPP_S1, NONE, PLTRST, NF4),
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/* GPP_S2 : [NF1: SNDW1_CLK NF2: DMIC_CKL_A0 NF4: I2S1_TXD] ==> SPK I2S_TX */
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PAD_CFG_NF(GPP_S2, NONE, PLTRST, NF4),
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/* GPP_S3 : [NF1: SNDW1_DATA NF2: DMIC_DAGPP_D1TA0 NF4: I2S1_RXD] ==> SPK I2S_RX */
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PAD_CFG_NF(GPP_S3, NONE, PLTRST, NF4),
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/* GPP_R4 : HDA_RST_L/I2S2_SCLK/DMIC_CLK_A0 ==> DMIC_CLK_A0 */
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PAD_CFG_NF(GPP_R4, NONE, PLTRST, NF3),
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/* GPP_R5 : HDA_SDI1/I2S2_SFRM/DMIC_DATA0 ==> SDMIC_DATA0 */
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PAD_CFG_NF(GPP_R5, NONE, PLTRST, NF3),
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/* GPP_R6 : I2S2_TXD/DMIC_CLK_A1 ==> DMIC_CLK_A1 */
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PAD_CFG_NF(GPP_R6, NONE, PLTRST, NF3),
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/* GPP_R7 : I2S2_RXD/DMIC_DATA1 ==> DMIC_DATA1 */
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PAD_CFG_NF(GPP_R7, NONE, PLTRST, NF3),
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/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
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/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
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/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
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/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_E10, NONE, PLTRST),
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/* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_S7, NONE, DEEP),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/*
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* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
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* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
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* early on in bootblock, followed by enabling of power. Reset signal is deasserted
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* later on in ramstage. Since reset signal is asserted in bootblock, it results in
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* FPMCU not working after a S3 resume. This is a known issue.
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*/
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/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */
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PAD_CFG_GPO(GPP_D15, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */
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PAD_NC(GPP_D11, NONE),
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/* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG),
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/* GPP_E8 : GPP_E8 ==> PCH_WP_OD */
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PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG),
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/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_F9, 0, DEEP),
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/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
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/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
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/* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_S7, NONE, DEEP),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> FPMCU_RST_J_SUB_L (active low) */
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PAD_CFG_GPO(GPP_D15, 0, DEEP),
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/* D2 : ISH_GP2 ==> EN_FP_PWR */
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PAD_CFG_GPO(GPP_D2, 0, DEEP),
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/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
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/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
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/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
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/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_E10, NONE, PLTRST),
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/* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_S7, NONE, DEEP),
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/* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
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PAD_CFG_GPO(GPP_F7, 1, PLTRST),
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/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_F9, 1, DEEP),
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/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
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PAD_CFG_GPO(GPP_F17, 0, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
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};
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DECLARE_WEAK_CROS_GPIOS(cros_gpios);
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@@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/ec.h>
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#endif /* MAINBOARD_GPIO_H */
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@@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __MAINBOARD_GPIO_H__
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#define __MAINBOARD_GPIO_H__
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#include <baseboard/gpio.h>
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#define T1_OFF_MS 16
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#define T2_OFF_MS 2
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#define WWAN_FCPO GPP_F21
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#endif /* __MAINBOARD_GPIO_H__ */
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@@ -0,0 +1,133 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef MAINBOARD_HDA_VERB_H
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#define MAINBOARD_HDA_VERB_H
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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/* coreboot specific header */
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0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256
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0x10ec12ac, // Subsystem ID
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0x00000013, // Number of jacks (NID entries)
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AZALIA_RESET(0x1),
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/* NID 0x01, HDA Codec Subsystem ID Verb table */
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AZALIA_SUBVENDOR(0, 0x10ec12ac),
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/* Pin Widget Verb Table */
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/*
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* DMIC
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* Requirement is to use PCH DMIC. Hence,
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* commented out codec's Internal DMIC.
|
||||
* AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
|
||||
* AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||
*/
|
||||
|
||||
/* Pin widget 0x14 - Front (Port-D) */
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
/* Pin widget 0x18 - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
|
||||
/* Pin widget 0x19 - MIC2 (Port-F) */
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
|
||||
/* Pin widget 0x1A - LINE1 (Port-C) */
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
|
||||
/* Pin widget 0x1B - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
|
||||
/* Pin widget 0x1D - BEEP-IN */
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
|
||||
/* Pin widget 0x1E - NPC */
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
|
||||
/* Pin widget 0x21 - HP1-OUT (Port-I) */
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||
/*
|
||||
* Widget node 0x20 - 1
|
||||
* Codec hidden reset and speaker power 2W/4ohm
|
||||
*/
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x02050038,
|
||||
0x02047901,
|
||||
/*
|
||||
* Widget node 0x20 - 2
|
||||
* Class D power on Reset
|
||||
*/
|
||||
0x0205003C,
|
||||
0x02040354,
|
||||
0x0205003C,
|
||||
0x02040314,
|
||||
/*
|
||||
* Widget node 0x20 - 3
|
||||
* Disable AGC and set AGC limit to -1.5dB
|
||||
*/
|
||||
0x02050016,
|
||||
0x02040C50,
|
||||
0x02050012,
|
||||
0x0204EBC1,
|
||||
/*
|
||||
* Widget node 0x20 - 4
|
||||
* Set AGC Post gain +1.5dB then Enable AGC
|
||||
*/
|
||||
0x02050013,
|
||||
0x02044023,
|
||||
0x02050016,
|
||||
0x02040E50,
|
||||
/*
|
||||
* Widget node 0x20 - 5
|
||||
* Silence detector enabling + Set EAPD to verb control
|
||||
*/
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050010,
|
||||
0x02040020,
|
||||
/*
|
||||
* Widget node 0x20 - 6
|
||||
* Silence data mode Threshold (-90dB)
|
||||
*/
|
||||
0x02050030,
|
||||
0x0204A000,
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
/*
|
||||
* Widget node 0x20 - 7
|
||||
* Default setting - 1
|
||||
*/
|
||||
0x05750003,
|
||||
0x05740DA3,
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
/*
|
||||
* Widget node 0x20 - 8
|
||||
* support 1 pin detect two port
|
||||
*/
|
||||
0x02050009,
|
||||
0x0204E003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
/*
|
||||
* Widget node 0x20 - 9
|
||||
* To set LDO1/LDO2 as default (used for headset)
|
||||
*/
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
0x02050008,
|
||||
0x02046A0C,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
/* Dos beep path - 1 */
|
||||
0x01470C00,
|
||||
0x02050036,
|
||||
0x02047151,
|
||||
0x01470740,
|
||||
/* Dos beep path - 2 */
|
||||
0x0143b000,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
0x01470C02,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
||||
#endif
|
||||
109
src/mainboard/google/brox/variants/jubilant/memory.c
Normal file
109
src/mainboard/google/brox/variants/jubilant/memory.c
Normal file
@@ -0,0 +1,109 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/gpio.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg baseboard_memcfg = {
|
||||
.type = MEM_TYPE_LP5X,
|
||||
|
||||
.rcomp = {
|
||||
/* Baseboard uses only 100ohm Rcomp resistors */
|
||||
.resistor = 100,
|
||||
},
|
||||
|
||||
/* DQ byte map */
|
||||
.lpx_dq_map = {
|
||||
.ddr0 = {
|
||||
.dq0 = { 0, 3, 2, 1, 6, 4, 5, 7 },
|
||||
.dq1 = { 14, 12, 13, 15, 8, 11, 9, 10 },
|
||||
},
|
||||
.ddr1 = {
|
||||
.dq0 = { 1, 0, 2, 3, 6, 4, 7, 5 },
|
||||
.dq1 = { 11, 8, 10, 9, 15, 14, 13, 12 },
|
||||
},
|
||||
.ddr2 = {
|
||||
.dq0 = { 6, 4, 7, 5, 3, 1, 2, 0 },
|
||||
.dq1 = { 14, 12, 13, 15, 9, 10, 11, 8 },
|
||||
},
|
||||
.ddr3 = {
|
||||
.dq0 = { 1, 2, 3, 0, 6, 4, 7, 5 },
|
||||
.dq1 = { 13, 15, 12, 14, 8, 11, 10, 9 },
|
||||
},
|
||||
.ddr4 = {
|
||||
.dq0 = { 2, 3, 0, 1, 6, 5, 7, 4 },
|
||||
.dq1 = { 14, 15, 13, 12, 10, 8, 9, 11 },
|
||||
},
|
||||
.ddr5 = {
|
||||
.dq0 = { 1, 2, 3, 0, 6, 4, 7, 5 },
|
||||
.dq1 = { 15, 13, 12, 14, 10, 9, 8, 11 },
|
||||
},
|
||||
.ddr6 = {
|
||||
.dq0 = { 2, 1, 3, 0, 7, 5, 4, 6 },
|
||||
.dq1 = { 15, 13, 14, 12, 11, 9, 10, 8 },
|
||||
},
|
||||
.ddr7 = {
|
||||
.dq0 = { 3, 1, 2, 0, 5, 4, 7, 6 },
|
||||
.dq1 = { 14, 15, 9, 11, 13, 8, 10, 12 },
|
||||
},
|
||||
},
|
||||
|
||||
/* DQS CPU<>DRAM map */
|
||||
.lpx_dqs_map = {
|
||||
.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
|
||||
},
|
||||
|
||||
.lp5x_config = {
|
||||
.ccc_config = 0xff,
|
||||
},
|
||||
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
|
||||
.ect = 1, /* Early Command Training */
|
||||
|
||||
.UserBd = BOARD_TYPE_ULT_ULX,
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memory_params(void)
|
||||
{
|
||||
return &baseboard_memcfg;
|
||||
}
|
||||
|
||||
int variant_memory_sku(void)
|
||||
{
|
||||
/*
|
||||
* Memory configuration board straps
|
||||
* MEM_STRAP_0 GPP_E15
|
||||
* MEM_STRAP_1 GPP_E12
|
||||
* MEM_STRAP_2 GPP_E13
|
||||
* MEM_STRAP_3 GPP_E10
|
||||
*/
|
||||
gpio_t spd_gpios[] = {
|
||||
GPP_E15,
|
||||
GPP_E12,
|
||||
GPP_E13,
|
||||
GPP_E10,
|
||||
};
|
||||
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
||||
bool variant_is_half_populated(void)
|
||||
{
|
||||
/* MEM_CH_SEL GPP_S7 */
|
||||
return gpio_get(GPP_S7);
|
||||
}
|
||||
|
||||
void variant_get_spd_info(struct mem_spd *spd_info)
|
||||
{
|
||||
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
|
||||
spd_info->cbfs_index = variant_memory_sku();
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B
|
||||
SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = MT62F1G32D2DS-023 WT:B
|
||||
@@ -0,0 +1,10 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
MT62F512M32D2DR-031 WT:B 0 (0000)
|
||||
H9JCNNNBK3MLYR-N6E 0 (0000)
|
||||
MT62F1G32D4DR-031 WT:B 1 (0001)
|
||||
MT62F1G32D2DS-023 WT:B 2 (0010)
|
||||
@@ -0,0 +1,4 @@
|
||||
MT62F512M32D2DR-031 WT:B
|
||||
H9JCNNNBK3MLYR-N6E
|
||||
MT62F1G32D4DR-031 WT:B
|
||||
MT62F1G32D2DS-023 WT:B
|
||||
434
src/mainboard/google/brox/variants/jubilant/overridetree.cb
Normal file
434
src/mainboard/google/brox/variants/jubilant/overridetree.cb
Normal file
@@ -0,0 +1,434 @@
|
||||
fw_config
|
||||
field STORAGE 2 3
|
||||
option STORAGE_UNKNOWN 0
|
||||
option STORAGE_UFS 1
|
||||
option STORAGE_NVME 2
|
||||
end
|
||||
field WIFI_BT 4 4
|
||||
option WIFI_BT_CNVI 0
|
||||
option WIFI_BT_PCIE 1
|
||||
end
|
||||
field DB_USB 11 12
|
||||
option DB_1A 0
|
||||
option DB_1A_LTE 1
|
||||
end
|
||||
field FPMCU 17 18
|
||||
option FPMCU_ABSENT 0
|
||||
option FPMCU_NUVOTON 1
|
||||
end
|
||||
end
|
||||
|
||||
chip soc/intel/alderlake
|
||||
register "platform_pmax" = "208"
|
||||
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
|
||||
register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port
|
||||
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # WWAN
|
||||
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC2)" # Type-A Port A0
|
||||
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC1)" # Type-A Port A1
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
|
||||
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A1(DB)
|
||||
register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3 Port
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type A port A0(DCI)
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN
|
||||
|
||||
device domain 0 on
|
||||
device ref dtt on
|
||||
chip drivers/intel/dptf
|
||||
## sensor information
|
||||
register "options.tsr[0].desc" = ""DRAM_SOC""
|
||||
register "options.tsr[1].desc" = ""Fan-Inlet""
|
||||
|
||||
## Active Policy
|
||||
register "policies.active" = "{
|
||||
[0] = {
|
||||
.target = DPTF_CPU,
|
||||
.thresholds = {
|
||||
TEMP_PCT(95, 90),
|
||||
TEMP_PCT(92, 80),
|
||||
TEMP_PCT(89, 60),
|
||||
TEMP_PCT(85, 40),
|
||||
TEMP_PCT(80, 30),
|
||||
}
|
||||
},
|
||||
[1] = {
|
||||
.target = DPTF_TEMP_SENSOR_0,
|
||||
.thresholds = {
|
||||
TEMP_PCT(54, 95),
|
||||
TEMP_PCT(52, 90),
|
||||
TEMP_PCT(50, 80),
|
||||
TEMP_PCT(48, 50),
|
||||
TEMP_PCT(46, 30),
|
||||
TEMP_PCT(44, 25),
|
||||
TEMP_PCT(42, 20),
|
||||
TEMP_PCT(40, 15),
|
||||
}
|
||||
},
|
||||
[2] = {
|
||||
.target = DPTF_TEMP_SENSOR_1,
|
||||
.thresholds = {
|
||||
TEMP_PCT(54, 95),
|
||||
TEMP_PCT(52, 90),
|
||||
TEMP_PCT(50, 80),
|
||||
TEMP_PCT(48, 50),
|
||||
TEMP_PCT(46, 30),
|
||||
TEMP_PCT(44, 25),
|
||||
TEMP_PCT(42, 20),
|
||||
TEMP_PCT(40, 15),
|
||||
}
|
||||
}
|
||||
}"
|
||||
|
||||
## Passive Policy
|
||||
register "policies.passive" = "{
|
||||
[0] = DPTF_PASSIVE(CPU, CPU, 97, 5000),
|
||||
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000),
|
||||
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000),
|
||||
}"
|
||||
|
||||
## Critical Policy
|
||||
register "policies.critical" = "{
|
||||
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
|
||||
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
|
||||
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
|
||||
}"
|
||||
|
||||
register "controls.power_limits" = "{
|
||||
.pl1 = {
|
||||
.min_power = 15000,
|
||||
.max_power = 15000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 200,
|
||||
},
|
||||
.pl2 = {
|
||||
.min_power = 55000,
|
||||
.max_power = 55000,
|
||||
.time_window_min = 28 * MSECS_PER_SEC,
|
||||
.time_window_max = 32 * MSECS_PER_SEC,
|
||||
.granularity = 1000,
|
||||
}
|
||||
}"
|
||||
|
||||
## Charger Performance Control (Control, mA)
|
||||
register "controls.charger_perf" = "{
|
||||
[0] = { 255, 1700 },
|
||||
[1] = { 24, 1500 },
|
||||
[2] = { 16, 1000 },
|
||||
[3] = { 8, 500 }
|
||||
}"
|
||||
|
||||
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||
register "controls.fan_perf" = "{
|
||||
[0] = { 90, 6700, 220, 2200, },
|
||||
[1] = { 80, 5800, 180, 1800, },
|
||||
[2] = { 70, 5000, 145, 1450, },
|
||||
[3] = { 60, 4900, 115, 1150, },
|
||||
[4] = { 50, 3838, 90, 900, },
|
||||
[5] = { 40, 2904, 55, 550, },
|
||||
[6] = { 30, 2337, 30, 300, },
|
||||
[7] = { 20, 1608, 15, 150, },
|
||||
[8] = { 10, 800, 10, 100, },
|
||||
[9] = { 0, 0, 0, 50, }
|
||||
}"
|
||||
|
||||
## Fan options
|
||||
register "options.fan.fine_grained_control" = "1"
|
||||
register "options.fan.step_size" = "2"
|
||||
|
||||
device generic 0 alias dptf_policy on end
|
||||
end
|
||||
end # DTT
|
||||
device ref igpu on
|
||||
chip drivers/gfx/generic
|
||||
register "device_count" = "6"
|
||||
# DDIA for eDP
|
||||
register "device[0].name" = ""LCD0""
|
||||
register "device[0].type" = "panel"
|
||||
# DDIB for HDMI
|
||||
# If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB
|
||||
register "device[1].name" = ""DD01""
|
||||
# TCP0 (DP-1) for port C0
|
||||
register "device[2].name" = ""DD02""
|
||||
register "device[2].use_pld" = "true"
|
||||
register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
# TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1
|
||||
register "device[3].name" = ""DD03""
|
||||
# TCP2 (DP-3) for port C2
|
||||
register "device[4].name" = ""DD04""
|
||||
register "device[4].use_pld" = "true"
|
||||
register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
# TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3
|
||||
register "device[5].name" = ""DD05""
|
||||
device generic 0 on end
|
||||
end
|
||||
end # Integrated Graphics Device
|
||||
device ref pch_espi on
|
||||
chip ec/google/chromeec
|
||||
device pnp 0c09.0 on end
|
||||
end
|
||||
end
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port1 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 on end
|
||||
end
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
use usb2_port3 as usb2_port
|
||||
use tcss_usb3_port3 as usb3_port
|
||||
device generic 1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C2 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref tcss_usb3_port3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C2 (MLB)""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port4 on
|
||||
probe DB_USB DB_1A_LTE
|
||||
end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "has_power_resource" = "1"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0 (DCI)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb2_port9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
register "has_power_resource" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1 (DB)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0 (DCI)""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "use_custom_pld" = "true"
|
||||
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 WWAN""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb3_port4 on
|
||||
probe DB_USB DB_1A_LTE
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref pcie4_0 on
|
||||
# Enable CPU PCIE RP 1 using CLK 3
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_req = 3,
|
||||
.clk_src = 3,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
probe STORAGE STORAGE_NVME
|
||||
end
|
||||
device ref pcie_rp5 on
|
||||
register "pch_pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 1,
|
||||
.clk_req = 1,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_DW0_03"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device pci 00.0 on
|
||||
probe WIFI_BT WIFI_BT_PCIE
|
||||
end
|
||||
end
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)"
|
||||
register "srcclk_pin" = "1"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI_BT WIFI_BT_PCIE
|
||||
end
|
||||
device ref cnvi_wifi on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_PME_B0"
|
||||
register "add_acpi_dma_property" = "true"
|
||||
register "enable_cnvi_ddr_rfim" = "true"
|
||||
device generic 0 on end
|
||||
end
|
||||
probe WIFI_BT WIFI_BT_CNVI
|
||||
end
|
||||
device ref ish on
|
||||
chip drivers/intel/ish
|
||||
register "add_acpi_dma_property" = "true"
|
||||
device generic 0 alias ish_conf on end
|
||||
end
|
||||
probe STORAGE STORAGE_UFS
|
||||
end
|
||||
device ref ufs on
|
||||
probe STORAGE STORAGE_UFS
|
||||
end
|
||||
device ref i2c0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""ELAN0000""
|
||||
register "desc" = ""ELAN Touchpad""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)"
|
||||
register "wake" = "GPE0_DW2_03"
|
||||
register "detect" = "1"
|
||||
device i2c 0x15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""SYNA0000""
|
||||
register "generic.cid" = ""ACPI0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)"
|
||||
register "generic.wake" = "GPE0_DW2_03"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 0x2c on end
|
||||
end
|
||||
end #I2C0
|
||||
device ref i2c1 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ILTK0001""
|
||||
register "generic.desc" = ""ILITEK Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
|
||||
register "generic.detect" = "1"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
|
||||
register "generic.reset_delay_ms" = "200"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
|
||||
register "generic.enable_delay_ms" = "12"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 41 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN9004""
|
||||
register "generic.desc" = ""ELAN Touchscreen""
|
||||
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)"
|
||||
register "generic.detect" = "1"
|
||||
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)"
|
||||
register "generic.reset_delay_ms" = "20"
|
||||
register "generic.reset_off_delay_ms" = "2"
|
||||
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)"
|
||||
register "generic.enable_delay_ms" = "1"
|
||||
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F14)"
|
||||
register "generic.stop_delay_ms" = "150"
|
||||
register "generic.stop_off_delay_ms" = "2"
|
||||
register "generic.has_power_resource" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 10 on end
|
||||
end
|
||||
end
|
||||
device ref i2c2 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Headset Codec""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_S6)"
|
||||
# Set the jd_src to RT5668_JD1 for jack detection
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
chip drivers/generic/alc1015
|
||||
register "hid" = ""RTL1019""
|
||||
register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F20)"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref gspi1 on
|
||||
chip drivers/spi/acpi
|
||||
register "name" = ""CRFP""
|
||||
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||
register "uid" = "1"
|
||||
register "compat_string" = ""google,cros-ec-spi""
|
||||
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
|
||||
register "wake" = "GPE0_DW2_15"
|
||||
register "has_power_resource" = "1"
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
|
||||
register "enable_delay_ms" = "3"
|
||||
device spi 0 on
|
||||
probe FPMCU FPMCU_NUVOTON
|
||||
end
|
||||
end # FPMCU
|
||||
end
|
||||
device ref hda on
|
||||
chip drivers/sof
|
||||
register "spkr_tplg" = "rt1019"
|
||||
register "jack_tplg" = "rt5682"
|
||||
register "mic_tplg" = "_2ch_pdm0"
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
54
src/mainboard/google/brox/variants/jubilant/ramstage.c
Normal file
54
src/mainboard/google/brox/variants/jubilant/ramstage.c
Normal file
@@ -0,0 +1,54 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <ec/google/chromeec/ec.h>
|
||||
#include <intelblocks/power_limit.h>
|
||||
|
||||
/*
|
||||
* SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts),
|
||||
* pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts)
|
||||
* Following values are for performance config as per document #640982
|
||||
*/
|
||||
|
||||
const struct cpu_power_limits performance_efficient_limits[] = {
|
||||
{
|
||||
.mchid = PCI_DID_INTEL_RPL_P_ID_3,
|
||||
.cpu_tdp = 15,
|
||||
.pl1_min_power = 6000,
|
||||
.pl1_max_power = 15000,
|
||||
.pl2_min_power = 55000,
|
||||
.pl2_max_power = 55000,
|
||||
.pl4_power = 114000
|
||||
},
|
||||
{
|
||||
.mchid = PCI_DID_INTEL_RPL_P_ID_4,
|
||||
.cpu_tdp = 15,
|
||||
.pl1_min_power = 6000,
|
||||
.pl1_max_power = 15000,
|
||||
.pl2_min_power = 55000,
|
||||
.pl2_max_power = 55000,
|
||||
.pl4_power = 114000
|
||||
},
|
||||
};
|
||||
|
||||
const struct system_power_limits sys_limits[] = {
|
||||
/* SKU_ID, TDP (Watts), psys_pl2 (Watts) */
|
||||
{ PCI_DID_INTEL_RPL_P_ID_3, 15, 60 },
|
||||
{ PCI_DID_INTEL_RPL_P_ID_4, 15, 60 },
|
||||
};
|
||||
|
||||
const struct psys_config psys_config = {
|
||||
.efficiency = 86,
|
||||
};
|
||||
|
||||
void __weak variant_devtree_update(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
|
||||
|
||||
const struct cpu_power_limits *limits = performance_efficient_limits;
|
||||
size_t limits_size = ARRAY_SIZE(performance_efficient_limits);
|
||||
|
||||
variant_update_power_limits(limits, limits_size);
|
||||
variant_update_psys_power_limits(limits, sys_limits, limits_size, &psys_config);
|
||||
}
|
||||
20
src/mainboard/google/brox/variants/jubilant/variant.c
Normal file
20
src/mainboard/google/brox/variants/jubilant/variant.c
Normal file
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <baseboard/variants.h>
|
||||
#include <chip.h>
|
||||
#include <fw_config.h>
|
||||
#include <sar.h>
|
||||
|
||||
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
|
||||
{
|
||||
if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI))) {
|
||||
printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n");
|
||||
config->cnvi_bt_core = true;
|
||||
}
|
||||
}
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT));
|
||||
}
|
||||
Reference in New Issue
Block a user