sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/system76: Fix left USB3 port on gaze14/gaze15

Browse Source 
The USB table in the manuals incorrectly list the USB3 port as 5.
The labeled pins show it correctly as port 2.

Change-Id: I9a6a96af847ca66ad667738d83cfca7c3166956a
This commit is contained in:
Tim Crawford
2020-08-12 11:27:04 -06:00
committed by Jeremy Soller
parent 011439cb91
commit efe04c82e0
2 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/system76/gaze14/devicetree.cb
View File

@@ -99,10 +99,10 @@ chip soc/intel/cannonlake
# USB2 # USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
@@ -117,10 +117,10 @@ chip soc/intel/cannonlake
# USB3 # USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
register "usb3_ports[1]" = "USB3_PORT_EMPTY" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left register "usb3_ports[4]" = "USB3_PORT_EMPTY"
register "usb3_ports[5]" = "USB3_PORT_EMPTY" register "usb3_ports[5]" = "USB3_PORT_EMPTY"
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
register "usb3_ports[7]" = "USB3_PORT_EMPTY" register "usb3_ports[7]" = "USB3_PORT_EMPTY"

8
src/mainboard/system76/gaze15/devicetree.cb
View File

@@ -99,10 +99,10 @@ chip soc/intel/cannonlake
# USB2 # USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right
register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
@@ -117,10 +117,10 @@ chip soc/intel/cannonlake
# USB3 # USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right
register "usb3_ports[1]" = "USB3_PORT_EMPTY" register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left register "usb3_ports[4]" = "USB3_PORT_EMPTY"
register "usb3_ports[5]" = "USB3_PORT_EMPTY" register "usb3_ports[5]" = "USB3_PORT_EMPTY"
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
register "usb3_ports[7]" = "USB3_PORT_EMPTY" register "usb3_ports[7]" = "USB3_PORT_EMPTY"