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soc/amd/*/Makefile: use all_x86 target

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Use the newly introduced 'all_x86' make target to add the compilation
unit to all stages that run on the x86 cores, but not to verstage on
PSP.

TEST=Timeless builds for Mandolin without verstage on PSP and Guybrush
with verstage on PSP result in identical images with and without this
patch applied.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94de6de5a4c7723065a4eb1b7149f9933ef134a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74151
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Felix Held
2023-04-01 01:31:24 +02:00
parent 0d20e3c720
commit f008e0af16
12 changed files with 32 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/amd/cezanne/Makefile.inc
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@@ -9,18 +9,15 @@ all-y += aoac.c
all-y += config.c
all-y += i2c.c
# all_x86-y adds the compilation unit to all stages that run on the x86 cores
all_x86-y += gpio.c
all_x86-y += uart.c
bootblock-y += early_fch.c
bootblock-y += espi_util.c
bootblock-y += gpio.c
bootblock-y += uart.c
verstage_x86-y += gpio.c
verstage_x86-y += uart.c
romstage-y += fsp_m_params.c
romstage-y += gpio.c
romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
@@ -28,11 +25,9 @@ ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += root_complex.c
ramstage-y += uart.c
ramstage-y += xhci.c
smm-y += gpio.c

6
src/soc/amd/common/block/acpi/Makefile.inc
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@@ -1,11 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI),y)
bootblock-y += acpi.c
verstage_x86-y += acpi.c
romstage-y += acpi.c
ramstage-y += acpi.c
postcar-y += acpi.c
all_x86-y += acpi.c
smm-y += acpi.c
ramstage-y += pm_state.c

6
src/soc/amd/common/block/alink/Makefile.inc
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@@ -1,11 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),y)
bootblock-y += alink.c
verstage_x86-y += alink.c
romstage-y += alink.c
postcar-y += alink.c
ramstage-y += alink.c
all_x86-y += alink.c
smm-y += alink.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_ALINK

23
src/soc/amd/common/block/cpu/tsc/Makefile.inc
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@@ -1,24 +1,9 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c
all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_TSC) += tsc_freq.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM15H_16H) += cpufreq_15_16.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c

11
src/soc/amd/common/block/lpc/Makefile.inc
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@@ -3,20 +3,13 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC),y)
ramstage-y += lpc.c
bootblock-y += lpc_util.c
verstage_x86-y += lpc_util.c
romstage-y += lpc_util.c
postcar-y += lpc_util.c
ramstage-y += lpc_util.c
all_x86-y += lpc_util.c
smm-y += lpc_util.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
bootblock-y += spi_dma.c
verstage_x86-y += spi_dma.c
romstage-y += spi_dma.c
ramstage-y += spi_dma.c
all_x86-y += spi_dma.c
smm-y += spi_dma.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA

6
src/soc/amd/common/block/pci/Makefile.inc
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@@ -11,10 +11,6 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF),y)
bootblock-y += amd_pci_mmconf.c
verstage_x86-y += amd_pci_mmconf.c
romstage-y += amd_pci_mmconf.c
postcar-y += amd_pci_mmconf.c
ramstage-y += amd_pci_mmconf.c
all_x86-y += amd_pci_mmconf.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF

8
src/soc/amd/common/block/pm/Makefile.inc
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@@ -1,13 +1,9 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
all_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c

7
src/soc/amd/common/block/uart/Makefile.inc
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@@ -1,12 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_UART),y)
# all-y can't be used, since verstage on PSP has a different implementation
bootblock-y += uart.c
verstage_x86-y += uart.c
romstage-y += uart.c
postcar-y += uart.c
ramstage-y += uart.c
all_x86-y += uart.c
smm-$(CONFIG_DEBUG_SMI) += uart.c
all-$(CONFIG_AMD_SOC_CONSOLE_UART) += uart_console.c

12
src/soc/amd/glinda/Makefile.inc
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@@ -12,19 +12,17 @@ all-y += aoac.c
all-y += config.c
all-y += i2c.c
# all_x86-y adds the compilation unit to all stages that run on the x86 cores
all_x86-y += gpio.c
all_x86-y += uart.c
bootblock-y += early_fch.c
bootblock-y += espi_util.c
bootblock-y += gpio.c
bootblock-y += uart.c
verstage-y += espi_util.c
verstage_x86-y += gpio.c
verstage_x86-y += uart.c
romstage-y += fsp_m_params.c
romstage-y += gpio.c
romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
@@ -32,10 +30,8 @@ ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += gpio.c
ramstage-y += mca.c
ramstage-y += root_complex.c
ramstage-y += uart.c
ramstage-y += xhci.c
smm-y += gpio.c

12
src/soc/amd/mendocino/Makefile.inc
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@@ -9,19 +9,17 @@ all-y += aoac.c
all-y += config.c
all-y += i2c.c
# all_x86-y adds the compilation unit to all stages that run on the x86 cores
all_x86-y += gpio.c
all_x86-y += uart.c
bootblock-y += early_fch.c
bootblock-y += espi_util.c
bootblock-y += gpio.c
bootblock-y += uart.c
verstage-y += espi_util.c
verstage_x86-y += gpio.c
verstage_x86-y += uart.c
romstage-y += fsp_m_params.c
romstage-y += gpio.c
romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
@@ -30,10 +28,8 @@ ramstage-y += cpu.c
ramstage-y += fch.c
ramstage-y += fsp_misc_data_hob.c
ramstage-y += fsp_s_params.c
ramstage-y += gpio.c
ramstage-y += mca.c
ramstage-y += root_complex.c
ramstage-y += uart.c
ramstage-y += xhci.c
smm-y += gpio.c

12
src/soc/amd/phoenix/Makefile.inc
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@@ -12,20 +12,18 @@ all-y += aoac.c
all-y += config.c
all-y += i2c.c
# all_x86-y adds the compilation unit to all stages that run on the x86 cores
all_x86-y += gpio.c
all_x86-y += uart.c
bootblock-y += early_fch.c
bootblock-y += espi_util.c
bootblock-y += gpio.c
bootblock-y += uart.c
verstage-y += espi_util.c
verstage_x86-y += gpio.c
verstage_x86-y += uart.c
romstage-y += fsp_m_params.c
romstage-y += gpio.c
romstage-y += romstage.c
romstage-y += soc_util.c
romstage-y += uart.c
ramstage-y += acpi.c
ramstage-y += agesa_acpi.c
@@ -33,12 +31,10 @@ ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += root_complex.c
ramstage-y += soc_util.c
ramstage-y += uart.c
ramstage-y += xhci.c
smm-y += gpio.c

13
src/soc/amd/picasso/Makefile.inc
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@@ -10,17 +10,14 @@ all-y += aoac.c
all-y += config.c
all-y += i2c.c
# all_x86-y adds the compilation unit to all stages that run on the x86 cores
all_x86-y += gpio.c
all_x86-y += uart.c
bootblock-y += early_fch.c
bootblock-y += gpio.c
bootblock-y += uart.c
romstage-y += fsp_m_params.c
romstage-y += gpio.c
romstage-y += romstage.c
romstage-y += uart.c
verstage_x86-y += gpio.c
verstage_x86-y += uart.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c
@@ -28,14 +25,12 @@ ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += fch.c
ramstage-y += fsp_s_params.c
ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += mca.c
ramstage-y += pcie_gpp.c
ramstage-y += root_complex.c
ramstage-y += sata.c
ramstage-y += soc_util.c
ramstage-y += uart.c
ramstage-y += xhci.c
smm-y += smihandler.c