mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543 Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SOC_INTEL_ALDERLAKE
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select HAVE_SPD_IN_CBFS
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select DRIVERS_SOUNDWIRE_ALC711
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select PCIEXP_HOTPLUG
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config CHROMEOS
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bool
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@@ -77,6 +78,18 @@ config ADL_INTEL_EC
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select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
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endchoice
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config PCIEXP_HOTPLUG_BUSES
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int
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default 42
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config PCIEXP_HOTPLUG_MEM
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hex
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default 0xc200000 # 194 MiB
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config PCIEXP_HOTPLUG_PREFETCH_MEM
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hex
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default 0x1c000000 # 448 MiB
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config VBOOT
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select VBOOT_LID_SWITCH
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select VBOOT_MOCK_SECDATA
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