Merge remote-tracking branch 'upstream/master' into system76

2020-05-09 12:56:34 -06:00
parent 0f11811ab7 29fbfcc472
commit f208e51e57
8610 changed files with 89314 additions and 139502 deletions
--- a/src/mainboard/51nb/Kconfig
+++ b/src/mainboard/51nb/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This file is part of the coreboot project.
+
+if VENDOR_51NB
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/51nb/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/51nb/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string "Mainboard Vendor"
+	default "51NB"
+
+endif # VENDOR_51NB
--- a/src/mainboard/51nb/Kconfig.name
+++ b/src/mainboard/51nb/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_51NB
+	bool "51NB"
--- a/src/mainboard/51nb/x210/Kconfig
+++ b/src/mainboard/51nb/x210/Kconfig
@@ -0,0 +1,54 @@
+if BOARD_51NB_X210
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select EC_51NB_NPCE985LA0DX
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_LIBGFXINIT
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SOC_INTEL_KABYLAKE
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+
+config MAINBOARD_FAMILY
+	string
+	default "X210"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "X210"
+
+config MAINBOARD_VERSION
+	string
+	default "1.0"
+
+config MAINBOARD_DIR
+	string
+	default "51nb/x210"
+
+config MAX_CPUS
+	int
+	default 8
+
+config VGA_BIOS_ID
+	string
+	default "8086,5917"
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config FMDFILE
+	string
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config NO_POST
+	default y
+
+endif
--- a/src/mainboard/51nb/x210/Kconfig.name
+++ b/src/mainboard/51nb/x210/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_51NB_X210
+	bool "51NB X210"
--- a/src/mainboard/51nb/x210/Makefile.inc
+++ b/src/mainboard/51nb/x210/Makefile.inc
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This file is part of the coreboot project.
+
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
--- a/src/mainboard/51nb/x210/acpi/battery.asl
+++ b/src/mainboard/51nb/x210/acpi/battery.asl
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Device (BAT)
+{
+	Name (_HID, EisaId ("PNP0C0A"))
+	Name (_UID, 1)
+	Name (_PCL, Package () { \_SB })
+
+	Method (_STA, 0, NotSerialized)  // _STA: Status
+	{
+		If (B1SS)
+		{
+			Return (0x1F)
+		}
+		Else
+		{
+			Return (0x0F)
+		}
+	}
+
+	Name (PBIF, Package () {
+		0x00000001,  /* 0x00: Power Unit: mAH */
+		0xFFFFFFFF,  /* 0x01: Design Capacity */
+		0xFFFFFFFF,  /* 0x02: Last Full Charge Capacity */
+		0x00000001,  /* 0x03: Battery Technology: Rechargeable */
+		0xFFFFFFFF,  /* 0x04: Design Voltage */
+		0x00000000,  /* 0x05: Design Capacity of Warning */
+		0xFFFFFFFF,  /* 0x06: Design Capacity of Low */
+		0x00000001,  /* 0x07: Capacity Granularity 1 */
+		0x00000001,  /* 0x08: Capacity Granularity 2 */
+		"Y91",       /* 0x09: Model Number */
+		"",          /* 0x0a: Serial Number */
+		"LION",      /* 0x0b: Battery Type */
+		"CJOYIN"     /* 0x0c: OEM Information */
+	})
+
+	Method (_BIF, 0, Serialized)
+	{
+		/* Design Capacity */
+		Store (DGCP * 10000 / DGVO, Index (PBIF, 1))
+
+		/* Last Full Charge Capacity */
+		Store (FLCP * 10000 / DGVO, Index (PBIF, 2))
+
+		/* Design Voltage */
+		Store (DGVO, Index (PBIF, 4))
+
+		/* Design Capacity of Warning */
+		Store (BDW * 10000 / DGVO, Index (PBIF, 5))
+
+		/* Design Capacity of Low */
+		Store (BDL, Index (PBIF, 6))
+
+		Return (PBIF)
+	}
+
+	Name (PBST, Package () {
+		0x00000000,  /* 0x00: Battery State */
+		0xFFFFFFFF,  /* 0x01: Battery Present Rate */
+		0xFFFFFFFF,  /* 0x02: Battery Remaining Capacity */
+		0xFFFFFFFF,  /* 0x03: Battery Present Voltage */
+	})
+
+	Method (_BST, 0, NotSerialized)  // _BST: Battery Status
+	{
+		/*
+		* 0: BATTERY STATE
+		*
+		* bit 0 = discharging
+		* bit 1 = charging
+		* bit 2 = critical level
+		*/
+		Store (BSTS, Index (PBST, 0))
+
+		/*
+		* 1: BATTERY PRESENT RATE
+		*/
+		Store (BPR, Index (PBST, 1))
+
+		/*
+		* 2: BATTERY REMAINING CAPACITY
+		*/
+		Store (BRC * 10000 / DGVO, Index (PBST, 2))
+
+		/*
+		* 3: BATTERY PRESENT VOLTAGE
+		*/
+		Store (BPV, Index (PBST, 3))
+
+		Return (PBST)
+	}
+}
--- a/src/mainboard/51nb/x210/acpi/ec.asl
+++ b/src/mainboard/51nb/x210/acpi/ec.asl
@@ -0,0 +1,115 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Device (EC)
+{
+	Name (_HID, EisaId ("PNP0C09"))
+	Name (_UID, 0)
+
+	Name (_GPE, 0x4F)  // _GPE: General Purpose Events
+	Name (_CRS, ResourceTemplate () {
+		IO (Decode16, 0x62, 0x62, 1, 1)
+		IO (Decode16, 0x66, 0x66, 1, 1)
+	})
+
+	OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x50),
+		CTMP,   8,
+		CFAN,   8,
+		B1SS,   1,
+		BSTS,   2,
+		ACIN,   1,
+		Offset (0x53),
+		BKLG,   8,
+		TOUP,   1,
+		WIRE,   1,
+		BLTH,   1,
+		LIDC,   1,
+		APFG,   1,
+		WRST,   1,
+		BTST,   1,
+		ACEB,   1,
+		CAME,   1,
+		Offset (0x60),
+		DGCP,   16,
+		FLCP,   16,
+		DGVO,   16,
+		BDW,    16,
+		BDL,    16,
+		BPR,    16,
+		BRC,    16,
+		BPV,    16
+	}
+
+	Method (_REG, 2, NotSerialized)
+	{
+		/* Initialize AC power state */
+		Store (ACIN, \PWRS)
+
+		/* Initialize LID switch state */
+		Store (LIDC, \LIDS)
+	}
+
+	/* KEY_BRIGHTNESSUP */
+	Method (_Q04)
+	{
+		Notify(\_SB.PCI0.GFX0.LCD, 0x86)
+	}
+
+	/* KEY_BRIGHTNESSDOWN */
+	Method (_Q05)
+	{
+		Notify(\_SB.PCI0.GFX0.LCD, 0x87)
+	}
+
+	/* Battery Information Event */
+	Method (_Q0C)
+	{
+		Notify (BAT, 0x81)
+	}
+
+	/* AC event */
+	Method (_Q0D)
+	{
+		Store (ACIN, \PWRS)
+		Notify (AC, 0x80)
+	}
+
+	/* Lid event */
+	Method (_Q0E)
+	{
+		Store (LIDC, \LIDS)
+		Notify (LID0, 0x80)
+	}
+
+	/* Battery Information Event */
+	Method (_Q13)
+	{
+		Notify (BAT, 0x81)
+	}
+
+	/* Battery Status Event */
+	Method (_Q14)
+	{
+		Notify (BAT, 0x80)
+	}
+
+	Device (AC)
+	{
+		Name (_HID, "ACPI0003")
+		Name (_PCL, Package () { \_SB })
+
+		Method (_STA)
+		{
+			Return (0x0F)
+		}
+		Method (_PSR)
+		{
+			Return (\PWRS)
+		}
+	}
+
+	#include "battery.asl"
+}
--- a/src/mainboard/51nb/x210/acpi/graphics.asl
+++ b/src/mainboard/51nb/x210/acpi/graphics.asl
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+	Method (_DOS, 1, NotSerialized)
+	{
+		/* We never do anything in firmware, so _DOS is a noop */
+	}
+	Method (_DOD, 0, NotSerialized)
+	{
+		return (Package (0x03)
+		{
+			0x80000410, /* LCD */
+			0x80000120, /* VGA */
+			0x80000330 /* DP */
+		})
+	}
+	Device (LCD)
+	{
+		Method (_ADR, 0, Serialized)
+		{
+			Return (0x800000410)
+		}
+
+		Method (_BCL, 0, NotSerialized)
+		{
+			Return (Package (0x12)
+			{
+				0x0A,
+				0x0F,
+				0x00,
+				0x01,
+				0x02,
+				0x03,
+				0x04,
+				0x05,
+				0x06,
+				0x07,
+				0x08,
+				0x09,
+				0x0A,
+				0x0B,
+				0x0C,
+				0x0D,
+				0x0E,
+				0x0F
+			})
+		}
+		Method (_BCM, 1, NotSerialized)
+		{
+			\_SB.PCI0.LPCB.EC.BKLG = Arg0
+		}
+		Method (_BQC, 0, NotSerialized)
+		{
+			Return (\_SB.PCI0.LPCB.EC.BKLG)
+		}
+	}
+}
--- a/src/mainboard/51nb/x210/acpi/mainboard.asl
+++ b/src/mainboard/51nb/x210/acpi/mainboard.asl
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId ("PNP0C0D"))
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+
+		Method (_LID)
+		{
+			Return (\LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+
+		Name (_PRW, Package () { 27, 4 })
+	}
+
+	Device (SLPB)
+	{
+		Name (_HID, EisaId ("PNP0C0E"))
+
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
--- a/src/mainboard/51nb/x210/acpi/platform.asl
+++ b/src/mainboard/51nb/x210/acpi/platform.asl
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+
+/*
+ * The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method (_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice. */
+	Store (Arg0, PICM)
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Store(\_SB.PCI0.LPCB.EC.LIDC, \LIDS)
+	Store(\_SB.PCI0.LPCB.EC.ACIN, \PWRS)
+	Return (Package (){ 0, 0 })
+}
--- a/src/mainboard/51nb/x210/acpi/superio.asl
+++ b/src/mainboard/51nb/x210/acpi/superio.asl
@@ -0,0 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
--- a/src/mainboard/51nb/x210/board.fmd
+++ b/src/mainboard/51nb/x210/board.fmd
@@ -0,0 +1,15 @@
+#
+# Manually defined FMD in order to ensure that space is reserved for the EC
+# at the base of the BIOS region.
+#
+
+FLASH 8M {
+	BIOS@0x200000 0x600000 {
+		EC@0x0 0x10000
+		RW_MRC_CACHE@0x10000 0x10000
+		SMMSTORE@0x20000 0x40000
+		CONSOLE@0x60000 0x20000
+		FMAP@0x80000 0x200
+		COREBOOT(CBFS)
+	}
+}
--- a/src/mainboard/51nb/x210/board_info.txt
+++ b/src/mainboard/51nb/x210/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: 51NB
+Board name: Thinkpad X210
+Category: laptop
+ROM package: SOIC8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2017
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -0,0 +1,176 @@
+chip soc/intel/skylake
+
+	# Enable Panel as eDP and configure power delays
+	register "gpu_pp_up_delay_ms"		  = "210"	# T3
+	register "gpu_pp_down_delay_ms"		  = "500"	# T10
+	register "gpu_pp_cycle_delay_ms"	  = "5000"	# T12
+	register "gpu_pp_backlight_on_delay_ms"	  = "1"		# T7
+	register "gpu_pp_backlight_off_delay_ms"  = "200"	# T9
+
+	# Enable deep Sx states
+	register "deep_s3_enable_ac" = "1"
+	register "deep_s3_enable_dc" = "1"
+	register "deep_s5_enable_ac" = "1"
+	register "deep_s5_enable_dc" = "1"
+	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+	register "eist_enable" = "1"
+
+	# GPE configuration
+	# Note that GPE events called out in ASL code rely on this
+	# route. i.e. If this route changes then the affected GPE
+	# offset bits also need to be changed.
+	register "gpe0_dw0" = "GPP_C"
+	register "gpe0_dw1" = "GPP_D"
+	register "gpe0_dw2" = "GPP_E"
+
+	register "gen1_dec" = "0x000c0081"
+	register "gen2_dec" = "0x000c0681"
+	register "gen3_dec" = "0x000c1641"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# Disable DPTF
+	register "dptf_enable" = "0"
+
+	# FSP Configuration
+	register "ProbelessTrace" = "0"
+	register "EnableLan" = "0"
+	register "EnableSata" = "1"
+	register "SataSalpSupport" = "1"
+	register "SataMode" = "0"
+
+	# The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
+	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsEnable[2]" = "1"
+	register "SataPortsDevSlp[0]" = "1"
+	register "SataPortsDevSlp[1]" = "1"
+	register "SataPortsDevSlp[2]" = "1"
+	register "EnableAzalia" = "1"
+	register "DspEnable" = "0"
+	register "IoBufferOwnership" = "0"
+	register "EnableTraceHub" = "0"
+	register "SsicPortEnable" = "0"
+	register "SmbusEnable" = "1"
+	register "Cio2Enable" = "0"
+	register "ScsEmmcEnabled" = "0"
+	register "ScsEmmcHs400Enabled" = "0"
+	register "ScsSdCardEnabled" = "0"
+	register "PttSwitch" = "0"
+	register "SkipExtGfxScan" = "1"
+	register "Device4Enable" = "1"
+	register "HeciEnabled" = "1"
+	register "SaGv" = "SaGv_Enabled"
+	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
+	register "PmConfigSlpS4MinAssert" = "1"		# 1s
+	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
+	register "PmConfigSlpAMinAssert" = "3"		# 2s
+	register "PmTimerDisabled" = "0"
+
+	register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+	register "pirqa_routing" = "PCH_IRQ11"
+	register "pirqb_routing" = "PCH_IRQ10"
+	register "pirqc_routing" = "PCH_IRQ11"
+	register "pirqd_routing" = "PCH_IRQ11"
+	register "pirqe_routing" = "PCH_IRQ11"
+	register "pirqf_routing" = "PCH_IRQ11"
+	register "pirqg_routing" = "PCH_IRQ11"
+	register "pirqh_routing" = "PCH_IRQ11"
+
+	register "PmConfigPciClockRun" = "1"
+
+	# Enable Root Ports 3, 4 and 9
+	register "PcieRpEnable[2]" = "1" # Ethernet controller
+	register "PcieRpClkReqSupport[2]" = "1"
+	register "PcieRpClkReqNumber[2]" = "0"
+	register "PcieRpClkSrcNumber[2]" = "0"
+	register "PcieRpAdvancedErrorReporting[2]" = "1"
+	register "PcieRpLtrEnable[2]" = "1"
+
+	register "PcieRpEnable[3]" = "1" # Wireless controller
+	register "PcieRpClkReqSupport[3]" = "1"
+	register "PcieRpClkReqNumber[3]" = "1"
+	register "PcieRpClkSrcNumber[3]" = "1"
+	register "PcieRpAdvancedErrorReporting[3]" = "1"
+	register "PcieRpLtrEnable[3]" = "1"
+
+	register "PcieRpEnable[8]" = "1" # NVMe controller
+	register "PcieRpClkReqSupport[8]" = "1"
+	register "PcieRpClkReqNumber[8]" = "4"
+	register "PcieRpClkSrcNumber[8]" = "4"
+	register "PcieRpAdvancedErrorReporting[8]" = "1"
+	register "PcieRpLtrEnable[8]" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"		# Type-A Port (left)
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"		# Type-A Port (left)
+	register "usb2_ports[2]" = "USB2_PORT_FLEX(OC_SKIP)"	# FPR
+	register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"	# SD
+	register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)"	# INT
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC1)"		# Type-A Port (right)
+	register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"	# Webcam
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)"	# mPCIe / WiFi Port
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# mSATA / WWAN Port
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A Port (left)
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A Port (left)
+
+	# PL1 override 25W
+	register "tdp_pl1_override" = "25"
+
+	# PL2 override 44W
+	register "tdp_pl2_override" = "44"
+
+	# Send an extra VR mailbox command for the PS4 exit issue
+	register "SendVrMbxCmd" = "2"
+
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.2 on  end # Thermal Subsystem
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 17.0 on  end # SATA
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 on  end # PCI Express Port 3
+		device pci 1c.3 on  end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1f.0 on
+			chip ec/51nb/npce985la0dx
+				device pnp 0c09.0 on end
+				device pnp 4e.5   on end
+				device pnp 4e.6   on end
+				device pnp 4e.11  on end
+			end
+		end # LPC Interface
+		device pci 1f.1 off end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 off end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
--- a/src/mainboard/51nb/x210/dsdt.asl
+++ b/src/mainboard/51nb/x210/dsdt.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x05,		// DSDT revision: ACPI v5.0
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include "acpi/platform.asl"
+
+	#include <soc/intel/skylake/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/skylake/acpi/systemagent.asl>
+		#include <soc/intel/skylake/acpi/pch.asl>
+		#include "acpi/graphics.asl"
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	// Mainboard specific
+	#include "acpi/mainboard.asl"
+}
--- a/src/mainboard/51nb/x210/gma-mainboard.ads
+++ b/src/mainboard/51nb/x210/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+-- This file is part of the coreboot project.
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      eDP,
+      Others => Disabled);
+
+end GMA.Mainboard;
--- a/src/mainboard/51nb/x210/gpio.h
+++ b/src/mainboard/51nb/x210/gpio.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#ifndef __ACPI__
+
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0),
+/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00),
+/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00),
+/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00),
+/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00),
+/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0),
+/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000),
+/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000),
+/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0),
+/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0),
+/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0),
+/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000),
+/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0),
+/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000),
+/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0),
+/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0),
+/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0),
+/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0),
+/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0),
+/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0),
+/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0),
+/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0),
+/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000),
+/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000),
+/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000),
+/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0),
+/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000),
+/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000),
+/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000),
+/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
+/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
+/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000),
+/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0),
+/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0),
+/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0),
+/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0),
+/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0),
+/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0),
+/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0),
+/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000),
+/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000),
+/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000),
+/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000),
+/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000),
+/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0),
+/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0),
+/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0),
+/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0),
+/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000),
+/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000),
+/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000),
+/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000),
+/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000),
+/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000),
+/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0),
+/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0),
+/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0),
+/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000),
+/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0),
+/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000),
+/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0),
+/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0),
+/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0),
+/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0),
+/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0),
+/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0),
+/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0),
+/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000),
+/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000),
+/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000),
+/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000),
+/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000),
+/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0),
+/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00),
+/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000),
+/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0),
+/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0),
+/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0),
+/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0),
+/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0),
+/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0),
+/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0),
+/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0),
+/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0),
+/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0),
+/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0),
+/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000),
+/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000),
+/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000),
+/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000),
+/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000),
+/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000),
+/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000),
+/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000),
+/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0),
+/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0),
+/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0),
+/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0),
+/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0),
+/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0),
+/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0),
+/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0),
+/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0),
+/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0),
+/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0),
+/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0),
+/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0),
+/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0),
+/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0),
+/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0),
+/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0),
+/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0),
+/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000),
+};
+
+#endif
+
+#endif
--- a/src/mainboard/51nb/x210/hda_verb.c
+++ b/src/mainboard/51nb/x210/hda_verb.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x14f15069,	/* Codec Vendor / Device ID: Conexant CX20585 */
+	0x17aa2155,	/* Subsystem ID */
+	12,		/* Number of jacks (NID entries) */
+
+	0x0017ff00,	/* Function Reset */
+	0x0017ff00,	/* Double Function Reset */
+	0x0017ff00,
+	0x0017ff00,
+
+	/* Bits 31:28 - Codec Address */
+	/* Bits 27:20 - NID */
+	/* Bits 19:8 - Verb ID */
+	/* Bits 7:0  - Payload */
+
+	/* NID 0x01, HDA Codec Subsystem ID */
+	AZALIA_SUBVENDOR(0, 0x17aa2155),
+
+	/* Pin Widget Verb Table */
+	AZALIA_PIN_CFG(0, 0x19, 0x042140f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x61a190f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x04a190f0),
+	AZALIA_PIN_CFG(0, 0x1c, 0x612140f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x601700f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x40f001f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x901701f0),
+	AZALIA_PIN_CFG(0, 0x1B, 0x40f001f0),
+	AZALIA_PIN_CFG(0, 0x22, 0x40f001f0),
+	AZALIA_PIN_CFG(0, 0x23, 0x90a601f0),
+};
+
+const u32 pc_beep_verbs[] = {
+};
+AZALIA_ARRAY_SIZES;
--- a/src/mainboard/51nb/x210/mainboard.c
+++ b/src/mainboard/51nb/x210/mainboard.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	 * dependencies during hardware initialization. */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	/* Route 0x4e/4f to LPC */
+	lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
--- a/src/mainboard/51nb/x210/romstage.c
+++ b/src/mainboard/51nb/x210/romstage.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later  */
+/* This file is part of the coreboot project. */
+
+#include <string.h>
+#include <assert.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <arch/io.h>
+#include <string.h>
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+	/* Rcomp resistor */
+	const u16 RcompResistor[3] = { 121, 81, 100 };
+	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+	/* Rcomp target */
+	const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 };
+	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg;
+	struct spd_block blk = {
+		.addr_map = { 0x50, 0x52 },
+	};
+
+	mem_cfg = &mupd->FspmConfig;
+
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+	assert(blk.spd_array[0][0] != 0);
+
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+	mem_cfg->DqPinsInterleaved = TRUE;
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t) blk.spd_array[1];
+}
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -10,6 +10,9 @@ endchoice

 source "src/mainboard/*/Kconfig"

+config MAINBOARD_VENDOR
+	string "Mainboard vendor name"
+
 config BOARD_ROMSIZE_KB_64
 	bool
 config BOARD_ROMSIZE_KB_128
@@ -44,16 +47,16 @@ config BOARD_ROMSIZE_KB_65536
 # TODO: No help text possible for choice fields?
 choice
 	prompt "ROM chip size"
-	default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64
-	default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128
-	default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256
-	default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
-	default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
-	default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
-	default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
-	default COREBOOT_ROMSIZE_KB_5120 if BOARD_ROMSIZE_KB_5120
-	default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144
-	default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
+	default COREBOOT_ROMSIZE_KB_64    if BOARD_ROMSIZE_KB_64
+	default COREBOOT_ROMSIZE_KB_128   if BOARD_ROMSIZE_KB_128
+	default COREBOOT_ROMSIZE_KB_256   if BOARD_ROMSIZE_KB_256
+	default COREBOOT_ROMSIZE_KB_512   if BOARD_ROMSIZE_KB_512
+	default COREBOOT_ROMSIZE_KB_1024  if BOARD_ROMSIZE_KB_1024
+	default COREBOOT_ROMSIZE_KB_2048  if BOARD_ROMSIZE_KB_2048
+	default COREBOOT_ROMSIZE_KB_4096  if BOARD_ROMSIZE_KB_4096
+	default COREBOOT_ROMSIZE_KB_5120  if BOARD_ROMSIZE_KB_5120
+	default COREBOOT_ROMSIZE_KB_6144  if BOARD_ROMSIZE_KB_6144
+	default COREBOOT_ROMSIZE_KB_8192  if BOARD_ROMSIZE_KB_8192
 	default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240
 	default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288
 	default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
@@ -145,16 +148,16 @@ endchoice
 # Map the config names to an integer (KB).
 config COREBOOT_ROMSIZE_KB
 	int
-	default 64 if COREBOOT_ROMSIZE_KB_64
-	default 128 if COREBOOT_ROMSIZE_KB_128
-	default 256 if COREBOOT_ROMSIZE_KB_256
-	default 512 if COREBOOT_ROMSIZE_KB_512
-	default 1024 if COREBOOT_ROMSIZE_KB_1024
-	default 2048 if COREBOOT_ROMSIZE_KB_2048
-	default 4096 if COREBOOT_ROMSIZE_KB_4096
-	default 5120 if COREBOOT_ROMSIZE_KB_5120
-	default 6144 if COREBOOT_ROMSIZE_KB_6144
-	default 8192 if COREBOOT_ROMSIZE_KB_8192
+	default    64 if COREBOOT_ROMSIZE_KB_64
+	default   128 if COREBOOT_ROMSIZE_KB_128
+	default   256 if COREBOOT_ROMSIZE_KB_256
+	default   512 if COREBOOT_ROMSIZE_KB_512
+	default  1024 if COREBOOT_ROMSIZE_KB_1024
+	default  2048 if COREBOOT_ROMSIZE_KB_2048
+	default  4096 if COREBOOT_ROMSIZE_KB_4096
+	default  5120 if COREBOOT_ROMSIZE_KB_5120
+	default  6144 if COREBOOT_ROMSIZE_KB_6144
+	default  8192 if COREBOOT_ROMSIZE_KB_8192
 	default 10240 if COREBOOT_ROMSIZE_KB_10240
 	default 12288 if COREBOOT_ROMSIZE_KB_12288
 	default 16384 if COREBOOT_ROMSIZE_KB_16384
@@ -164,21 +167,21 @@ config COREBOOT_ROMSIZE_KB
 # Map the config names to a hex value (bytes).
 config ROM_SIZE
 	hex
-	default 0x10000 if COREBOOT_ROMSIZE_KB_64
-	default 0x20000 if COREBOOT_ROMSIZE_KB_128
-	default 0x40000 if COREBOOT_ROMSIZE_KB_256
-	default 0x80000 if COREBOOT_ROMSIZE_KB_512
-	default 0x100000 if COREBOOT_ROMSIZE_KB_1024
-	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
-	default 0x400000 if COREBOOT_ROMSIZE_KB_4096
-	default 0x500000 if COREBOOT_ROMSIZE_KB_5120
-	default 0x600000 if COREBOOT_ROMSIZE_KB_6144
-	default 0x800000 if COREBOOT_ROMSIZE_KB_8192
-	default 0xa00000 if COREBOOT_ROMSIZE_KB_10240
-	default 0xc00000 if COREBOOT_ROMSIZE_KB_12288
-	default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
-	default 0x2000000 if COREBOOT_ROMSIZE_KB_32768
-	default 0x4000000 if COREBOOT_ROMSIZE_KB_65536
+	default 0x00010000 if COREBOOT_ROMSIZE_KB_64
+	default 0x00020000 if COREBOOT_ROMSIZE_KB_128
+	default 0x00040000 if COREBOOT_ROMSIZE_KB_256
+	default 0x00080000 if COREBOOT_ROMSIZE_KB_512
+	default 0x00100000 if COREBOOT_ROMSIZE_KB_1024
+	default 0x00200000 if COREBOOT_ROMSIZE_KB_2048
+	default 0x00400000 if COREBOOT_ROMSIZE_KB_4096
+	default 0x00500000 if COREBOOT_ROMSIZE_KB_5120
+	default 0x00600000 if COREBOOT_ROMSIZE_KB_6144
+	default 0x00800000 if COREBOOT_ROMSIZE_KB_8192
+	default 0x00a00000 if COREBOOT_ROMSIZE_KB_10240
+	default 0x00c00000 if COREBOOT_ROMSIZE_KB_12288
+	default 0x01000000 if COREBOOT_ROMSIZE_KB_16384
+	default 0x02000000 if COREBOOT_ROMSIZE_KB_32768
+	default 0x04000000 if COREBOOT_ROMSIZE_KB_65536

 config ENABLE_POWER_BUTTON
 	bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
--- a/src/mainboard/adlink/Kconfig
+++ b/src/mainboard/adlink/Kconfig
@@ -4,7 +4,6 @@ comment "see under vendor LiPPERT"
 # any further boards will then be ADLINK

 config MAINBOARD_VENDOR
-	string
 	default "ADLINK"

 endif # VENDOR_ADLINK
--- a/src/mainboard/amd/Kconfig
+++ b/src/mainboard/amd/Kconfig
@@ -10,7 +10,6 @@ endchoice
 source "src/mainboard/amd/*/Kconfig"

 config MAINBOARD_VENDOR
-	string
 	default "AMD"

 endif # VENDOR_AMD
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci_def.h>
-#include <device/device.h>
-#include <AGESA.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <northbridge/amd/pi/00660F01/chip.h>
-#include <FchPlatform.h>
-#include <stdlib.h>
-#include <string.h>
-#include <northbridge/amd/pi/dimmSpd.h>
-#include <boardid.h>
-
-#include "imc.h"
-#include "hudson.h"
-
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_READ_SPD,                 board_ReadSpd },
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-static const GPIO_CONTROL oem_bettong_gpio[] = {
-	{86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA},
-	{64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA},
-	{-1}
-};
-
-/* Bettong Hardware Monitor Fan Control
- * Hardware limitation:
- *  HWM will fail to read the input temperature via I2C if other
- *  software switches the I2C address.  AMD recommends using IMC
- *  to control fans, instead of HWM.
- */
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
-	/* Enable IMC fan control. the recommand way */
-	imc_reg_init();
-
-	FchParams->Imc.ImcEnable = TRUE;
-	FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */
-	FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
-
-	memset(&FchParams->Imc.EcStruct, 0, sizeof(FCH_EC));
-}
-
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such as Azalia, SATA, IMC etc.
- */
-AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
-{
-	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
-
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-
-		FchParams_reset->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams_reset->FchReset.Xhci1Enable = FALSE;
-		FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
-		if (CONFIG(HUDSON_IMC_FWM))
-			oem_fan_control(FchParams_env);
-
-		/* XHCI configuration */
-		if (CONFIG(HUDSON_XHCI_ENABLE))
-			FchParams_env->Usb.Xhci0Enable = TRUE;
-		else
-			FchParams_env->Usb.Xhci0Enable = FALSE;
-
-		FchParams_env->Usb.Xhci1Enable = FALSE;
-		FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is irremovable. */
-
-		/* sata configuration */
-		/* SD configuration */
-		/* Rev F has an on-board eMMC, which only supports SD 2.0 */
-		if (board_id() == 'F') {
-			FchParams_env->Sd.SdConfig = SdVer2;
-		}
-	}
-	printk(BIOS_DEBUG, "Done\n");
-
-	return AGESA_SUCCESS;
-}
-
-static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
-{
-	AGESA_READ_SPD_PARAMS *info = ConfigPtr;
-	int spdAddress;
-
-	if (!ENV_ROMSTAGE)
-		return AGESA_UNSUPPORTED;
-
-	DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2);
-
-	if (dev == NULL)
-		return AGESA_ERROR;
-
-	DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
-
-	if (config == NULL)
-		return AGESA_ERROR;
-
-	UINT8 spdAddrLookup_rev_F [2][2][4]= {
-		{ {0xA0, 0xA2}, {0xA4, 0xAC}, }, /* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
-		{ {0x00, 0x00}, {0x00, 0x00}, }, /* socket 1 - Channel 0 & 1 - 8-bit SPD addresses */
-	};
-
-	if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
-		return AGESA_ERROR;
-	if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
-		return AGESA_ERROR;
-	if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
-		return AGESA_ERROR;
-	if (board_id() == 'F')
-		spdAddress = spdAddrLookup_rev_F
-			[info->SocketId] [info->MemChannelId] [info->DimmId];
-	else
-		spdAddress = config->spdAddrLookup
-			[info->SocketId] [info->MemChannelId] [info->DimmId];
-
-	if (spdAddress == 0)
-		return AGESA_ERROR;
-	int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
-	if (err)
-		return AGESA_ERROR;
-
-	return AGESA_SUCCESS;
-}
--- a/src/mainboard/amd/bettong/BiosCallOuts.h
+++ b/src/mainboard/amd/bettong/BiosCallOuts.h
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define FAN_INPUT_INTERNAL_DIODE	0
-#define FAN_INPUT_TEMP0			1
-#define FAN_INPUT_TEMP1			2
-#define FAN_INPUT_TEMP2			3
-#define FAN_INPUT_TEMP3			4
-#define FAN_INPUT_TEMP0_FILTER		5
-#define FAN_INPUT_ZERO			6
-#define FAN_INPUT_DISABLED		7
-
-#define FAN_AUTOMODE			(1 << 0)
-#define FAN_LINEARMODE			(1 << 1)
-#define FAN_STEPMODE			~(1 << 1)
-#define FAN_POLARITY_HIGH		(1 << 2)
-#define FAN_POLARITY_LOW		~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ			0x0
-#define FREQ_25KHZ			0x1
-#define FREQ_23KHZ			0x2
-#define FREQ_21KHZ			0x3
-#define FREQ_29KHZ			0x4
-#define FREQ_18KHZ			0x5
-#define FREQ_100HZ			0xF7
-#define FREQ_87HZ			0xF8
-#define FREQ_58HZ			0xF9
-#define FREQ_44HZ			0xFA
-#define FREQ_35HZ			0xFB
-#define FREQ_29HZ			0xFC
-#define FREQ_22HZ			0xFD
-#define FREQ_14HZ			0xFE
-#define FREQ_11HZ			0xFF
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -1,60 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config BOARD_AMD_BETTONG
-	def_bool n
-
-if BOARD_AMD_BETTONG
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	#select BINARYPI_LEGACY_WRAPPER
-	#select ROMCC_BOOTBLOCK
-	select CPU_AMD_PI_00660F01
-	select NORTHBRIDGE_AMD_PI_00660F01
-	select SOUTHBRIDGE_AMD_PI_KERN
-	select DEFAULT_POST_ON_LPC
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_8192
-	select GFXUMA
-
-config MAINBOARD_DIR
-	string
-	default "amd/bettong"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "FP4"
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config HUDSON_LEGACY_FREE
-	bool
-	default y
-
-endif # BOARD_AMD_BETTONG
--- a/src/mainboard/amd/bettong/Kconfig.name
+++ b/src/mainboard/amd/bettong/Kconfig.name
@@ -1,3 +0,0 @@
-# Disabled
-#config BOARD_AMD_BETTONG
-#	bool "Bettong"
--- a/src/mainboard/amd/bettong/Makefile.inc
+++ b/src/mainboard/amd/bettong/Makefile.inc
@@ -1,23 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-romstage-y += boardid.c
-
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c
-ramstage-y += boardid.c
--- a/src/mainboard/amd/bettong/OemCustomize.c
+++ b/src/mainboard/amd/bettong/OemCustomize.c
@@ -1,154 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-#include <boardid.h>
-
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 3, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x02, 0)
-	},
-
-	/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x03, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 6, 6),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, 2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x05, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x06, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
-	{
-		DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags  !!!IMPORTANT!!! Terminate last element of array */
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x07, 0)
-	},
-
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DP0 */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-	},
-	/* DP1 */
-	{
-		0, /*DESCRIPTOR_TERMINATE_LIST, */
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	},
-	/* DP2 */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly (
-	IN  OUT AMD_EARLY_PARAMS    *InitEarly
-	)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
-
-static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
-	DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
-	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
-	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
-	MOTHER_BOARD_LAYERS(LAYERS_6),
-	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
-	CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
-	ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
-	CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
-	PSO_END
-};
-
-void OemPostParams(AMD_POST_PARAMS *PostParams)
-{
-	if (board_id() == 'F') {
-		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
-	}
-}
--- a/src/mainboard/amd/bettong/README
+++ b/src/mainboard/amd/bettong/README
@@ -1,25 +0,0 @@
-coreboot is changing all the time and the patches are reabsed when pushed to
-community, so it is a little difficult to provide stable Bettong code.
-From now on, AMD provides source code which is validated by QA team.
-The code is pushed to github https://github.com/BTDC/coreboot
-The version is identified by a tag. All the changes will be pushed to coreboot
-community.
-
-=====
-Version: TCMEF1F0        Release Date: 09/29/2015
-
-Changes from last version:
-1. Fix external graphics issue.
-2. Add board ID support.
-3. Support DDR4.
-4. Support SD 2.0.
-5. Fix Windows 7 S4 issue.
-6. Add GPIO, I2C and UART support.
-7. Fix the interrupt routine.
-8. Restruct PCI interrupt table (C00/C01).
-9. Fix DSDT issue.
-10. Fix the PCIe lane map.
-11. Lower the TOM to give more MMIO space.
-12. Add USB device.
-13. Set the USB3 port as irremovable.
-14. Update AGESA to CarrizoPI 1.1.0.1.
--- a/src/mainboard/amd/bettong/acpi/carrizo_fch.asl
+++ b/src/mainboard/amd/bettong/acpi/carrizo_fch.asl
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device(GPIO) {
-	Name (_HID, "AMD0030")
-	Name (_CID, "AMD0030")
-	Name(_UID, 0)
-
-	Method (_CRS, 0x0, NotSerialized) {
-		Name (RBUF, ResourceTemplate () {
-			//
-			// Interrupt resource. In this example, banks 0 & 1 share the same
-			// interrupt to the parent controller and similarly banks 2 & 3.
-			//
-			// N.B. The definition below is chosen for an arbitrary
-			//      test platform. It needs to be changed to reflect the hardware
-			//      configuration of the actual platform
-			//
-			Interrupt(ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
-
-			//
-			// Memory resource. The definition below is chosen for an arbitrary
-			// test platform. It needs to be changed to reflect the hardware
-			// configuration of the actual platform.
-			//
-			Memory32Fixed(ReadWrite, 0xFED81500, 0x300)
-		})
-
-		Return (RBUF)
-	}
-
-	Method (_STA, 0x0, NotSerialized) {
-			Return (0x0F)
-	}
-}
-
-Device(FUR0) {
-	Name(_HID,"AMD0020")
-	Name(_UID,0x0)
-	Name(_CRS, ResourceTemplate() {
-		IRQ(Edge, ActiveHigh, Exclusive) {10}
-		Memory32Fixed(ReadWrite, 0xFEDC6000, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized) {
-		Return (0x0F)
-	}
-}
-
-Device(FUR1) {
-	Name(_HID,"AMD0020")
-	Name(_UID,0x1)
-	Name(_CRS, ResourceTemplate() {
-			IRQ(Edge, ActiveHigh, Exclusive) {11}
-			Memory32Fixed(ReadWrite, 0xFEDC8000, 0x2000)
-	})
-	Method (_STA, 0x0, NotSerialized) {
-			Return (0x0F)
-	}
-}
-
-Device(I2CA) {
-	Name(_HID,"AMD0010")
-	Name(_UID,0x0)
-	Name(_CRS, ResourceTemplate() {
-		IRQ(Edge, ActiveHigh, Exclusive) {3}
-		Memory32Fixed(ReadWrite, 0xFEDC2000, 0x1000)
-	})
-
-	Method (_STA, 0x0, NotSerialized) {
-		Return (0x0F)
-	}
-}
-
-Device(I2CB)
-{
-	Name(_HID,"AMD0010")
-	Name(_UID,0x1)
-	Name(_CRS, ResourceTemplate() {
-		IRQ(Edge, ActiveHigh, Exclusive) {15}
-		Memory32Fixed(ReadWrite, 0xFEDC3000, 0x1000)
-	})
-	Method (_STA, 0x0, NotSerialized) {
-		Return (0x0F)
-	}
-}
--- a/src/mainboard/amd/bettong/acpi/gpe.asl
+++ b/src/mainboard/amd/bettong/acpi/gpe.asl
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
--- a/src/mainboard/amd/bettong/acpi/mainboard.asl
+++ b/src/mainboard/amd/bettong/acpi/mainboard.asl
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Memory related values */
-Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-Name(PBLN, 0x0)	/* Length of BIOS area */
-
-Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-
-/* Some global data */
-Name(OSVR, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-Name(OSV, Ones)	/* Assume nothing */
-Name(PMOD, One)	/* Assume APIC */
--- a/src/mainboard/amd/bettong/acpi/routing.asl
+++ b/src/mainboard/amd/bettong/acpi/routing.asl
@@ -1,247 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Name(PR0, Package(){
-	/* NB devices */
-	/* Bus 0, Dev 0 - F16 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
-	Package(){0x0001FFFF, 0, INTB, 0 },
-	Package(){0x0001FFFF, 1, INTC, 0 },
-
-
-	/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
-	Package(){0x0002FFFF, 0, INTC, 0 },
-	Package(){0x0002FFFF, 1, INTD, 0 },
-	Package(){0x0002FFFF, 2, INTA, 0 },
-	Package(){0x0002FFFF, 3, INTB, 0 },
-
-	/* FCH devices */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, INTA, 0 },
-	Package(){0x0014FFFF, 1, INTB, 0 },
-	Package(){0x0014FFFF, 2, INTC, 0 },
-	Package(){0x0014FFFF, 3, INTD, 0 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, INTC, 0 },
-	Package(){0x0012FFFF, 1, INTB, 0 },
-
-	Package(){0x0013FFFF, 0, INTC, 0 },
-	Package(){0x0013FFFF, 1, INTB, 0 },
-
-	Package(){0x0016FFFF, 0, INTC, 0 },
-	Package(){0x0016FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, INTC, 0 },
-	Package(){0x0010FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, INTD, 0 },
-
-})
-
-Name(APR0, Package(){
-	/* NB devices in APIC mode */
-	/* Bus 0, Dev 0 - F15 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	Package(){0x0001FFFF, 0, 0, 43 },
-	Package(){0x0001FFFF, 1, 0, 40 },
-
-	/* Bus 0, Dev 2 - PCIe Bridges  */
-	Package(){0x0002FFFF, 0, 0, 44 },
-	Package(){0x0002FFFF, 1, 0, 45 },
-	Package(){0x0002FFFF, 2, 0, 46 },
-	Package(){0x0002FFFF, 3, 0, 47 },
-
-	Package(){0x0003FFFF, 0, 0, 49 },
-	Package(){0x0003FFFF, 1, 0, 50 },
-	Package(){0x0003FFFF, 2, 0, 51 },
-	Package(){0x0003FFFF, 3, 0, 52 },
-
-	Package(){0x0008FFFF, 0, 0, 35 },
-	Package(){0x0008FFFF, 1, 0, 32 },
-	Package(){0x0008FFFF, 2, 0, 33 },
-	Package(){0x0008FFFF, 3, 0, 34 },
-
-	/* SB devices in APIC mode */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, 0, 16 },
-	Package(){0x0014FFFF, 1, 0, 17 },
-	Package(){0x0014FFFF, 2, 0, 18 },
-	Package(){0x0014FFFF, 3, 0, 19 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, 0, 18 },
-	Package(){0x0012FFFF, 1, 0, 17 },
-
-	Package(){0x0013FFFF, 0, 0, 18 },
-	Package(){0x0013FFFF, 1, 0, 17 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, 0, 18},
-	Package(){0x0010FFFF, 1, 0, 17},
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, 0, 19 },
-
-	/* Bus 0, Dev 9, Func 2 - HDAudio */
-	Package(){0x0009FFFF, 0, 0, 39 },
-	Package(){0x0009FFFF, 1, 0, 36 },
-	Package(){0x0009FFFF, 2, 0, 37 },
-	Package(){0x0009FFFF, 3, 0, 38 },
-})
-
-Name(PS2, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS2, Package(){
-	Package(){0x0000FFFF, 0, 0, 18 },
-	Package(){0x0000FFFF, 1, 0, 19 },
-	Package(){0x0000FFFF, 2, 0, 16 },
-	Package(){0x0000FFFF, 3, 0, 17 },
-})
-
-/* GFX */
-Name(PS4, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS4, Package(){
-	/* PCIe slot - Hooked to PCIe slot 4 */
-	Package(){0x0000FFFF, 0, 0, 24 },
-	Package(){0x0000FFFF, 1, 0, 25 },
-	Package(){0x0000FFFF, 2, 0, 26 },
-	Package(){0x0000FFFF, 3, 0, 27 },
-})
-
-/* GPP 0 */
-Name(PS5, Package(){
-	Package(){0x0000FFFF, 0, INTB, 0 },
-	Package(){0x0000FFFF, 1, INTC, 0 },
-	Package(){0x0000FFFF, 2, INTD, 0 },
-	Package(){0x0000FFFF, 3, INTA, 0 },
-})
-Name(APS5, Package(){
-	Package(){0x0000FFFF, 0, 0, 28 },
-	Package(){0x0000FFFF, 1, 0, 29 },
-	Package(){0x0000FFFF, 2, 0, 30 },
-	Package(){0x0000FFFF, 3, 0, 31 },
-})
-
-/* GPP 1 */
-Name(PS6, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS6, Package(){
-	Package(){0x0000FFFF, 0, 0, 32 },
-	Package(){0x0000FFFF, 1, 0, 33 },
-	Package(){0x0000FFFF, 2, 0, 34 },
-	Package(){0x0000FFFF, 3, 0, 35 },
-})
-
-/* GPP 2 */
-Name(PS7, Package(){
-	Package(){0x0000FFFF, 0, INTD, 0 },
-	Package(){0x0000FFFF, 1, INTA, 0 },
-	Package(){0x0000FFFF, 2, INTB, 0 },
-	Package(){0x0000FFFF, 3, INTC, 0 },
-})
-Name(APS7, Package(){
-	Package(){0x0000FFFF, 0, 0, 36 },
-	Package(){0x0000FFFF, 1, 0, 37 },
-	Package(){0x0000FFFF, 2, 0, 38 },
-	Package(){0x0000FFFF, 3, 0, 39 },
-})
-
-/* GPP 3 */
-Name(PS8, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS8, Package(){
-	Package(){0x0000FFFF, 0, 0, 40 },
-	Package(){0x0000FFFF, 1, 0, 41 },
-	Package(){0x0000FFFF, 2, 0, 42 },
-	Package(){0x0000FFFF, 3, 0, 43 },
-})
-
-/* GFX 2 */
-Name(PSA, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APSA, Package(){
-	Package(){0x0000FFFF, 0, 0, 52 },
-	Package(){0x0000FFFF, 1, 0, 53 },
-	Package(){0x0000FFFF, 2, 0, 54 },
-	Package(){0x0000FFFF, 3, 0, 55 },
-})
-
-/* GFX 3 */
-Name(PSB, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APSB, Package(){
-	Package(){0x0000FFFF, 0, 0, 27 },
-	Package(){0x0000FFFF, 1, 0, 24 },
-	Package(){0x0000FFFF, 2, 0, 25 },
-	Package(){0x0000FFFF, 3, 0, 26 },
-})
-
-/* GFX 4 */
-Name(PSC, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APSC, Package(){
-	Package(){0x0000FFFF, 0, 0, 31 },
-	Package(){0x0000FFFF, 1, 0, 28 },
-	Package(){0x0000FFFF, 2, 0, 29 },
-	Package(){0x0000FFFF, 3, 0, 30 },
-})
--- a/src/mainboard/amd/bettong/acpi/sleep.asl
+++ b/src/mainboard/amd/bettong/acpi/sleep.asl
@@ -1,86 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear wake status structure. */
-	Store(0, PEWD)
-	Store(0, Index(WKST,0))
-	Store(0, Index(WKST,1))
-	Store(7, UPWS)
-} /* End Method(\_PTS) */
-
-/*
-*	\_BFS OEM Back From Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		-none-
-*/
-Method(\_BFS, 1) {
-	/* DBGO("\\_BFS\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-}
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	Return(WKST)
-} /* End Method(\_WAK) */
--- a/src/mainboard/amd/bettong/acpi/usb_oc.asl
+++ b/src/mainboard/amd/bettong/acpi/usb_oc.asl
@@ -1,129 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
-
-/* USB Overcurrent GPEs */
-
-#if 0 /* TODO: Update for Bettong */
-Method(UCOC, 0) {
-	Sleep(20)
-	Store(0x13,CMTI)
-	Store(0,GPSL)
-}
-
-/* USB Port 0 overcurrent uses Gpm 0 */
-If(LLessEqual(UOM0,9)) {
-	Scope (\_GPE) {
-		Method (_L13) {
-		}
-	}
-}
-
-/* USB Port 1 overcurrent uses Gpm 1 */
-If (LLessEqual(UOM1,9)) {
-	Scope (\_GPE) {
-		Method (_L14) {
-		}
-	}
-}
-
-/* USB Port 2 overcurrent uses Gpm 2 */
-If (LLessEqual(UOM2,9)) {
-	Scope (\_GPE) {
-		Method (_L15) {
-		}
-	}
-}
-
-/* USB Port 3 overcurrent uses Gpm 3 */
-If (LLessEqual(UOM3,9)) {
-	Scope (\_GPE) {
-		Method (_L16) {
-		}
-	}
-}
-
-/* USB Port 4 overcurrent uses Gpm 4 */
-If (LLessEqual(UOM4,9)) {
-	Scope (\_GPE) {
-		Method (_L19) {
-		}
-	}
-}
-
-/* USB Port 5 overcurrent uses Gpm 5 */
-If (LLessEqual(UOM5,9)) {
-	Scope (\_GPE) {
-		Method (_L1A) {
-		}
-	}
-}
-
-/* USB Port 6 overcurrent uses Gpm 6 */
-If (LLessEqual(UOM6,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1C) { */
-		Method (_L06) {
-		}
-	}
-}
-
-/* USB Port 7 overcurrent uses Gpm 7 */
-If (LLessEqual(UOM7,9)) {
-	Scope (\_GPE) {
-		/* Method (_L1D) { */
-		Method (_L07) {
-		}
-	}
-}
-
-/* USB Port 8 overcurrent uses Gpm 8 */
-If (LLessEqual(UOM8,9)) {
-	Scope (\_GPE) {
-		Method (_L17) {
-		}
-	}
-}
-
-/* USB Port 9 overcurrent uses Gpm 9 */
-If (LLessEqual(UOM9,9)) {
-	Scope (\_GPE) {
-		Method (_L0E) {
-		}
-	}
-}
-#endif
--- a/src/mainboard/amd/bettong/acpi_tables.c
+++ b/src/mainboard/amd/bettong/acpi_tables.c
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-
-#define IO_APIC2_ADDR 0xFEC20000
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write Kern IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-					   IO_APIC_ADDR, 0);
-
-	/* TODO: Remove the hardcode */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
-					   IO_APIC2_ADDR, 24);
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
--- a/src/mainboard/amd/bettong/board_info.txt
+++ b/src/mainboard/amd/bettong/board_info.txt
@@ -1 +0,0 @@
-Category: eval
--- a/src/mainboard/amd/bettong/boardid.c
+++ b/src/mainboard/amd/bettong/boardid.c
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <amdblocks/acpimmio.h>
-#include <device/mmio.h>
-#include <southbridge/amd/common/amd_defs.h>
-#include <boardid.h>
-
-/**
- *Bettong uses 3 GPIO(5-7) pins to identify board.
- *The GPIO ports are mapped to MMIO space.
- *The GPIO value and board version are mapped as follow:
- *GPIO5 GPIO6 GPIO7 Version
- *  0     0     0      A
- *  0     0     1      B
- *  ......
- *  1     1     1      H
- */
-uint32_t board_id(void)
-{
-	u8  value = 0;
-	u8  boardrev = 0;
-	char boardid;
-
-	value = gpio0_read8((7 << 2) + 2); /* agpio7: board_id2 */
-	boardrev = value & 1;
-	value = gpio0_read8((6 << 2) + 2); /* agpio6: board_id1 */
-	boardrev |= (value & 1) << 1;
-	value = gpio0_read8((5 << 2) + 2); /* agpio5: board_id0 */
-	boardrev |= (value & 1) << 2;
-
-	boardid = 'A' + boardrev;
-
-	return boardid;
-}
--- a/src/mainboard/amd/bettong/cmos.layout
+++ b/src/mainboard/amd/bettong/cmos.layout
@@ -1,101 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-#start-bit length  config config-ID    name
-#0            8       r       0        seconds
-#8            8       r       0        alarm_seconds
-#16           8       r       0        minutes
-#24           8       r       0        alarm_minutes
-#32           8       r       0        hours
-#40           8       r       0        alarm_hours
-#48           8       r       0        day_of_week
-#56           8       r       0        day_of_month
-#64           8       r       0        month
-#72           8       r       0        year
-#80           4       r       0        rate_select
-#84           3       r       0        REF_Clock
-#87           1       r       0        UIP
-#88           1       r       0        auto_switch_DST
-#89           1       r       0        24_hour_mode
-#90           1       r       0        binary_values_enable
-#91           1       r       0        square-wave_out_enable
-#92           1       r       0        update_finished_enable
-#93           1       r       0        alarm_interrupt_enable
-#94           1       r       0        periodic_interrupt_enable
-#95           1       r       0        disable_clock_updates
-#96         288       r       0        temporary_filler
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-386          1       e       1        ECC_memory
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-416          4       e       7        boot_first
-420          4       e       7        boot_second
-424          4       e       7        boot_third
-428          4       h       0        boot_index
-432          8       h       0        boot_countdown
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Network
-7     1     HDD
-7     2     Floppy
-7     8     Fallback_Network
-7     9     Fallback_HDD
-7     10    Fallback_Floppy
-#7     3     ROM
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
--- a/src/mainboard/amd/bettong/devicetree.cb
+++ b/src/mainboard/amd/bettong/devicetree.cb
@@ -1,67 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/pi/00660F01/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/pi/00660F01
-			device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-
-		chip northbridge/amd/pi/00660F01
-			device pci 0.0 on  end # Root Complex
-			device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on  end # Internal Multimedia
-			device pci 2.0 on  end # PCIe Host Bridge
-			device pci 2.1 on  end # x4 PCIe slot
-			device pci 2.2 on  end # mPCIe slot
-			device pci 2.3 on  end # Realtek NIC
-			device pci 2.4 on  end # Edge Connector
-			device pci 2.5 on  end # Edge Connector
-			device pci 3.0 on  end # Edge Connector
-			device pci 3.1 on  end # Edge Connector
-		end	#chip northbridge/amd/pi/00660F01
-
-		chip southbridge/amd/pi/hudson
-			device pci 9.0 on  end # HDA
-			device pci 9.2 on  end # HDA
-			device pci 10.0 on  end # USB
-			device pci 11.0 on  end # SATA
-			device pci 12.0 on  end # USB
-			device pci 14.0 on  end # SM
-			#device pci 14.2 on  end # HDA	0x4383
-			device pci 14.3 on  end # LPC	0x439d
-			device pci 14.7 on  end # SD
-		end	#chip southbridge/amd/pi/hudson
-
-		chip northbridge/amd/pi/00660F01
-			device pci 18.0 on  end
-			device pci 18.1 on  end
-			device pci 18.2 on  end
-			device pci 18.3 on  end
-			device pci 18.4 on  end
-			device pci 18.5 on  end
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-				{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-		end
-
-	end #domain
-end #northbridge/amd/pi/00660F01/root_complex
--- a/src/mainboard/amd/bettong/dsdt.asl
+++ b/src/mainboard/amd/bettong/dsdt.asl
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-#include <arch/acpi.h>
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
-
-	/* Globals for the platform */
-	#include "acpi/mainboard.asl"
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_PR) */
-	#include <cpu/amd/pi/00660F01/acpi/cpu.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PWRB) {
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})
-			Name(_STA, 0x0B)
-		}
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/pi/00660F01/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
-
-		/* Describe the devices in the Southbridge */
-		#include "acpi/carrizo_fch.asl"
-
-	} /* End \_SB scope */
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-}
-/* End of ASL file */
--- a/src/mainboard/amd/bettong/fchec.c
+++ b/src/mainboard/amd/bettong/fchec.c
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "fchec.h"
-
-void agesawrapper_fchecfancontrolservice()
-{
-	FCH_DATA_BLOCK LateParams;
-
-	/* Thermal Zone Parameter */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0xc6;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01;
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */
-	LateParams.Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
-
-	/* IMC Fan Policy temperature thresholds */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x3c; /*AC0 threshold in Celsius */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x28; /*AC1 threshold in Celsius */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0xff; /*AC2 threshold in Celsius */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */
-	LateParams.Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
-	/* IMC Fan Policy PWM Settings */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x50; /* AL0 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x32; /* AL1 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0xff; /* AL2 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
-	LateParams.Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
-
-	LateParams.Imc.EcStruct.IMCFUNSupportBitMap = 0x111;
-
-	FchECfancontrolservice(&LateParams);
-}
--- a/src/mainboard/amd/bettong/irq_tables.c
+++ b/src/mainboard/amd/bettong/irq_tables.c
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
-	return (unsigned long)pirq_info;
-}
--- a/src/mainboard/amd/bettong/mainboard.c
+++ b/src/mainboard/amd/bettong/mainboard.c
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- */
-static const u8 mainboard_picr_data[] = {
-	[0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
-	[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
-	[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
-	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,
-	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
-	[0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
-	[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-};
-
-static const u8 mainboard_intr_data[] = {
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
-	[0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
-	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
-	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,
-	[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,
-	[0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-	[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
-	[0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-
-
-/*************************************************
- * enable the dedicated function in bettong board.
- *************************************************/
-static void bettong_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = bettong_enable,
-};
--- a/src/mainboard/amd/bettong/mptable.c
+++ b/src/mainboard/amd/bettong/mptable.c
@@ -1,157 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
-{
-	mc->mpc_length += length;
-	mc->mpc_entry_count++;
-}
-
-static void my_smp_write_bus(struct mp_config_table *mc,
-			     unsigned char id, const char *bustype)
-{
-	struct mpc_config_bus *mpc;
-	mpc = smp_next_mpc_entry(mc);
-	memset(mpc, '\0', sizeof(*mpc));
-	mpc->mpc_type = MP_BUS;
-	mpc->mpc_busid = id;
-	memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
-	smp_add_mpc_entry(mc, sizeof(*mpc));
-}
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	/*
-	 * By the time this function gets called, the IOAPIC registers
-	 * have been written so they can be read to get the correct
-	 * APIC ID and Version
-	 */
-	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-	memcpy(mc->mpc_oem, "AMD     ", 8);
-
-	smp_write_processors(mc);
-
-	my_smp_write_bus(mc, 0, "PCI   ");
-	my_smp_write_bus(mc, 1, "PCI   ");
-	bus_isa = 0x02;
-	my_smp_write_bus(mc, bus_isa, "ISA   ");
-
-	/* I/O APICs:   APIC ID Version State   Address */
-	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
-	smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000);
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin)				\
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin)				\
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-	/* Internal VGA */
-	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
-
-	/* SMBUS */
-	PCI_INT(0x0, 0x14, 0x0, 0x10);
-
-	/* HD Audio */
-	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
-
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
-	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
-
-	/* sata */
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
-
-	/* on board NIC & Slot PCIE.  */
-
-	/* PCI slots */
-	struct device *dev = pcidev_on_root(0x14, 4);
-	if (dev && dev->enabled) {
-		u8 bus_pci = dev->link_list->secondary;
-		/* PCI_SLOT 0. */
-		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
-		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
-		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
-		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
-
-		/* PCI_SLOT 1. */
-		PCI_INT(bus_pci, 0x6, 0x0, 0x15);
-		PCI_INT(bus_pci, 0x6, 0x1, 0x16);
-		PCI_INT(bus_pci, 0x6, 0x2, 0x17);
-		PCI_INT(bus_pci, 0x6, 0x3, 0x14);
-
-		/* PCI_SLOT 2. */
-		PCI_INT(bus_pci, 0x7, 0x0, 0x16);
-		PCI_INT(bus_pci, 0x7, 0x1, 0x17);
-		PCI_INT(bus_pci, 0x7, 0x2, 0x14);
-		PCI_INT(bus_pci, 0x7, 0x3, 0x15);
-	}
-
-	/* PCIe Lan*/
-	PCI_INT(0x0, 0x06, 0x0, 0x13);
-
-	/* FCH PCIe PortA */
-	PCI_INT(0x0, 0x15, 0x0, 0x10);
-	/* FCH PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, 0x11);
-	/* FCH PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, 0x12);
-	/* FCH PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, 0x13);
-
-	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);
-	return (unsigned long)smp_write_config_table(v);
-}
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-/* Mask BIST bit 31. One result of Silicon Observation
- * report_bist_failure(bist & 0x7FFFFFFF);
- */
-
-static void romstage_main_template(void)
-{
-	u32 val;
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-
-#if CONFIG(HUDSON_UART)
-		configure_hudson_uart();
-#endif
-		post_code(0x31);
-		console_init();
-	}
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	/* After AMD_INIT_ENV -> move to ramstage ? */
-	if (acpi_is_wakeup_s4()) {
-		outb(0xEE, PM_INDEX);
-		outb(0x8, PM_DATA);
-	}
-}
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -1,319 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *               2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <device/azalia.h>
-#include <FchPlatform.h>
-#include <stdlib.h>
-
-#include "imc.h"
-#include "hudson.h"
-
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_READ_SPD,                 agesa_ReadSpd_from_cbfs },
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/**
- * Realtek ALC272 CODEC Verb Table
- */
-static const CODEC_ENTRY Alc272_VerbTbl[] = {
-	{ 0x11, 0x411111F0 },               /*        - S/PDIF Output 2         */
-	{ 0x12, 0x411111F0 },               /*        - Digital Mic 1/2 [GPIO0] */
-	{ 0x13, 0x411111F0 },               /*        - Digital Mic 3/4 [GPIO1] */
-	{ 0x14, 0x411111F0 },               /* Port D - Front Panel headphone   */
-	{ 0x15, 0x411111F0 },               /* Port A - Surround                */
-	{ 0x17, 0x411111F0 },               /* Port H - Mono                    */
-	{ 0x18,                             /* Port B - MIC - combo jack        */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
-			| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
-			| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
-			| (AZALIA_PINCFG_COLOR_BLACK << 12)
-			| (4 << 4)
-			| (0 << 0)
-	},
-	{ 0x19, 0x411111F0 },               /* Port F - Front Panel Mic        */
-	{ 0x1A, 0x411111F0 },               /* Port C - LINE1      */
-	{ 0x1B, 0x411111F0 },               /* Port E - Front Panel line-out   */
-	{ 0x1D, 0x40130605 },               /*        - PCBEEP     */
-	{ 0x1E, 0x411111F0 },               /*        - SPDIF_OUT1 */
-	{ 0x21,                             /* Port I - HPout - combo jack     */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
-			| (AZALIA_PINCFG_DEVICE_HP_OUT << 20)
-			| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
-			| (AZALIA_PINCFG_COLOR_BLACK << 12)
-			| (4 << 4)
-			| (0 << 0)
-	},
-	{ 0xFF, 0xFFFFFFFF },
-};
-
-static const CODEC_TBL_LIST CodecTableList[] =
-{
-	{0x10ec0272, Alc272_VerbTbl},
-	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
-};
-
-#define FAN_INPUT_INTERNAL_DIODE	0
-#define FAN_INPUT_TEMP0			1
-#define FAN_INPUT_TEMP1			2
-#define FAN_INPUT_TEMP2			3
-#define FAN_INPUT_TEMP3			4
-#define FAN_INPUT_TEMP0_FILTER		5
-#define FAN_INPUT_ZERO			6
-#define FAN_INPUT_DISABLED		7
-
-#define FAN_AUTOMODE			(1 << 0)
-#define FAN_LINEARMODE			(1 << 1)
-#define FAN_STEPMODE			~(1 << 1)
-#define FAN_POLARITY_HIGH		(1 << 2)
-#define FAN_POLARITY_LOW		~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ			0x0
-#define FREQ_25KHZ			0x1
-#define FREQ_23KHZ			0x2
-#define FREQ_21KHZ			0x3
-#define FREQ_29KHZ			0x4
-#define FREQ_18KHZ			0x5
-#define FREQ_100HZ			0xF7
-#define FREQ_87HZ			0xF8
-#define FREQ_58HZ			0xF9
-#define FREQ_44HZ			0xFA
-#define FREQ_35HZ			0xFB
-#define FREQ_29HZ			0xFC
-#define FREQ_22HZ			0xFD
-#define FREQ_14HZ			0xFE
-#define FREQ_11HZ			0xFF
-
-/*
- * Hardware Monitor Fan Control
- * Hardware limitation:
- *  HWM will fail to read the input temperature via I2C if other
- *  software switches the I2C address.  AMD recommends using IMC
- *  to control fans, instead of HWM.
- */
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
-	FCH_HWM_FAN_CTR oem_factl[5] = {
-		/*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
-		/* DB-FT3 FanOUT0 Fan header J32 */
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		/* DB-FT3 FanOUT1 Fan header J31*/
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-	};
-	LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
-
-	/* Enable IMC fan control. the recommended way */
-	if (CONFIG(HUDSON_IMC_FWM)) {
-		/* HwMonitorEnable = TRUE &&  HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;               /* 0 disable, 1 enable TSI Auto Polling */
-
-		FchParams->Imc.ImcEnable = TRUE;
-		FchParams->Hwm.HwmControl = 1;                          /* 1 IMC, 0 HWM */
-		FchParams->Imc.ImcEnableOverWrite = 1;                  /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
-
-		LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
-
-		/* Thermal Zone Parameter */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00;    /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;    /* 6 | BIT3 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0;
-
-		/* IMC Fan Policy temperature thresholds */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;       /* AC0 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0;       /* AC1 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0;       /* AC2 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0;       /* AC3 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0;       /* AC4 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0;       /* AC5 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0;       /* AC6 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0;       /* AC7 lowest threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0;       /* critical threshold* in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
-		/* IMC Fan Policy PWM Settings */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0;       /* AL0 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0;       /* AL1 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0;       /* AL2 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00;    /* AL3 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00;    /* AL4 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00;    /* AL5 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00;    /* AL6 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00;    /* AL7 percentage */
-
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;    /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
-
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60;      /* AC0 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40;      /* AC1 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0;       /* AC2 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0;       /* AC3 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0;       /* AC4 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0;       /* AC5 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0;       /* AC6 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0;       /* AC7 lowest threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0;       /* critical threshold* in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
-
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0;       /* AL0 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0;       /* AL1 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0;       /* AL2 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00;    /* AL3 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00;    /* AL4 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00;    /* AL5 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00;    /* AL6 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00;    /* AL7 percentage */
-
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2;     /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;     /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
-
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3;     /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;     /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0;     /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
-
-		/* IMC Function */
-		FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;    /*BIT0 | BIT4 |BIT8; */
-
-		/* NOTE:
-		 * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
-		 * AGESA put EcDefaultMessage as global data in ROM, so we can't override it.
-		 * so we remove it from AGESA code. Please See FchInitLateHwm.
-		 */
-	} else {
-		/* HWM fan control, using the alternative method */
-		FchParams->Imc.ImcEnable = FALSE;
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;                /* 1 enable, 0 disable TSI Auto Polling */
-	}
-}
-
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
-{
-	AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams =  (FCH_RESET_DATA_BLOCK *) FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-		FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
-		FchParams->FchReset.SataEnable = hudson_sata_enable();
-		FchParams->FchReset.IdeEnable = hudson_ide_enable();
-		FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->FchReset.Xhci1Enable = FALSE;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
-		/* Azalia Controller OEM Codec Table Pointer */
-		FchParams->Azalia.AzaliaPinCfg = TRUE;
-		FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
-			.AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03,
-			.AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03,
-			.AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03,
-			.AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03
-		};
-		FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
-		/* Azalia Controller Front Panel OEM Table Pointer */
-
-		/* Fan Control */
-		oem_fan_control(FchParams);
-
-		/* XHCI configuration */
-		FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams->Usb.Xhci1Enable = FALSE;
-
-		/* sata configuration */
-		FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
-		switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
-		case SataRaid:
-		case SataAhci:
-		case SataAhci7804:
-		case SataLegacyIde:
-			FchParams->Sata.SataIdeMode = FALSE;
-			break;
-		case SataIde2Ahci:
-		case SataIde2Ahci7804:
-		default: /* SataNativeIde */
-			FchParams->Sata.SataIdeMode = TRUE;
-			break;
-		}
-	}
-	printk(BIOS_DEBUG, "Done\n");
-
-	return AGESA_SUCCESS;
-}
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig
+++ b/src/mainboard/amd/db-ft3b-lc/Kconfig
@@ -1,65 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config BOARD_AMD_DB_FT3B_LC
-	def_bool n
-
-if BOARD_AMD_DB_FT3B_LC
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	#select BINARYPI_LEGACY_WRAPPER
-	#select ROMCC_BOOTBLOCK
-	select CPU_AMD_PI_00730F01
-	select NORTHBRIDGE_AMD_PI_00730F01
-	select SOUTHBRIDGE_AMD_PI_AVALON
-	select DEFAULT_POST_ON_LPC
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_8192
-	select GFXUMA
-
-config MAINBOARD_DIR
-	string
-	default "amd/db-ft3b-lc"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "DB-FT3b-LC"
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config HUDSON_LEGACY_FREE
-	bool
-	default y
-
-config DIMM_SPD_SIZE
-	int
-	default 128
-
-endif # BOARD_AMD_DB_FT3B_LC
--- a/src/mainboard/amd/db-ft3b-lc/Kconfig.name
+++ b/src/mainboard/amd/db-ft3b-lc/Kconfig.name
@@ -1,3 +0,0 @@
-# Disabled
-#config BOARD_AMD_DB_FT3B_LC
-#	bool "DB-FT3b-LC"
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
@@ -1,40 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
-
-## DIMM SPD for on-board memory
-SPD_BIN = $(obj)/spd.bin
-
-# Order of names in SPD_SOURCES is important!
-SPD_SOURCES  = Memphis_MEM4G16D3EABG
-
-SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
-
-# Include spd ROM data
-$(SPD_BIN): $(SPD_DEPS)
-	for f in $+; \
-	  do for c in $$(cat $$f | grep -v ^#); \
-	    do printf $$(printf '\%o' 0x$$c); \
-	  done; \
-	done > $@
-
-cbfs-files-y += spd.bin
-spd.bin-file := $(SPD_BIN)
-spd.bin-type := spd
--- a/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
+++ b/src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
@@ -1,237 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-# LOWCOST board has 2GB using 4 Memphis MEM4G16D3EABG chips
-
-# The datasheet is available at:
-# http://www.memphis.ag/fileadmin/datasheets/MEM4G16D3EABG_10.pdf
-
-#      SPD contents for LC (LowCost) 4GB DDR3 (1600MHz) soldered down
-
-#      0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
-#              bits[3:0]: 1 = 128 SPD Bytes Used
-#              bits[6:4]: 1 = 256 SPD Bytes Total
-#              bit7     : 0 = CRC covers bytes 0 ~ 125
-11
-
-#      1 SPD Revision -
-#              0x10 = Revision 1.0
-10
-
-#      2 Key Byte / DRAM Device Type
-#              bits[7:0]: 0x0b = DDR3 SDRAM
-0B
-
-#      3 Key Byte / Module Type
-#              bits[3:0]: 1 = RDIMM
-#              bits[3:0]: 2 = UDIMM
-#              bits[3:0]: 3 = SO-DIMM
-#              bits[7:4]:     reserved
-03
-
-#      4 SDRAM CHIP Density and Banks
-#              bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
-#              bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
-#              bits[6:4]: 0 = 3 (8 banks)
-#              bit7     :     reserved
-04
-
-#      5 SDRAM Addressing
-#              bits[2:0]: 1 = 10 Column Address Bits
-#              bits[5:3]: 2 = 14 Row Address Bits
-#              bits[5:3]: 3 = 15 Row Address Bits
-#              bits[7:6]:     reserved
-19
-
-#      6 Module Nominal Voltage, VDD
-#              bit0     : 0 = 1.5 V operable
-#              bit1     : 0 = NOT 1.35 V operable
-#              bit2     : 0 = NOT 1.25 V operable
-#              bits[7:3]:     reserved
-00
-
-#      7 Module Organization
-#              bits[2:0]: 2 = 16 bits
-#              bits[5:3]: 0 = 1 Rank
-#              bits[7:6]:     reserved
-02
-
-#      8 Module Memory Bus Width
-#              bits[2:0]: 3 = Primary bus width is 64 bits
-#              bits[4:3]: 0 = 0 bits (no bus width extension)
-#              bits[7:5]:     reserved
-03
-
-#      9 Fine Timebase (FTB) Dividend / Divisor
-#              bits[3:0]: 0x02 divisor
-#              bits[7:4]: 0x05 dividend
-#              5/2 = 2.5ps
-52
-
-#      10 Medium Timebase (MTB) Dividend
-#      11 Medium Timebase (MTB) Divisor
-#              1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz
-01 08
-
-#      12 SDRAM Minimum Cycle Time (tCKmin)
-#              0x0a  = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
-0A
-
-#      13 Reserved
-00
-
-#      14 CAS Latencies Supported, Least Significant Byte
-#      15 CAS Latencies Supported, Most Significant Byte
-#              Cas Latencies of 11 - 5 are supported
-FE 00
-
-#      16 Minimum CAS Latency Time (tAAmin)
-#              0x6E = 13.75ns - DDR3-1600K
-6E
-
-#      17 Minimum Write Recovery Time (tWRmin)
-#              0x78 = tWR of 15ns - All DDR3 speed grades
-78
-
-#      18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-#              0x6E = 13.75ns -  DDR3-1600K
-6E
-
-#      19 Minimum Row Active to Row Active Delay Time (tRRDmin)
-#              0x3C = 7.5ns
-3C
-
-#      20 Minimum Row Precharge Delay Time (tRPmin)
-#              0x6E = 13.75ns -  DDR3-1600K
-6E
-
-#      21 Upper Nibbles for tRAS and tRC
-#              bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
-#              bits[7:4]: tRC most significant nibble = 1 (see byte 23)
-11
-
-#      22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-#              0x118 = 35ns - DDR3-1600 (see byte 21)
-2C
-
-#      23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-#              0x186 = 48.75ns - DDR3-1600K
-95
-
-#      24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
-#      25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
-#              0x500 = 160ns - for 2 Gigabit chips
-#              0x820 = 260ns - for 4 Gigabit chips
-20 08
-
-#      26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
-#              0x3c = 7.5 ns - All DDR3 SDRAM speed bins
-3C
-
-#      27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
-#              0x3c =  7.5ns -  All DDR3 SDRAM speed bins
-3C
-
-#      28 Upper Nibble for tFAWmin
-#      29 Minimum Four Activate Window Delay Time (tFAWmin)
-#              0x0140 = 40ns -  DDR3-1600, 2 KB page size
-#              0x00F0 = 30ns -  DDR3-1600, 2 KB page size
-00 F0
-
-#      30 SDRAM Optional Feature
-#              bit0     : 1= RZQ/6 supported
-#              bit1     : 1 = RZQ/7 supported
-#              bits[6:2]:     reserved
-#              bit7     : 1 = DLL Off mode supported
-83
-
-#      31 SDRAM Thermal and Refresh Options
-#              bit0     : 1 = Temp up to 95c supported
-#              bit1     : 0 = 85-95c uses 2x refresh rate
-#              bit2     : 1 = Auto Self Refresh supported
-#              bit3     : 0 = no on die thermal sensor
-#              bits[6:4]:     reserved
-#              bit7     : 0 = partial self refresh supported
-05
-
-#      32 Module Thermal Sensor
-#              0 = Thermal sensor not incorporated onto this assembly
-00
-
-#      33 SDRAM Device Type
-#              bits[1:0]: 0 = Signal Loading not specified
-#              bits[3:2]:     reserved
-#              bits[6:4]: 0 = Die count not specified
-#              bit7     : 0 = Standard Monolithic DRAM Device
-00
-
-#      34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
-#      35 Fine Offset for Minimum CAS Latency Time (tAAmin)
-#      36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
-#      37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
-#      38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
-00 00 00 00 00
-
-#      39 - 59 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-#      60 Raw Card Extension, Module Nominal Height
-#              bits[4:0]: 0 = <= 15mm tall
-#              bits[7:5]: 0 = raw card revision 0-3
-00
-
-#      61 Module Maximum Thickness
-#              bits[3:0]: 0 = thickness front <= 1mm
-#              bits[7:4]: 0 = thinkness back <= 1mm
-00
-
-#      62 Reference Raw Card Used
-#              bits[4:0]: 0 = Reference Raw card A used
-#              bits[6:5]: 0 = revision 0
-#              bit7     : 0 = Reference raw cards A through AL
-00
-
-#      63 Address Mapping from Edge Connector to DRAM
-#              bit0     : 0 = standard mapping (not mirrored)
-#              bits[7:1]:     reserved
-00
-
-#      64 - 116 (reserved)
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00
-00 00 00 00 00
-
-#      117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-#              0x0001 = AMD
-00 01
-
-#      119 Module ID: Module Manufacturing Location - oem specified
-#      120 Module ID: Module Manufacture Year in BCD
-#              0x14 = 2014
-00 14
-
-#      121 Module ID: Module Manufacture week
-#              0x12 = 12th week
-12
-
-#      122 - 125: Module Serial Number
-00 00 00 00
-
-#      126 - 127: Cyclical Redundancy Code
-00 00
--- a/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
+++ b/src/mainboard/amd/db-ft3b-lc/OemCustomize.c
@@ -1,208 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <PlatformMemoryConfiguration.h>
-
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-	/* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x01, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x02, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x03, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
-	{
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x04, 0)
-	},
-	/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
-		PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled, 0x05, 0)
-	}
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	/* DP0 to HDMI0/DP */
-	{
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
-	IN  OUT AMD_EARLY_PARAMS    *InitEarly
-	)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
-
-/*
- *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
- *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
- *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
- *  use its default conservative settings.
- */
-static const PSO_ENTRY ROMDATA PlatformMemoryConfiguration[] = {
-  /*
-   * The following macros are supported (use comma to separate macros):
-   *
-   * MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-   *      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-   *      AGESA will base on this value to disable unused MemClk to save power.
-   *      Example:
-   *      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-   *           Bit AM3/S1g3 pin name
-   *           0   M[B,A]_CLK_H/L[0]
-   *           1   M[B,A]_CLK_H/L[1]
-   *           2   M[B,A]_CLK_H/L[2]
-   *           3   M[B,A]_CLK_H/L[3]
-   *           4   M[B,A]_CLK_H/L[4]
-   *           5   M[B,A]_CLK_H/L[5]
-   *           6   M[B,A]_CLK_H/L[6]
-   *           7   M[B,A]_CLK_H/L[7]
-   *      And platform has the following routing:
-   *           CS0   M[B,A]_CLK_H/L[4]
-   *           CS1   M[B,A]_CLK_H/L[2]
-   *           CS2   M[B,A]_CLK_H/L[3]
-   *           CS3   M[B,A]_CLK_H/L[5]
-   *      Then platform can specify the following macro:
-   *      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-   *
-   * CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-   *      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-   *      AGESA will base on this value to tristate unused CKE to save power.
-   *
-   * ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-   *      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-   *      AGESA will base on this value to tristate unused ODT pins to save power.
-   *
-   * CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-   *      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-   *      AGESA will base on this value to tristate unused Chip select to save power.
-   *
-   * NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-   *      Specifies the number of DIMM slots per channel.
-   *
-   * NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-   *      Specifies the number of Chip selects per channel.
-   *
-   * NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-   *      Specifies the number of channels per socket.
-   *
-   * OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-   *      Specifies DDR bus speed of channel ChannelID on socket SocketID.
-   *
-   * DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-   *      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-   *
-   * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-   *      Byte6Seed, Byte7Seed, ByteEccSeed)
-   *      Specifies the write leveling seed for a channel of a socket.
-   *
-   * HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-   *      Byte6Seed, Byte7Seed, ByteEccSeed)
-   *      Speicifes the HW RXEN training seed for a channel of a socket
-   */
-
-#define SEED_WL 0x0E
-WRITE_LEVELING_SEED(
-       ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-       SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,SEED_WL,
-       SEED_WL),
-
-#define SEED_A 0x12
-HW_RXEN_SEED(
-       ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
-       SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
-       SEED_A),
-
-  NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
-  NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
-  MOTHER_BOARD_LAYERS(LAYERS_6),
-
-  MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-  CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
-  ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
-  CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
-
-  PSO_END
-};
-
-void OemPostParams(AMD_POST_PARAMS *PostParams)
-{
-	/* Add the memory configuration table needed for soldered down memory */
-	PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryConfiguration;
-}
--- a/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/gpe.asl
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
--- a/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/ide.asl
@@ -1,2 +0,0 @@
-/* No license required */
-/* No IDE functionality */
--- a/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/mainboard.asl
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Memory related values */
-Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-Name(PBLN, 0x0)	/* Length of BIOS area */
-
-Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-
-/* Some global data */
-Name(OSVR, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-Name(OSV, Ones)	/* Assume nothing */
-Name(PMOD, One)	/* Assume APIC */
-
-/* AcpiGpe0Blk */
-OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
-	Field(GP0B, ByteAcc, NoLock, Preserve) {
-	, 11,
-	USBS, 1,
-}
--- a/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/routing.asl
@@ -1,194 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "routing.asl"
-	}
-*/
-
-/* Routing is in System Bus scope */
-Name(PR0, Package(){
-	/* NB devices */
-	/* Bus 0, Dev 0 - F16 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	/* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */
-	Package(){0x0001FFFF, 0, INTB, 0 },
-	Package(){0x0001FFFF, 1, INTC, 0 },
-
-
-	/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
-	Package(){0x0002FFFF, 0, INTC, 0 },
-	Package(){0x0002FFFF, 1, INTD, 0 },
-	Package(){0x0002FFFF, 2, INTA, 0 },
-	Package(){0x0002FFFF, 3, INTB, 0 },
-
-	/* FCH devices */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, INTA, 0 },
-	Package(){0x0014FFFF, 1, INTB, 0 },
-	Package(){0x0014FFFF, 2, INTC, 0 },
-	Package(){0x0014FFFF, 3, INTD, 0 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, INTC, 0 },
-	Package(){0x0012FFFF, 1, INTB, 0 },
-
-	Package(){0x0013FFFF, 0, INTC, 0 },
-	Package(){0x0013FFFF, 1, INTB, 0 },
-
-	Package(){0x0016FFFF, 0, INTC, 0 },
-	Package(){0x0016FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, INTC, 0 },
-	Package(){0x0010FFFF, 1, INTB, 0 },
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, INTD, 0 },
-
-})
-
-Name(APR0, Package(){
-	/* NB devices in APIC mode */
-	/* Bus 0, Dev 0 - F15 Host Controller */
-
-	/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-	Package(){0x0001FFFF, 0, 0, 44 },
-	Package(){0x0001FFFF, 1, 0, 45 },
-
-	/* Bus 0, Dev 2 - PCIe Bridges  */
-	Package(){0x0002FFFF, 0, 0, 24 },
-	Package(){0x0002FFFF, 1, 0, 25 },
-	Package(){0x0002FFFF, 2, 0, 26 },
-	Package(){0x0002FFFF, 3, 0, 27 },
-
-
-	/* SB devices in APIC mode */
-	/* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */
-	Package(){0x0014FFFF, 0, 0, 16 },
-	Package(){0x0014FFFF, 1, 0, 17 },
-	Package(){0x0014FFFF, 2, 0, 18 },
-	Package(){0x0014FFFF, 3, 0, 19 },
-
-	/* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */
-	/* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */
-	Package(){0x0012FFFF, 0, 0, 18 },
-	Package(){0x0012FFFF, 1, 0, 17 },
-
-	Package(){0x0013FFFF, 0, 0, 18 },
-	Package(){0x0013FFFF, 1, 0, 17 },
-
-	Package(){0x0016FFFF, 0, 0, 18 },
-	Package(){0x0016FFFF, 1, 0, 17 },
-
-	/* Bus 0, Dev 10 - USB: XHCI func 0, 1 */
-	Package(){0x0010FFFF, 0, 0, 0x12},
-	Package(){0x0010FFFF, 1, 0, 0x11},
-
-	/* Bus 0, Dev 17 - SATA controller */
-	Package(){0x0011FFFF, 0, 0, 19 },
-
-})
-
-Name(PS2, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS2, Package(){
-	Package(){0x0000FFFF, 0, 0, 18 },
-	Package(){0x0000FFFF, 1, 0, 19 },
-	Package(){0x0000FFFF, 2, 0, 16 },
-	Package(){0x0000FFFF, 3, 0, 17 },
-})
-
-/* GFX */
-Name(PS4, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS4, Package(){
-	/* PCIe slot - Hooked to PCIe slot 4 */
-	Package(){0x0000FFFF, 0, 0, 24 },
-	Package(){0x0000FFFF, 1, 0, 25 },
-	Package(){0x0000FFFF, 2, 0, 26 },
-	Package(){0x0000FFFF, 3, 0, 27 },
-})
-
-/* GPP 0 */
-Name(PS5, Package(){
-	Package(){0x0000FFFF, 0, INTB, 0 },
-	Package(){0x0000FFFF, 1, INTC, 0 },
-	Package(){0x0000FFFF, 2, INTD, 0 },
-	Package(){0x0000FFFF, 3, INTA, 0 },
-})
-Name(APS5, Package(){
-	Package(){0x0000FFFF, 0, 0, 28 },
-	Package(){0x0000FFFF, 1, 0, 29 },
-	Package(){0x0000FFFF, 2, 0, 30 },
-	Package(){0x0000FFFF, 3, 0, 31 },
-})
-
-/* GPP 1 */
-Name(PS6, Package(){
-	Package(){0x0000FFFF, 0, INTC, 0 },
-	Package(){0x0000FFFF, 1, INTD, 0 },
-	Package(){0x0000FFFF, 2, INTA, 0 },
-	Package(){0x0000FFFF, 3, INTB, 0 },
-})
-Name(APS6, Package(){
-	Package(){0x0000FFFF, 0, 0, 32 },
-	Package(){0x0000FFFF, 1, 0, 33 },
-	Package(){0x0000FFFF, 2, 0, 34 },
-	Package(){0x0000FFFF, 3, 0, 35 },
-})
-
-/* GPP 2 */
-Name(PS7, Package(){
-	Package(){0x0000FFFF, 0, INTD, 0 },
-	Package(){0x0000FFFF, 1, INTA, 0 },
-	Package(){0x0000FFFF, 2, INTB, 0 },
-	Package(){0x0000FFFF, 3, INTC, 0 },
-})
-Name(APS7, Package(){
-	Package(){0x0000FFFF, 0, 0, 36 },
-	Package(){0x0000FFFF, 1, 0, 37 },
-	Package(){0x0000FFFF, 2, 0, 38 },
-	Package(){0x0000FFFF, 3, 0, 39 },
-})
-
-/* GPP 3 */
-Name(PS8, Package(){
-	Package(){0x0000FFFF, 0, INTA, 0 },
-	Package(){0x0000FFFF, 1, INTB, 0 },
-	Package(){0x0000FFFF, 2, INTC, 0 },
-	Package(){0x0000FFFF, 3, INTD, 0 },
-})
-Name(APS8, Package(){
-	Package(){0x0000FFFF, 0, 0, 40 },
-	Package(){0x0000FFFF, 1, 0, 41 },
-	Package(){0x0000FFFF, 2, 0, 42 },
-	Package(){0x0000FFFF, 3, 0, 43 },
-})
--- a/src/mainboard/amd/db-ft3b-lc/acpi/si.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/si.asl
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope(\_SI) {
-	Method(_SST, 1) {
-		/* DBGO("\\_SI\\_SST\n") */
-		/* DBGO("   New Indicator state: ") */
-		/* DBGO(Arg0) */
-		/* DBGO("\n") */
-	}
-} /* End Scope SI */
--- a/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/sleep.asl
@@ -1,95 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-*	Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-
-External(\_SB.APTS, MethodObj)
-External(\_SB.AWAK, MethodObj)
-
-Method(_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear wake status structure. */
-	Store(0, Index(WKST,0))
-	Store(0, Index(WKST,1))
-	Store(7, UPWS)
-	\_SB.APTS(Arg0)
-} /* End Method(\_PTS) */
-
-/*
-*	\_BFS OEM Back From Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		-none-
-*/
-Method(\_BFS, 1) {
-	/* DBGO("\\_BFS\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-}
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* clear USB wake up signal */
-	Store(1, USBS)
-
-	\_SB.AWAK(Arg0)
-
-	Return(WKST)
-} /* End Method(\_WAK) */
--- a/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/thermal.asl
@@ -1,2 +0,0 @@
-/* No license required */
-/* No thermal zone functionality */
--- a/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl
+++ b/src/mainboard/amd/db-ft3b-lc/acpi/usb_oc.asl
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* simple name description */
-/*
-#include <arch/acpi.h>
-DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
-		)
-	{
-		#include "usb.asl"
-	}
-*/
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
--- a/src/mainboard/amd/db-ft3b-lc/acpi_tables.c
+++ b/src/mainboard/amd/db-ft3b-lc/acpi_tables.c
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write SB800 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-					   IO_APIC_ADDR, 0);
-
-	/* TODO: Remove the hardcode */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
-					   0xFEC20000, 24);
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
--- a/src/mainboard/amd/db-ft3b-lc/board_info.txt
+++ b/src/mainboard/amd/db-ft3b-lc/board_info.txt
@@ -1,6 +0,0 @@
-Board name: DB-FT3b-LC
-Board URL: http://wwwd.amd.com/amd/devsite.nsf/platforms/db-ft3-lc.htm
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
--- a/src/mainboard/amd/db-ft3b-lc/cmos.layout
+++ b/src/mainboard/amd/db-ft3b-lc/cmos.layout
@@ -1,66 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-395          1       e       1        hw_scrubber
-396          1       e       1        interleave_chip_selects
-397          2       e       8        max_mem_clock
-399          1       e       2        multi_core
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          4       e       9        slow_cpu
-444          1       e       1        nmi
-445          1       e       1        iommu
-456          1       e       1        ECC_memory
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
--- a/src/mainboard/amd/db-ft3b-lc/devicetree.cb
+++ b/src/mainboard/amd/db-ft3b-lc/devicetree.cb
@@ -1,61 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2013 Advanced Micro Devices, Inc.
-# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/pi/00730F01/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/pi/00730F01
-			device lapic 0 on  end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-
-		chip northbridge/amd/pi/00730F01
-			device pci 0.0 on  end # Root Complex
-			device pci 0.2 off end # IOMMU
-			device pci 1.0 on  end # Internal Graphics P2P bridge 0x9804
-			device pci 1.1 on  end # Internal Multimedia
-			device pci 2.0 on  end # PCIe Host Bridge
-			device pci 2.1 on  end # x4 PCIe slot
-			device pci 2.2 on  end # mPCIe slot
-			device pci 2.3 on  end # Realtek NIC
-			device pci 2.4 off end # Edge Connector
-			device pci 2.5 off end # Edge Connector
-			device pci 8.0 off end # Platform Security Processor
-		end	#chip northbridge/amd/pi/00730F01
-
-		chip southbridge/amd/pi/hudson
-			device pci 10.0 on  end # XHCI HC0
-			device pci 11.0 on  end # SATA
-			device pci 12.0 on  end # EHCI #0
-			device pci 13.0 on  end # EHCI #1
-			device pci 14.0 on  end # SMBus
-			device pci 14.2 on  end # HDA	0x4383
-			device pci 14.3 on  end # LPC	0x439d
-			device pci 14.7 on  end # SD
-			device pci 16.0 on  end # EHCI #2
-			register "sd_mode" = "3"
-		end	#chip southbridge/amd/pi/hudson
-
-		device pci 18.0 on  end
-		device pci 18.1 on  end
-		device pci 18.2 on  end
-		device pci 18.3 on  end
-		device pci 18.4 on  end
-		device pci 18.5 on  end
-
-	end #domain
-end #northbridge/amd/pi/00730F01/root_complex
--- a/src/mainboard/amd/db-ft3b-lc/dsdt.asl
+++ b/src/mainboard/amd/db-ft3b-lc/dsdt.asl
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-#include <arch/acpi.h>
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
-
-	/* Globals for the platform */
-	#include "acpi/mainboard.asl"
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_PR) */
-	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PWRB) {
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})
-			Name(_STA, 0x0B)
-		}
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
-
-	} /* End \_SB scope */
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-
-	/* Define the Thermal zones and methods for the platform */
-	#include "acpi/thermal.asl"
-
-	/* Define the System Indicators for the platform */
-	#include "acpi/si.asl"
-}
-/* End of ASL file */
--- a/src/mainboard/amd/db-ft3b-lc/irq_tables.c
+++ b/src/mainboard/amd/db-ft3b-lc/irq_tables.c
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
-
-	return (unsigned long)pirq_info;
-}
--- a/src/mainboard/amd/db-ft3b-lc/mainboard.c
+++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/pi/hudson/pci_devs.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <northbridge/amd/pi/00730F01/pci_devs.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- */
-static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
-	[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
-	/* INTA# - INTH# */
-	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
-	[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/22 INTA-C */
-	[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* SATA */
-	[0x41] = 0x0F,
-};
-
-static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
-	[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
-	/* INTA# - INTH# */
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
-	/* SATA */
-	[0x41] = 0x13,
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	/* {PCI_devfn,	{PIN A, PIN B, PIN C, PIN D}}, */
-	{GFX_DEVFN,	{PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}},			/* VGA:		01.0 */
-	{ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}},			/* Audio:	01.1 */
-	{NB_PCIE_PORT1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* x4 PCIe:	02.1 */
-	{NB_PCIE_PORT2_DEVFN,	{PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},	/* mPCIe:	02.2 */
-	{NB_PCIE_PORT3_DEVFN,	{PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}},	/* NIC:		02.3 */
-	{XHCI_DEVFN,	{PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* XHCI:	10.0 */
-	{SATA_DEVFN,	{PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SATA:	11.0 */
-	{OHCI1_DEVFN,	{PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI1:	12.0 */
-	{EHCI1_DEVFN,	{PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},	/* EHCI1:	12.2 */
-	{OHCI2_DEVFN,	{PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI2:	13.0 */
-	{EHCI2_DEVFN,	{PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},	/* EHCI2:	13.2 */
-	{SMBUS_DEVFN,	{PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SMBUS:	14.0 */
-	{HDA_DEVFN,		{PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* HDA:		14.2 */
-	{SD_DEVFN,		{PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* SD:		14.7 */
-	{OHCI3_DEVFN,	{PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI3:	16.0 (same device as xHCI 10.0) */
-	{EHCI3_DEVFN,	{PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}},	/* EHCI3:	16.2 (same device as xHCI 10.1) */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/**********************************************
- * enable the dedicated function in mainboard.
- **********************************************/
-static void mainboard_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
--- a/src/mainboard/amd/db-ft3b-lc/mptable.c
+++ b/src/mainboard/amd/db-ft3b-lc/mptable.c
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	/* Initialize the MP_Table */
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	/*
-	 * Type 0: Processor Entries:
-	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
-	 * CPU Signature (Stepping, Model, Family),
-	 * Feature Flags
-	 */
-	smp_write_processors(mc);
-
-	/*
-	 * Type 1: Bus Entries:
-	 * Bus ID, Bus Type
-	 */
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * Type 2: I/O APICs:
-	 * APIC ID, Version, APIC Flags:EN, Address
-	 */
-	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
-	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
-
-	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
-
-	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-#define IO_LOCAL_INT(type, intr, apicid, pin)				\
-	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-	/*
-	 * Type 3: I/O Interrupt Table Entries:
-	 * Int Type, Int Polarity, Int Level, Source Bus ID,
-	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
-	 */
-
-	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-#define PCI_INT(bus, dev, int_sign, pin)				\
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
-
-	/* APU Internal Graphic Device */
-	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
-	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
-
-	/* SMBUS / ACPI */
-	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
-
-	/* Southbridge HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
-
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
-	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]);
-	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
-	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]);
-	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
-	PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]);
-	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
-
-	/* on board NIC & Slot PCIE */
-	PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
-	PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
-
-	/* PCIe Lan*/
-	PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
-
-	/* FCH PCIe PortA */
-	PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
-	/* FCH PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
-	/* FCH PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
-	/* FCH PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
-
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);	/* ADDR, Enable Virtual Wire */
-	return (unsigned long)smp_write_config_table(v);
-}
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <amdblocks/acpimmio.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-static void romstage_main_template(void)
-{
-	u32 val;
-
-	/*
-	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  This following register setting has been
-	 *  replicated in every reference design since Parmer, so it is
-	 *  believed to be required even though it is not documented in
-	 *  the SoC BKDGs.  Without this setting, there is no serial
-	 *  output.
-	 */
-	pm_io_write8(0xd2, 0);
-
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-
-		post_code(0x31);
-		console_init();
-	}
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	pm_io_write8(0xea, 1);
-}
--- a/src/mainboard/amd/gardenia/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/BiosCallOuts.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/BiosCallOuts.h>
--- a/src/mainboard/amd/gardenia/Kconfig
+++ b/src/mainboard/amd/gardenia/Kconfig
@@ -1,7 +1,6 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -1,7 +1,6 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2015 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
--- a/src/mainboard/amd/gardenia/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/OemCustomize.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <chip.h>
 #include <amdblocks/agesawrapper.h>
--- a/src/mainboard/amd/gardenia/acpi/gpe.asl
+++ b/src/mainboard/amd/gardenia/acpi/gpe.asl
@@ -1,17 +1,7 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+External (\_SB.PCI0.AZHD, DeviceObj)

 Scope(\_GPE) {	/* Start Scope GPE */

--- a/src/mainboard/amd/gardenia/acpi/mainboard.asl
+++ b/src/mainboard/amd/gardenia/acpi/mainboard.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /* Memory related values */
 Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
--- a/src/mainboard/amd/gardenia/acpi/routing.asl
+++ b/src/mainboard/amd/gardenia/acpi/routing.asl
@@ -1,21 +1,8 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /*
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
 		)
 	{
--- a/src/mainboard/amd/gardenia/acpi/sleep.asl
+++ b/src/mainboard/amd/gardenia/acpi/sleep.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /* Wake status package */
 Name(WKST,Package(){Zero, Zero})
--- a/src/mainboard/amd/gardenia/acpi/usb_oc.asl
+++ b/src/mainboard/amd/gardenia/acpi/usb_oc.asl
@@ -1,22 +1,9 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /* simple name description */
 /*
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
 		)
 	{
--- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <amdblocks/agesawrapper.h>

--- a/src/mainboard/amd/gardenia/bootblock/bootblock.c
+++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <bootblock_common.h>
 #include <soc/southbridge.h>
--- a/src/mainboard/amd/gardenia/devicetree.cb
+++ b/src/mainboard/amd/gardenia/devicetree.cb
@@ -1,7 +1,6 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -1,22 +1,10 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #define MAINBOARD_HAS_SPEAKER 1

 /* DefinitionBlock Statement */
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 DefinitionBlock (
 	"DSDT.AML",	/* Output filename */
 	"DSDT",		/* Signature */
@@ -40,7 +28,7 @@ DefinitionBlock (
 	/* PCI IRQ mapping for the Southbridge */
 	#include <pcie.asl>

-	/* Describe the processor tree (\_PR) */
+	/* Describe the processor tree (\_SB) */
 	#include <cpu.asl>

 	/* Contains the supported sleep states for this chipset */
--- a/src/mainboard/amd/gardenia/gpio.c
+++ b/src/mainboard/amd/gardenia/gpio.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <soc/southbridge.h>
 #include <soc/gpio.h>
--- a/src/mainboard/amd/gardenia/gpio.h
+++ b/src/mainboard/amd/gardenia/gpio.h
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2018 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
--- a/src/mainboard/amd/gardenia/irq_tables.c
+++ b/src/mainboard/amd/gardenia/irq_tables.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <console/console.h>
 #include <device/pci_def.h>
@@ -76,7 +64,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	pirq_info = (void *)(&pirq->checksum + 1);
 	slot_num = 0;

-	/* pci bridge */
+	/* PCI bridge */
 	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
 			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
 			0);
@@ -94,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	if (sum != pirq->checksum)
 		pirq->checksum = sum;

-	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+	printk(BIOS_INFO, "%s done.\n", __func__);

 	return (unsigned long)pirq_info;
 }
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <console/console.h>
 #include <device/device.h>
--- a/src/mainboard/amd/gardenia/mptable.c
+++ b/src/mainboard/amd/gardenia/mptable.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <arch/smp/mpspec.h>
 #include <arch/ioapic.h>
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -1,14 +1,2 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 #include <AGESA.h>
 #include <amdlib.h>
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -1,7 +1,6 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2010-2011 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -13,14 +12,10 @@
 # GNU General Public License for more details.
 #

-config BOARD_AMD_INAGUA
-	def_bool n
-
 if BOARD_AMD_INAGUA

 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	#select ROMCC_BOOTBLOCK
 	select CPU_AMD_AGESA_FAMILY14
 	select NORTHBRIDGE_AMD_AGESA_FAMILY14
 	select SOUTHBRIDGE_AMD_CIMX_SB800
--- a/src/mainboard/amd/inagua/Kconfig.name
+++ b/src/mainboard/amd/inagua/Kconfig.name
@@ -1,2 +1,2 @@
-#config BOARD_AMD_INAGUA
-#	bool"Inagua"
+config BOARD_AMD_INAGUA
+	bool "Inagua"
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -1,7 +1,6 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -20,6 +19,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI
 pci$(stripped_ahcibios_id).rom-type := optionrom
 endif

+bootblock-y += bootblock.c
+
 romstage-y += buildOpts.c
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
--- a/src/mainboard/amd/inagua/OemCustomize.c
+++ b/src/mainboard/amd/inagua/OemCustomize.c
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */


 #include <AGESA.h>
--- a/src/mainboard/amd/inagua/OptionsIds.h
+++ b/src/mainboard/amd/inagua/OptionsIds.h
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /**
 * @file
--- a/src/mainboard/amd/inagua/acpi/gpe.asl
+++ b/src/mainboard/amd/inagua/acpi/gpe.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 Scope(\_GPE) {	/* Start Scope GPE */

--- a/src/mainboard/amd/inagua/acpi/ide.asl
+++ b/src/mainboard/amd/inagua/acpi/ide.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /*
 Scope (_SB) {
--- a/src/mainboard/amd/inagua/acpi/mainboard.asl
+++ b/src/mainboard/amd/inagua/acpi/mainboard.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /* Data to be patched by the BIOS during POST */
 /* FIXME the patching is not done yet! */
--- a/src/mainboard/amd/inagua/acpi/routing.asl
+++ b/src/mainboard/amd/inagua/acpi/routing.asl
@@ -1,20 +1,8 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /*
-#include <arch/acpi.h>
+#include <acpi/acpi.h>
 DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001
 		)
 	{
--- a/src/mainboard/amd/inagua/acpi/sata.asl
+++ b/src/mainboard/amd/inagua/acpi/sata.asl
@@ -1,17 +1,5 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */

 /* simple name description */

--- a/Show More
+++ b/Show More