soc/intel/apollolake/acpi: Replace Add(a,b) with ASL 2.0 syntax
Replace `Add (a, b)` with `a + b`. Change-Id: Id465558f054494d3273d5cd6077476d878d7c183 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60504 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -31,7 +31,7 @@ Scope (\_SB)
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Method (GPC1, 0x1, Serialized)
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Method (GPC1, 0x1, Serialized)
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{
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{
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/* Arg0 - GPIO DW0 address */
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/* Arg0 - GPIO DW0 address */
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Store (Add (Arg0, 0x4), Local0)
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Store (Arg0 + 4, Local0)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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Field (PDW1, AnyAcc, NoLock, Preserve) {
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Field (PDW1, AnyAcc, NoLock, Preserve) {
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TEMP, 32
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TEMP, 32
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@ -44,7 +44,7 @@ Scope (\_SB)
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{
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{
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/* Arg0 - GPIO DW0 address */
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/* Arg0 - GPIO DW0 address */
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/* Arg1 - Value for DW1 register */
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/* Arg1 - Value for DW1 register */
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Store (Add (Arg0, 0x4), Local0)
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Store (Arg0 + 4, Local0)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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OperationRegion (PDW1, SystemMemory, Local0, 4)
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Field(PDW1, AnyAcc, NoLock, Preserve) {
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Field(PDW1, AnyAcc, NoLock, Preserve) {
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TEMP,32
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TEMP,32
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@ -60,8 +60,8 @@ Scope (\_SB)
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Store (0, Local1)
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Store (0, Local1)
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Or( Or (ShiftLeft (Arg0, 16), CONFIG_PCR_BASE_ADDRESS),
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Or( Or (ShiftLeft (Arg0, 16), CONFIG_PCR_BASE_ADDRESS),
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Local1, Local1)
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Local1, Local1)
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Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply (
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Or(PAD_CFG_BASE + Multiply (Arg1, Multiply (
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GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1)
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GPIO_NUM_PAD_CFG_REGS, 4)), Local1, Local1)
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Return (Local1)
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Return (Local1)
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}
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}
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@ -109,7 +109,7 @@ Method (_CRS, 0, Serialized)
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/* Set 64bit MMIO resource base and length */
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/* Set 64bit MMIO resource base and length */
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Store (A4GS, MLEN)
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Store (A4GS, MLEN)
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Store (A4GB, MMIN)
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Store (A4GB, MMIN)
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MMAX = Add (MMIN, MLEN) - 1
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MMAX = MMIN + MLEN - 1
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}
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}
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Return (MCRS)
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Return (MCRS)
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