drivers/nxp/uwb: Add new driver for NXP UWB SR1xx chip
Add a new driver for NXP UWB SR1xx (e.g., SR150) device. The driver was originally written by Tim Wawrzynczak as a WIP in CL:3503703, and was based on drivers/spi/acpi. BUG=b:240607130 BRANCH=firmware-brya-14505.B TEST=On ghost (with follow-up CL), patch linux with NXP's pending drivers -> UWB device is probed and can respond to a simple hello packet Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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committed by
Martin Roth
parent
9e111f2853
commit
f48f1fdc84
30
src/drivers/nxp/uwb/Kconfig
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30
src/drivers/nxp/uwb/Kconfig
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config DRIVERS_NXP_UWB_SR1XX
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bool "NXP UWB SR1xx driver"
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help
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Enable support for a NXP UWB SR1xx (e.g., SR150) chip.
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A configuration should be added to device tree like below:
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device ref gspi0 on
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chip drivers/nxp/uwb
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# The ACPI name of the device. Note it will be
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# truncated to 4 characters if a longer name is given.
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register "name" = ""UWB0""
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# Description of the module.
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register "desc" = ""NXP UWB Module""
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# SPI bus speed (in Hz).
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register "speed" = "1000000"
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# The GPIO connected to SENSORINT.
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register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_HIGH(GPP_F21)"
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# The GPIO connected to CHIP_EN.
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register "ce_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A12)"
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# The GPIO connected to WAKEUP.
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register "ri_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A7)"
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device spi 0 on end
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end
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end
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1
src/drivers/nxp/uwb/Makefile.inc
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src/drivers/nxp/uwb/Makefile.inc
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ramstage-$(CONFIG_DRIVER_NXP_UWB_SR1XX) += uwb.c
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27
src/drivers/nxp/uwb/chip.h
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src/drivers/nxp/uwb/chip.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __NXP_UWB_CHIP_H__
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#define __NXP_UWB_CHIP_H__
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#include <acpi/acpi_device.h>
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struct drivers_nxp_uwb_config {
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/* ACPI Device Name */
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const char *name;
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/* Device Description */
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const char *desc;
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/* ACPI _UID */
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unsigned int uid;
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/* Bus speed in Hz (default 1MHz) */
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unsigned int speed;
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/* Use GPIO based interrupt instead of PIRQ */
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struct acpi_gpio irq_gpio;
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struct acpi_gpio ce_gpio;
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struct acpi_gpio ri_gpio;
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};
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#endif /* __NXP_UWB_CHIP_H__ */
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138
src/drivers/nxp/uwb/uwb.c
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138
src/drivers/nxp/uwb/uwb.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_device.h>
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#include <acpi/acpigen.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/path.h>
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#include <device/spi.h>
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#include <spi-generic.h>
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#include <string.h>
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#include "chip.h"
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static int spi_acpi_get_bus(const struct device *dev)
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{
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struct device *spi_dev;
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struct device_operations *ops;
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if (!dev->bus || !dev->bus->dev)
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return -1;
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spi_dev = dev->bus->dev;
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ops = spi_dev->ops;
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if (ops && ops->ops_spi_bus && ops->ops_spi_bus->dev_to_bus)
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return ops->ops_spi_bus->dev_to_bus(spi_dev);
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return -1;
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}
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static int write_gpio(struct acpi_gpio *gpio, int *curr_index)
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{
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int ret = -1;
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if (gpio->pin_count == 0)
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return ret;
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acpi_device_write_gpio(gpio);
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ret = *curr_index;
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(*curr_index)++;
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return ret;
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}
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static void nxp_uwb_fill_ssdt(const struct device *dev)
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{
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struct drivers_nxp_uwb_config *config = dev->chip_info;
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const char *scope = acpi_device_scope(dev);
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const char *path = acpi_device_path(dev);
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struct acpi_spi spi = {
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.device_select = dev->path.spi.cs,
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.speed = config->speed ? : 1 * MHz,
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.resource = scope,
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.device_select_polarity = SPI_POLARITY_LOW,
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.wire_mode = SPI_4_WIRE_MODE,
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.data_bit_length = 8,
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.clock_phase = SPI_CLOCK_PHASE_FIRST,
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.clock_polarity = SPI_POLARITY_LOW,
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};
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int curr_index = 0;
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int irq_gpio_index = -1;
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int ce_gpio_index = -1;
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int ri_gpio_index = -1;
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if (!scope)
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return;
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if (spi_acpi_get_bus(dev) == -1) {
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printk(BIOS_ERR, "%s: Cannot get bus for device.\n",
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dev_path(dev));
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return;
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}
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/* Device */
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acpigen_write_scope(scope);
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acpigen_write_device(acpi_device_name(dev));
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acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID);
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acpigen_write_name_integer("_UID", config->uid);
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if (config->desc)
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acpigen_write_name_string("_DDN", config->desc);
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acpigen_write_STA(acpi_device_status(dev));
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/* Resources */
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acpigen_write_name("_CRS");
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acpigen_write_resourcetemplate_header();
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acpi_device_write_spi(&spi);
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irq_gpio_index = write_gpio(&config->irq_gpio, &curr_index);
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ce_gpio_index = write_gpio(&config->ce_gpio, &curr_index);
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ri_gpio_index = write_gpio(&config->ri_gpio, &curr_index);
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acpigen_write_resourcetemplate_footer();
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struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
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acpi_dp_add_string(dsd, "compatible", "nxp,sr1xx");
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acpi_dp_add_gpio(dsd, "nxp,sr1xx-irq-gpios", path, irq_gpio_index, 0,
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config->irq_gpio.active_low);
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acpi_dp_add_gpio(dsd, "nxp,sr1xx-ce-gpios", path, ce_gpio_index, 0,
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config->ce_gpio.active_low);
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acpi_dp_add_gpio(dsd, "nxp,sr1xx-ri-gpios", path, ri_gpio_index, 0,
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config->ri_gpio.active_low);
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acpi_dp_write(dsd);
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acpigen_write_device_end();
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acpigen_write_scope_end();
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printk(BIOS_INFO, "%s: %s at %s\n", path,
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config->desc ? : dev->chip_ops->name, dev_path(dev));
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}
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static const char *nxp_uwb_name(const struct device *dev)
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{
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struct drivers_nxp_uwb_config *config = dev->chip_info;
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static char name[ACPI_NAME_BUFFER_SIZE];
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if (config->name)
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snprintf(name, sizeof(name), "%s", config->name);
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else
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snprintf(name, sizeof(name), "UWB%1X", spi_acpi_get_bus(dev));
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name[4] = '\0';
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return name;
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}
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static struct device_operations nxp_uwb_ops = {
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.read_resources = noop_read_resources,
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.set_resources = noop_set_resources,
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.acpi_name = nxp_uwb_name,
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.acpi_fill_ssdt = nxp_uwb_fill_ssdt,
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};
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static void nxb_uwb_enable(struct device *dev)
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{
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dev->ops = &nxp_uwb_ops;
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}
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struct chip_operations drivers_nxp_uwb_ops = {
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CHIP_NAME("NXP UWB Device")
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.enable_dev = nxb_uwb_enable
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};
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