acpi: Add acpigen_write_OSC_pci_domain
Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Dynamic SSDT generation is used to generate a list of ASL device objects based on FSP outputs (e.g. the SoC/SKU configurations) and _OSC is a method inside these objects (hence it would be straightforward to be generated altogether, plus some C codes managed boot configs could be referenced as well). This usage is optional. It is helpful for cases where the same code set supports multiple SKUs/SoCs (difficult to be handled by one set of static SSDT), and the CPU performance is good enough to run SSDT generation logics with minimal costs. TEST=intel/archercity CRB Tested with https://review.coreboot.org/c/coreboot/+/81377. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Shuo Liu
Lean Sheng Tan
parent
96d7524ee6
commit
f4a12e1d39
@ -55,3 +55,308 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin,
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acpigen_pop_len(); /* Package */
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}
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#define PCI_HOST_BRIDGE_OSC_UUID "33db4d5b-1ff7-401c-9657-7441c03dd766"
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#define CXL_HOST_BRIDGE_OSC_UUID "68f2d50b-c469-4d8a-bd3d-941a103fd3fc"
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#define OSC_RET_FAILURE 0x02
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#define OSC_RET_UNRECOGNIZED_UUID 0x04
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#define OSC_RET_UNRECOGNIZED_REV 0x08
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#define OSC_RET_CAPABILITIES_MASKED 0x10
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#define OSC_QUERY_SUPPORT_SET 0x01
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#define ASL_UUID_UNHANDLED 0x00
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#define ASL_UUID_HANDLED 0x01
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static void acpigen_OSC_handle_pcie_request(const struct device *domain);
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static void acpigen_OSC_handle_cxl_request(const struct device *domain);
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/*
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* acpigen_write_OSC_pci_domain
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*
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* Reference:
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* 6.2.11 in https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html
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*
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* _OSC ASL Arguments: (4)
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* Arg0 - A Buffer containing a UUID
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* Arg1 - An Integer containing a Revision ID of the buffer format
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* Arg2 - An Integer containing a count of entries in Arg3
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* Arg3 - A Buffer containing a list of DWORD capabilities
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*
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* _OSC ASL Return Value:
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* A Buffer containing a list of capabilities
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*
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* Local Variables Assignment:
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* Local0 - Temp assigned
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* Local1 - Temp assigned
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* Local2 - Not used
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* Local3 - Not used
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* Local4 - Not used
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* Local5 - Not used
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* Local6 - Record whether the UUID is handled
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* Local7 - Backs up the input value of Arg3
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*
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* Field Definitions:
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* Name - Width Source Offset Description
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* --------------------------------
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* QSUP - DWord Local7 0x00 Query support
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* RETE - DWord Arg3 0x00 Returned errors
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* SUPP - Dword Arg3 0x04 PCIe Features that OS supported
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* CTRL - Dword Arg3 0x08 PCIe Features that firmware grant control to OS
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* OTRL - Dword Local7 0x08 PCIe Features that OS requests for control
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* SUPC - Dword Arg3 0x0C CXL Features that OS supported
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* CTRC - Dword Arg3 0x10 CXL Features that firmware grant control to OS
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* OTRC - Dword Local7 0x10 CXL Features that OS requests for control
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*/
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void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain)
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{
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/*
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* Method (_OSC, 4, NotSerialized)
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* {
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*/
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acpigen_write_method("_OSC", 4);
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/*
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* //
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* // Check revision ID
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* //
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* If (Arg1 != 1)
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* {
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* RETE = OSC_RET_UNRECOGNIZED_REV
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* Return (Arg3)
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* }
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*/
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acpigen_write_if();
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acpigen_emit_byte(LNOT_OP);
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_byte(ARG1_OP);
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acpigen_write_integer(0x1);
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acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_REV, "RETE");
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acpigen_write_return_op(ARG3_OP);
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acpigen_write_if_end();
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/*
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* //
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* // Setup up local variables
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* //
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* Local7 = Arg3
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* CreateDwordField (Local7, 0x00, QSUP)
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* CreateDWordField (Arg3, 0x00, RETE)
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* RETE = 0x0
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* Local6 = ASL_UUID_UNHANDLED
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*/
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acpigen_write_store_ops(ARG3_OP, LOCAL7_OP);
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acpigen_write_create_dword_field(LOCAL7_OP, 0x00, "QSUP");
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acpigen_write_create_dword_field(ARG3_OP, 0x00, "RETE");
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acpigen_write_store_int_to_namestr(0x0, "RETE");
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acpigen_write_store_int_to_op(ASL_UUID_UNHANDLED, LOCAL6_OP);
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/*
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* //
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* // Refer to CXL-3.1-Specification, 9.18.2
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* // A CXL Host Bridge also originates a PCIe hierarchy and will have a
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* // _CID of EISAID("PNP0A08"). As such, a CXL Host Bridge device may expose
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* // both CXL _OSC and PCIe _OSC.
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* //
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*
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* If (Arg0 == ToUUID (PCI_HOST_BRIDGE_OSC_UUID))
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* {
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* //
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* // Handle PCIe _OSC request
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* // Mark UUID handled
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* //
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* }
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*/
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acpigen_write_if();
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_byte(ARG0_OP);
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acpigen_write_uuid(PCI_HOST_BRIDGE_OSC_UUID);
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acpigen_OSC_handle_pcie_request(domain);
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acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP);
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acpigen_write_if_end();
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if (is_cxl_domain) {
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/*
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* If (Arg0 == ToUUID (CXL_HOST_BRIDGE_OSC_UUID))
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* {
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* //
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* // Handle CXL _OSC request
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* // Mark UUID handled
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* //
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* }
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*/
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acpigen_write_if();
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_byte(ARG0_OP);
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acpigen_write_uuid(CXL_HOST_BRIDGE_OSC_UUID);
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acpigen_OSC_handle_cxl_request(domain);
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acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP);
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acpigen_write_if_end();
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}
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/*
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* //
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* // Handle unrecognized UUID
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* //
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* If (Local6 == ASL_UUID_UNHANDLED)
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* {
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* RETE = OSC_RET_UNRECOGNIZED_UUID
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* }
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*/
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acpigen_write_if_lequal_op_int(LOCAL6_OP, ASL_UUID_UNHANDLED);
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acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_UUID, "RETE");
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acpigen_write_if_end();
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/*
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* //
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* // All done, return
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* //
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* Return (Arg3)
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*/
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acpigen_write_return_op(ARG3_OP);
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/*
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* } // Method (_OSC, 4, NotSerialized)
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*/
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acpigen_pop_len();
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}
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void acpigen_OSC_handle_pcie_request(const struct device *domain)
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{
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uint32_t osc_features = soc_get_granted_pci_features(domain);
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/*
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* If (Arg2 < 2))
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* {
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* RETE = OSC_RET_FAILURE
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* Return (Arg3)
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* }
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*/
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acpigen_write_if();
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acpigen_emit_byte(LLESS_OP);
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acpigen_emit_byte(ARG2_OP);
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acpigen_write_integer(0x2);
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acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE");
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acpigen_write_return_op(ARG3_OP);
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acpigen_write_if_end();
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/*
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* CreateDWordField (Arg3, 0x04, SUPP)
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* CreateDWordField (Arg3, 0x08, CTRL)
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* CreateDWordField (Local7, 0x08, OTRL)
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*/
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acpigen_write_create_dword_field(ARG3_OP, 0x04, "SUPP");
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acpigen_write_create_dword_field(ARG3_OP, 0x08, "CTRL");
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acpigen_write_create_dword_field(LOCAL7_OP, 0x08, "OTRL");
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/*
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* // Grant PCIe feature controls to OS
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* CTRL &= osc_features
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*/
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acpigen_write_to_integer_from_namestring("CTRL", LOCAL0_OP);
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acpigen_write_store_int_to_op(osc_features, LOCAL1_OP);
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acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP);
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acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRL");
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/*
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* If (CTRL != OTRL)
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* {
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* RETE = OSC_RET_CAPABILITIES_MASKED
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* }
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*/
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acpigen_write_if();
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acpigen_emit_byte(LNOT_OP);
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_namestring("CTRL");
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acpigen_emit_namestring("OTRL");
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acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE");
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acpigen_write_if_end();
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};
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void acpigen_OSC_handle_cxl_request(const struct device *domain)
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{
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uint32_t osc_features = soc_get_granted_cxl_features(domain);
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/*
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* If (Arg2 < 4))
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* {
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* RETE = OSC_RET_FAILURE
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* Return (Arg3)
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* }
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*/
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acpigen_write_if();
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acpigen_emit_byte(LLESS_OP);
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acpigen_emit_byte(ARG2_OP);
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acpigen_write_integer(0x4);
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acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE");
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acpigen_write_return_op(ARG3_OP);
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acpigen_write_if_end();
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/*
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* CreateDWordField (Arg3, 0x0C, SUPC)
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* CreateDWordField (Arg3, 0x10, CTRC)
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* CreateDWordField (Local7, 0x10, OTRC)
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*/
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acpigen_write_create_dword_field(ARG3_OP, 0x0C, "SUPC");
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acpigen_write_create_dword_field(ARG3_OP, 0x10, "CTRC");
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acpigen_write_create_dword_field(LOCAL7_OP, 0x10, "OTRC");
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/*
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* // Grant CXL feature controls to OS
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* CTRC &= osc_features
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*/
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acpigen_write_to_integer_from_namestring("CTRC", LOCAL0_OP);
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acpigen_write_store_int_to_op(osc_features, LOCAL1_OP);
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acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP);
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acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRC");
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/*
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* If (CTRC != OTRC)
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* {
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* RETE = OSC_RET_CAPABILITIES_MASKED
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* }
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*/
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acpigen_write_if();
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acpigen_emit_byte(LNOT_OP);
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acpigen_emit_byte(LEQUAL_OP);
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acpigen_emit_namestring("CTRC");
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acpigen_emit_namestring("OTRC");
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acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE");
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acpigen_write_if_end();
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};
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__weak uint32_t soc_get_granted_pci_features(const struct device *domain)
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{
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/*
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* By default grant no features to OS, which equals to the case where _OSC
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* is absent.
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*
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* Refer to PCI firmware specification, revision 3.1.
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* If the _OSC control method is absent from the scope of a host bridge device, then
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* the operating system must not enable or attempt to use any features defined in this
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* section for the hierarchy originated by the host bridge. Doing so could contend with
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* platform firmware operations or produce undesired results.
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*/
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return 0;
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}
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__weak uint32_t soc_get_granted_cxl_features(const struct device *domain)
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{
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/*
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* By default grant no features to OS, which equals to the case where _OSC
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* is absent.
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*/
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return 0;
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}
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@ -7,6 +7,13 @@
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#include <device/pci_def.h>
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#include <device/pci_type.h>
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#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01
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#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02
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#define PCIE_PME_CONTROL 0x04
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#define PCIE_AER_CONTROL 0x08
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#define PCIE_CAP_STRUCTURE_CONTROL 0x10
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#define PCIE_LTR_CONTROL 0x20
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void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn);
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void acpigen_write_ADR_pci_device(const struct device *dev);
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@ -16,4 +23,8 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin,
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void pci_domain_fill_ssdt(const struct device *domain);
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void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain);
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uint32_t soc_get_granted_pci_features(const struct device *domain);
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uint32_t soc_get_granted_cxl_features(const struct device *domain);
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#endif /* ACPIGEN_PCI_H */
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