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soc/intel/cannonlake: Add PCIe RP 17-24 ACPI information

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Change-Id: I119b9cd6dbaa8f2d17d6132dbd9d44a778ff8111
This commit is contained in:
Jeremy Soller 2020-08-20 14:06:21 -06:00
parent 4f1c9f486a
commit f6268a00d4
No known key found for this signature in database
GPG Key ID: E988B49EE78A7FB1
2 changed files with 150 additions and 4 deletions
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10
src/soc/intel/cannonlake/acpi/pci_irqs.asl
View File

@ -24,6 +24,11 @@ Name (PICP, Package () {
Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
/* PCI Express Port 17-24 */
Package(){0x001BFFFF, 0, 0, PCIE_1_IRQ },
Package(){0x001BFFFF, 1, 0, PCIE_2_IRQ },
Package(){0x001BFFFF, 2, 0, PCIE_3_IRQ },
Package(){0x001BFFFF, 3, 0, PCIE_4_IRQ },
/* eMMC */
Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
/* SerialIo */
@ -88,6 +93,11 @@ Name (PICN, Package () {
Package () { 0x001CFFFF, 1, 0, 10 },
Package () { 0x001CFFFF, 2, 0, 11 },
Package () { 0x001CFFFF, 3, 0, 11 },
/* D27: PCI Express Port 17-24 */
Package () { 0x001BFFFF, 0, 0, 11 },
Package () { 0x001BFFFF, 1, 0, 10 },
Package () { 0x001BFFFF, 2, 0, 11 },
Package () { 0x001BFFFF, 3, 0, 11 },
/* D25: Can't use PIC*/
/* D23 */
Package () { 0x0017FFFF, 0, 0, 11 },

144
src/soc/intel/cannonlake/acpi/pcie.asl
View File

@ -54,7 +54,7 @@ Method (IRQM, 1, Serialized) {
Switch (ToInteger (Arg0))
{
Case (Package () { 1, 5, 9, 13 }) {
Case (Package () { 1, 5, 9, 13, 17, 21 }) {
If (PICM) {
Return (IQAA)
} Else {
@ -62,7 +62,7 @@ Method (IRQM, 1, Serialized) {
}
}
Case (Package () { 2, 6, 10, 14 }) {
Case (Package () { 2, 6, 10, 14, 18, 22 }) {
If (PICM) {
Return (IQBA)
} Else {
@ -70,7 +70,7 @@ Method (IRQM, 1, Serialized) {
}
}
Case (Package () { 3, 7, 11, 15 }) {
Case (Package () { 3, 7, 11, 15, 19, 23 }) {
If (PICM) {
Return (IQCA)
} Else {
@ -78,7 +78,7 @@ Method (IRQM, 1, Serialized) {
}
}
Case (Package () { 4, 8, 12, 16 }) {
Case (Package () { 4, 8, 12, 16, 20, 24 }) {
If (PICM) {
Return (IQDA)
} Else {
@ -367,3 +367,139 @@ Device (RP16)
Return (IRQM (RPPN))
}
}
Device (RP17)
{
Name (_ADR, 0x001B0000)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP18)
{
Name (_ADR, 0x001B0001)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP19)
{
Name (_ADR, 0x001B0002)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP20)
{
Name (_ADR, 0x001B0003)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP21)
{
Name (_ADR, 0x001B0004)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP22)
{
Name (_ADR, 0x001B0005)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP23)
{
Name (_ADR, 0x001B0006)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP24)
{
Name (_ADR, 0x001B0007)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}