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soc/intel/fsp_broadwell_de: Drop support

Browse Source 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I8b6502b0894f9e2b8b1334871d7b6cde65cba7d4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Arthur Heymans 2019-11-19 18:50:20 +01:00 committed by Kyösti Mälkki
parent 433471244b
commit f67c81fc70
52 changed files with 1 additions and 6218 deletions
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4
src/security/intel/txt/Kconfig
View File

@ -22,7 +22,7 @@ config INTEL_TXT
depends on (TPM1 || TPM2)
depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE
depends on PLATFORM_HAS_DRAM_CLEAR
depends on SOC_INTEL_FSP_BROADWELL_DE || SOC_INTEL_COMMON_BLOCK_SA
depends on SOC_INTEL_COMMON_BLOCK_SA
if INTEL_TXT
@ -30,7 +30,6 @@ menu "Intel"
config INTEL_TXT_BIOSACM_FILE
string "BIOS ACM file"
default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE
default "3rdparty/blobs/soc/intel/skylake/biosacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE
help
Intel TXT BIOS ACM file. This file can be obtained by privileged
@ -39,7 +38,6 @@ config INTEL_TXT_BIOSACM_FILE
config INTEL_TXT_SINITACM_FILE
string "SINIT ACM file"
default "3rdparty/blobs/soc/intel/fsp_broadwell_de/sinitacm.bin" if SOC_INTEL_FSP_BROADWELL_DE
default "3rdparty/blobs/soc/intel/skylake/sinitacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE
help
Intel TXT SINIT ACM file. This file can be obtained by privileged

100
src/soc/intel/fsp_broadwell_de/Kconfig
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@ -1,100 +0,0 @@
config SOC_INTEL_FSP_BROADWELL_DE
bool
help
Broadwell-DE support using the Intel FSP.
if SOC_INTEL_FSP_BROADWELL_DE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_RESET
select SOUTHBRIDGE_INTEL_COMMON_RTC
select PARALLEL_MP
select SMP
select IOAPIC
select SSE2
select UDELAY_TSC
select SUPPORT_CPU_UCODE_IN_CBFS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select TSC_MONOTONIC_TIMER
select HAVE_FSP_BIN
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_IMC
select BOOT_DEVICE_SUPPORTS_WRITES
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config CBFS_SIZE
hex
default 0x200000
config HEAP_SIZE
hex
default 0x100000
config BOOTBLOCK_CPU_INIT
string
default "soc/intel/fsp_broadwell_de/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS
hex
default 0x80000000
config MAX_CPUS
int
default 32
config CPU_ADDR_BITS
int
default 36
config VGA_BIOS
bool
default n
config IED_REGION_SIZE
hex
default 0x400000
config SMM_RESERVED_SIZE
hex
default 0x100000
config INTEGRATED_UART
bool "Integrated UART ports"
default y
select DRIVERS_UART_8250IO
select CONSOLE_SERIAL
help
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
config SERIRQ_CONTINUOUS_MODE
bool
default n
help
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
config DIMM_SPD_SIZE
int
default 512
config HPET_MIN_TICKS
hex
default 0x80
## Broadwell-DE Specific FSP Kconfig
source src/soc/intel/fsp_broadwell_de/fsp/Kconfig
endif # SOC_INTEL_FSP_BROADWELL_DE

51
src/soc/intel/fsp_broadwell_de/Makefile.inc
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@ -1,51 +0,0 @@
ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y)
subdirs-y += fsp
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/cache
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
subdirs-y += ../../../lib/fsp
romstage-y += gpio.c
romstage-y += memmap.c
romstage-y += tsc_freq.c
romstage-y += smbus-imc.c
romstage-y += ubox.c
romstage-y += vtd.c
postcar-y += tsc_freq.c
ramstage-y += acpi.c
ramstage-y += chip.c
ramstage-y += cpu.c
ramstage-y += gpio.c
ramstage-y += iou_complto.c
ramstage-y += memmap.c
ramstage-y += northcluster.c
ramstage-y += ramstage.c
ramstage-y += smbus.c
ramstage-y += smbus_common.c
ramstage-y += smi.c
ramstage-y += southcluster.c
ramstage-y += tsc_freq.c
ramstage-y += vtd.c
ramstage-y += ubox.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += tsc_freq.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-56-*)
CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/include
CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/fsp
CPPFLAGS_common += -I$(src)/soc/intel/fsp_broadwell_de/
endif # ifeq ($(CONFIG_SOC_INTEL_FSP_BROADWELL_DE),y)

549
src/soc/intel/fsp_broadwell_de/acpi.c
View File

@ -1,549 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2016-2018 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <types.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <soc/acpi.h>
#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/lpc.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/pci_devs.h>
#include <soc/broadwell_de.h>
#include <version.h>
#include "chip.h"
uint16_t get_pmbase(void)
{
return ACPI_BASE_ADDRESS;
}
#define MWAIT_RES(state, sub_state) \
{ \
.addrl = (((state) << 4) | (sub_state)), \
.space_id = ACPI_ADDRESS_SPACE_FIXED, \
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
}
/* C-state map */
static acpi_cstate_t cstate_map[] = {
{
/* C1 */
.ctype = 1, /* ACPI C1 */
.latency = 1,
.power = 1000,
.resource = MWAIT_RES(0, 0),
},
{
/* C3 */
.ctype = 2, /* ACPI C2 */
.latency = 15,
.power = 500,
.resource = MWAIT_RES(1, 0),
},
{
/* C6 */
.ctype = 3, /* ACPI C3 */
.latency = 41,
.power = 350,
.resource = MWAIT_RES(2, 0),
}
};
static int acpi_sci_irq(void)
{
uint8_t actl = 0;
static uint8_t sci_irq = 0;
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
/* If this function was already called, just return the stored value. */
if (sci_irq)
return sci_irq;
/* Get contents of ACPI control register. */
actl = pci_read_config8(dev, ACPI_CNTL_OFFSET) & SCIS_MASK;
/* Determine how SCI is routed. */
switch (actl) {
case SCIS_IRQ9:
case SCIS_IRQ10:
case SCIS_IRQ11:
sci_irq = actl + 9;
break;
case SCIS_IRQ20:
case SCIS_IRQ21:
case SCIS_IRQ22:
case SCIS_IRQ23:
sci_irq = actl - SCIS_IRQ20 + 20;
break;
default:
printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n");
sci_irq = 9;
break;
}
printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq);
return sci_irq;
}
unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
MCFG_BASE_ADDRESS, 0, 0, 255);
return current;
}
/**
* Fill in the fadt with generic values that can be overridden later.
*/
void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
u16 pmbase = get_pmbase();
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
/*
* Reference section 5.2.9 Fixed ACPI Description Table (FADT)
* in the ACPI 3.0b specification.
*/
/* FADT Header Structure */
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = get_acpi_table_revision(FADT);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = asl_revision;
/* ACPI Pointers */
fadt->firmware_ctrl = (unsigned long) facs;
fadt->dsdt = (unsigned long) dsdt;
fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */
fadt->preferred_pm_profile = 0;
fadt->sci_int = acpi_sci_irq();
/* System Management */
fadt->smi_cmd = 0x00; /* disable SMM */
fadt->acpi_enable = 0x00; /* unused if SMI_CMD = 0 */
fadt->acpi_disable = 0x00; /* unused if SMI_CMD = 0 */
/* Enable ACPI */
outl(inl(pmbase + 4) | 0x01, pmbase + 4);
/* Power Control */
fadt->s4bios_req = 0x00;
fadt->pstate_cnt = 0x00;
/* Control Registers - Base Address */
fadt->pm1a_evt_blk = pmbase + PM1_STS;
fadt->pm1b_evt_blk = 0x00; /* Not Used */
fadt->pm1a_cnt_blk = pmbase + PM1_CNT;
fadt->pm1b_cnt_blk = 0x00; /* Not Used */
fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK;
fadt->pm_tmr_blk = pmbase + PM1_TMR;
fadt->gpe0_blk = pmbase + GPE0_STS;
fadt->gpe1_blk = 0x00; /* Not Used */
/* Control Registers - Length */
fadt->pm1_evt_len = 4; /* 32 bits */
fadt->pm1_cnt_len = 2; /* 32 bit register, 16 bits used */
fadt->pm2_cnt_len = 1; /* 8 bits */
fadt->pm_tmr_len = 4; /* 32 bits */
fadt->gpe0_blk_len = 8; /* 64 bits */
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
fadt->cst_cnt = 0;
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1;
fadt->duty_width = 0;
/* RTC Registers */
fadt->day_alrm = 0x0D;
fadt->mon_alrm = 0x00;
fadt->century = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE |
ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
/* Reset Register */
fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->reset_reg.bit_width = 8;
fadt->reset_reg.bit_offset = 0;
fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->reset_reg.addrl = 0xCF9;
fadt->reset_reg.addrh = 0x00;
fadt->reset_value = 6;
fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */
fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */
/* Extended ACPI Pointers */
fadt->x_firmware_ctl_l = (unsigned long)facs;
fadt->x_firmware_ctl_h = 0x00;
fadt->x_dsdt_l = (unsigned long)dsdt;
fadt->x_dsdt_h = 0x00;
/* PM1 Status & PM1 Enable */
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
fadt->x_pm1a_evt_blk.addrh = 0x00;
fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_evt_blk.bit_width = 0;
fadt->x_pm1b_evt_blk.bit_offset = 0;
fadt->x_pm1b_evt_blk.access_size = 0;
fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
fadt->x_pm1b_evt_blk.addrh = 0x00;
/* PM1 Control Registers */
fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
fadt->x_pm1a_cnt_blk.addrh = 0x00;
fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1b_cnt_blk.bit_width = 0;
fadt->x_pm1b_cnt_blk.bit_offset = 0;
fadt->x_pm1b_cnt_blk.access_size = 0;
fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
fadt->x_pm1b_cnt_blk.addrh = 0x00;
/* PM2 Control Registers */
fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm2_cnt_blk.bit_width = 8;
fadt->x_pm2_cnt_blk.bit_offset = 0;
fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
fadt->x_pm2_cnt_blk.addrh = 0x00;
/* PM1 Timer Register */
fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
fadt->x_pm_tmr_blk.addrh = 0x00;
/* General-Purpose Event Registers */
fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
fadt->x_gpe0_blk.addrh = 0x00;
fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_gpe1_blk.bit_width = 0;
fadt->x_gpe1_blk.bit_offset = 0;
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
fadt->x_gpe1_blk.addrh = 0x00;
}
static unsigned long acpi_fill_dmar(unsigned long current)
{
uint32_t vtbar, tmp = current;
struct device *dev = pcidev_path_on_root(IIO_DEVFN_VTD);
uint16_t bdf, hpet_bdf[8];
uint8_t i, j;
if (!dev)
return current;
vtbar = pci_read_config32(dev, VTBAR_OFFSET) & VTBAR_MASK;
if (!vtbar)
return current;
current += acpi_create_dmar_drhd(current,
DRHD_INCLUDE_PCI_ALL, 0, vtbar);
/* The IIO I/O APIC is fixed on PCI 00:05.4 on Broadwell-DE */
current += acpi_create_dmar_ds_ioapic(current,
9, 0, 5, 4);
/* Get the PCI BDF for the PCH I/O APIC */
dev = pcidev_path_on_root(PCH_DEVFN_LPC);
bdf = pci_read_config16(dev, 0x6c);
current += acpi_create_dmar_ds_ioapic(current,
8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf));
/*
* Check if there are different PCI paths for the 8 HPET timers
* and add every different PCI path as a separate HPET entry.
* Although the DMAR specification talks about HPET block for this
* entry, it is possible to assign a unique PCI BDF to every single
* timer within a HPET block which will result in different source
* IDs reported by a generated MSI.
* In default configuration every single timer will have the same
* PCI BDF which will result in a single HPET entry in DMAR table.
* I have checked several different systems and all of them had one
* single entry for HPET in DMAR.
*/
memset(hpet_bdf, 0, sizeof(hpet_bdf));
/* Get all unique HPET paths. */
for (i = 0; i < ARRAY_SIZE(hpet_bdf); i++) {
bdf = pci_read_config16(dev, 0x70 + (i * 2));
for (j = 0; j < i; j++) {
if (hpet_bdf[j] == bdf)
break;
}
if (j == i)
hpet_bdf[i] = bdf;
}
/* Create one HPET entry in DMAR for every unique HPET PCI path. */
for (i = 0; i < ARRAY_SIZE(hpet_bdf); i++) {
if (hpet_bdf[i])
current += acpi_create_dmar_ds_msi_hpet(current,
0, (hpet_bdf[i] >> 8), PCI_SLOT(hpet_bdf[i]),
PCI_FUNC(hpet_bdf[i]));
}
acpi_dmar_drhd_fixup(tmp, current);
/* Create root port ATSR capability */
tmp = current;
current += acpi_create_dmar_atsr(current, 0, 0);
/* Add one entry to ATSR for each PCI root port */
dev = all_devices;
do {
dev = dev_find_class(PCI_CLASS_BRIDGE_PCI << 8, dev);
if (dev && dev->bus->secondary == 0 &&
PCI_SLOT(dev->path.pci.devfn) <= 3)
current += acpi_create_dmar_ds_pci_br(current,
dev->bus->secondary,
PCI_SLOT(dev->path.pci.devfn),
PCI_FUNC(dev->path.pci.devfn));
} while (dev);
acpi_dmar_atsr_fixup(tmp, current);
return current;
}
unsigned long vtd_write_acpi_tables(struct device *const dev,
unsigned long current,
struct acpi_rsdp *const rsdp)
{
acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
/* Create DMAR table only if virtualization is enabled */
if (!(pci_read_config32(dev, VTBAR_OFFSET) & VTBAR_ENABLED))
return current;
printk(BIOS_DEBUG, "ACPI: * DMAR\n");
acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
current += dmar->header.length;
current = acpi_align_current(current);
acpi_add_table(rsdp, dmar);
current = acpi_align_current(current);
return current;
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
{
u32 m;
u32 power;
/*
* M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
*
* Power = (ratio / p1_ratio) * m * tdp
*/
m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
m = (m * m) / 1000;
power = ((ratio * 100000 / p1_ratio) / 100);
power *= (m / 100) * (tdp / 1000);
power /= 1000;
return (int)power;
}
static void generate_P_state_entries(int core, int cores_per_package)
{
int ratio_min, ratio_max, ratio_step;
int coord_type, power_max, power_unit, num_entries;
int ratio, power, clock;
int turbo;
u32 control_status;
msr_t msr;
/* Hardware coordination of P-states */
coord_type = HW_ALL;
/* Check for Turbo Mode */
turbo = get_turbo_state() == TURBO_ENABLED;
/* CPU attributes */
msr = rdmsr(MSR_PLATFORM_INFO);
ratio_min = (msr.hi >> 8) & 0xff; // LFM
ratio_max = (msr.lo >> 8) & 0xff; // HFM
/* Calculate CPU TDP in mW */
msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
power_unit = 1 << (msr.lo & 0xf);
msr = rdmsr(MSR_PKG_POWER_LIMIT);
power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
/* Write _PCT indicating use of FFixedHW */
acpigen_write_empty_PCT();
/* Write _PPC starting from first supported P-state */
acpigen_write_PPC(0);
/* Write PSD indicating configured coordination type */
acpigen_write_PSD_package(core, 1, coord_type);
/* Add P-state entries in _PSS table */
acpigen_write_name("_PSS");
/* Determine ratio points */
/* Note: There should be at most 16 performance states. If Turbo Mode
is enabled, the Max Turbo Ratio will occupy one of these states. */
ratio_step = 1;
num_entries = (ratio_max - ratio_min) / ratio_step;
while (num_entries > (15-turbo)) {
ratio_step <<= 1;
num_entries >>= 1;
}
if (turbo) {
/* _PSS package count (with turbo) */
acpigen_write_package(num_entries + 2);
/* Get Max Turbo Ratio */
msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
ratio = msr.lo & 0xff;
acpigen_write_PSS_package(
ratio * 100, /* MHz */
power_max, /* mW */
10, /* lat1 */
10, /* lat2 */
ratio << 8, /* control */
ratio << 8); /* status */
} else {
/* _PSS package count (without turbo) */
acpigen_write_package(num_entries + 1);
}
/* Generate the _PSS entries */
for (ratio = ratio_min + (num_entries * ratio_step);
ratio >= ratio_min; ratio -= ratio_step) {
/* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * 100;
control_status = ratio << 8;
acpigen_write_PSS_package(
clock, /* MHz */
power, /* mW */
10, /* lat1 */
10, /* lat2 */
control_status, /* control */
control_status); /* status */
}
/* Fix package length */
acpigen_pop_len();
}
void generate_cpu_entries(struct device *device)
{
int core;
int pcontrol_blk = get_pmbase(), plen = 6;
const struct pattrs *pattrs = pattrs_get();
for (core = 0; core < pattrs->num_cpus; core++) {
if (core > 0) {
pcontrol_blk = 0;
plen = 0;
}
/* Generate processor \_PR.CP0x */
acpigen_write_processor(core, pcontrol_blk, plen);
/* Generate P-state tables */
generate_P_state_entries(core, pattrs->num_cpus);
/* Generate C-state tables */
acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map));
acpigen_pop_len();
}
}
unsigned long acpi_madt_irq_overrides(unsigned long current)
{
int sci_irq = acpi_sci_irq();
acpi_madt_irqoverride_t *irqovr;
uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
/* INT_SRC_OVR */
irqovr = (void *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
if (sci_irq >= 20)
sci_flags |= MP_IRQ_POLARITY_LOW;
else
sci_flags |= MP_IRQ_POLARITY_HIGH;
irqovr = (void *)current;
current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
sci_flags);
return current;
}
unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long current,
acpi_rsdp_t *rsdp)
{
current = acpi_write_hpet(device, current, rsdp);
current = acpi_align_current(current);
printk(BIOS_DEBUG, "current = %lx\n", current);
return current;
}

464
src/soc/intel/fsp_broadwell_de/acpi/irqlinks.asl
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@ -1,464 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
OperationRegion (PRR0, PCI_Config, 0x00, 0x100)
Field (PRR0, AnyAcc, NoLock, Preserve) {
Offset(0x60),
PIRA, 8,
PIRB, 8,
PIRC, 8,
PIRD, 8,
Offset(0x68),
PIRE, 8,
PIRF, 8,
PIRG, 8,
PIRH, 8
}
Device (LNKA) { // PCI IRQ link A
Name (_HID,EISAID("PNP0C0F"))
//Name(_UID, 1)
Method (_STA,0,NotSerialized) {
If(And(PIRA, 0x80)) {
Return (0x9)
} Else {
Return (0xB)
} // Don't display
}
Method (_DIS,0,NotSerialized) {
Or (PIRA, 0x80, PIRA)
}
Method (_CRS,0,Serialized) {
Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And(PIRA, 0x80)) {
Store (Zero, Local0)
} Else {
Store (One,Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer
Return (BUF0) // Return Buf0
} // End of _CRS method
Name (_PRS, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual (IRQW,Zero)){
And (Local0, 0x7F,Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80,Local0)
}
Store (Local0, PIRA)
} // End of _SRS Method
}
Device(LNKB) { // PCI IRQ link B
Name (_HID,EISAID("PNP0C0F"))
//Name(_UID, 2)
Method (_STA,0,NotSerialized) {
If (And (PIRB, 0x80)) {
Return (0x9)
} Else {
Return (0xB)
} // Don't display
}
Method (_DIS,0,NotSerialized) {
Or (PIRB, 0x80,PIRB)
}
Method (_CRS,0,Serialized) {
Name(BUF0, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And (PIRB, 0x80)) {
Store (Zero, Local0)
} Else {
Store (One,Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer
Return (BUF0) // Return Buf0
} // End of _CRS method
Name (_PRS,
ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual(IRQW,Zero)) {
And (Local0, 0x7F, Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80, Local0)
}
Store (Local0, PIRB)
} // End of _SRS Method
}
Device(LNKC) { // PCI IRQ link C
Name(_HID, EISAID("PNP0C0F"))
//Name(_UID, 3)
Method (_STA,0,NotSerialized) {
If (And (PIRC, 0x80)) {
Return (0x9)
} Else {
Return (0xB)
} // Don't display
}
Method (_DIS, 0, NotSerialized) {
Or (PIRC, 0x80, PIRC)
}
Method (_CRS, 0, Serialized) {
Name (BUF0, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And (PIRC, 0x80)) {
Store (Zero, Local0)
} Else {
Store (One,Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0,And (PIRC,0x0F),IRQW)
Return (BUF0)
} // End of _CRS method
Name (_PRS, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual (IRQW,Zero)) {
And (Local0, 0x7F, Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80,Local0)
}
Store (Local0, PIRC)
} // End of _SRS Method
}
Device (LNKD) { // PCI IRQ link D
Name (_HID,EISAID ("PNP0C0F"))
//Name(_UID, 4)
Method (_STA, 0, NotSerialized) {
If (And (PIRD, 0x80)) {
Return (0x9)
} Else {
Return (0xB)
} // Don't display
}
Method (_DIS, 0, NotSerialized) {
Or(PIRD, 0x80,PIRD)
}
Method (_CRS,0,Serialized) {
Name (BUF0, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And (PIRD, 0x80)) {
Store (Zero, Local0)
} Else {
Store (One,Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0, And (PIRD,0x0F), IRQW)
Return (BUF0) // Return Buf0
} // End of _CRS method
Name (_PRS, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit (IRQW, Local0)// Set IRQ
If (LNotEqual (IRQW, Zero)) {
And (Local0, 0x7F, Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80, Local0)
}
Store(Local0, PIRD)
} // End of _SRS Method
}
Device(LNKE) { // PCI IRQ link E
Name(_HID,EISAID("PNP0C0F"))
//Name(_UID, 5)
Method (_STA,0,NotSerialized) {
If (And (PIRE, 0x80)) {
Return(0x9)
} Else {
Return(0xB)
} // Don't display
}
Method (_DIS,0,NotSerialized) {
Or (PIRE, 0x80, PIRE)
}
Method (_CRS, 0, Serialized) {
Name (BUF0, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And (PIRE, 0x80)) {
Store (Zero, Local0)
} Else {
Store (One, Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0, And (PIRE,0x0F), IRQW)
Return (BUF0) // Return Buf0
} // End of _CRS method
Name(_PRS, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit (IRQW, Local0) // Set IRQ
If (LNotEqual (IRQW, Zero)) {
And (Local0, 0x7F, Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80, Local0)
}
Store (Local0, PIRE)
} // End of _SRS Method
}
Device(LNKF) { // PCI IRQ link F
Name (_HID,EISAID("PNP0C0F"))
//Name(_UID, 6)
Method (_STA,0,NotSerialized) {
If (And (PIRF, 0x80)) {
Return (0x9)
} Else {
Return (0xB)
} // Don't display
}
Method (_DIS,0,NotSerialized) {
Or (PIRB, 0x80, PIRF)
}
Method (_CRS,0,Serialized) {
Name(BUF0, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And (PIRF, 0x80)) {
Store (Zero, Local0)
} Else {
Store (One, Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0, And (PIRF, 0x0F),IRQW)
Return (BUF0)
} // End of _CRS method
Name(_PRS, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit (IRQW,Local0) // Set IRQ
If (LNotEqual (IRQW,Zero)) {
And (Local0, 0x7F,Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80, Local0)
}
Store (Local0, PIRF)
} // End of _SRS Method
}
Device(LNKG) { // PCI IRQ link G
Name(_HID,EISAID("PNP0C0F"))
//Name(_UID, 7)
Method(_STA,0,NotSerialized) {
If (And (PIRG, 0x80)) {
Return (0x9)
} Else {
Return (0xB)
} // Don't display
}
Method (_DIS, 0, NotSerialized) {
Or(PIRG, 0x80,PIRG)
}
Method (_CRS,0,Serialized){
Name(BUF0,ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And(PIRG, 0x80)) {
Store(Zero, Local0)
} Else {
Store(One,Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0,And(PIRG,0x0F),IRQW)
Return (BUF0)
} // End of _CRS method
Name (_PRS, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit(IRQW,Local0) // Set IRQ
If (LNotEqual (IRQW,Zero)) {
And (Local0, 0x7F,Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80,Local0)
}
Store (Local0, PIRG)
} // End of _SRS Method
}
Device(LNKH) { // PCI IRQ link H
Name (_HID,EISAID("PNP0C0F"))
//Name(_UID, 8)
Method (_STA,0,NotSerialized) {
If (And(PIRH, 0x80)) {
Return(0x9)
} Else {
Return(0xB)
} // Don't display
}
Method (_DIS,0,NotSerialized) {
Or(PIRH, 0x80,PIRH)
}
Method (_CRS,0,Serialized) {
Name(BUF0, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){0}})
//
// Define references to buffer elements
//
CreateWordField (BUF0, 0x01, IRQW) // IRQ low
//
// Write current settings into IRQ descriptor
//
If (And (PIRH, 0x80)) {
Store (Zero, Local0)
} Else {
Store (One,Local0)
}
//
// Shift 1 by value in register 70, Save in buffer
//
ShiftLeft (Local0,And(PIRH,0x0F),IRQW)
Return (BUF0)
} // End of _CRS method
Name(_PRS, ResourceTemplate()
{IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
Method (_SRS,1,NotSerialized) {
CreateWordField (ARG0, 0x01, IRQW) // IRQ low
FindSetRightBit (IRQW,Local0)// Set IRQ
If (LNotEqual (IRQW,Zero)) {
And (Local0, 0x7F,Local0)
Decrement (Local0)
} Else {
Or (Local0, 0x80,Local0)
}
Store (Local0, PIRH)
}
}

92
src/soc/intel/fsp_broadwell_de/acpi/lpc.asl
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@ -1,92 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Intel LPC Bus Device - 0:1f.0 */
Device (LPC0)
{
Name(_ADR, 0x001f0000)
#include "irqlinks.asl"
Device (FWH) // Firmware Hub
{
Name (_HID, EISAID("INT0800"))
Name (_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
})
}
Device (HPET)
{
Name (_HID, EISAID("PNP0103"))
Name (_CID, 0x010CD041)
Method (_STA, 0) // Device Status
{
Return (0xf) // Enable and show device
}
Name(_CRS, ResourceTemplate()
{
Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
})
}
Device(LDRC) // LPC device: Resource consumption
{
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 2)
Name (RBUF, ResourceTemplate()
{
IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status
IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
})
Method (_CRS, 0, NotSerialized)
{
Return (RBUF)
}
}
Device (RTC) // Real Time Clock
{
Name (_HID, EISAID("PNP0B00"))
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
})
}
Device (TIMR) // Intel 8254 timer
{
Name(_HID, EISAID("PNP0100"))
Name(_CRS, ResourceTemplate()
{
IO (Decode16, 0x40, 0x40, 0x01, 0x04)
IO (Decode16, 0x50, 0x50, 0x10, 0x04)
IRQNoFlags() {0}
})
}
}

465
src/soc/intel/fsp_broadwell_de/acpi/pcie1.asl
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@ -1,465 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Name (PR01, Package() {
// [SL01]: PCI Express Slot 1 on 1A on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR01, Package() {
// [SL01]: PCI Express Slot 1 on 1A on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH01, Package() {
// [SL01]: PCI Express Slot 1 on 1A on PCI0
Package() { 0x0000FFFF, 0, 0, 26 },
Package() { 0x0000FFFF, 1, 0, 28 },
Package() { 0x0000FFFF, 2, 0, 29 },
Package() { 0x0000FFFF, 3, 0, 30 },
})
Name (PR02, Package() {
// [SL02]: PCI Express Slot 2 on 1B on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR02, Package() {
// [SL02]: PCI Express Slot 2 on 1B on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH02, Package() {
// [SL02]: PCI Express Slot 2 on 1B on PCI0
Package() { 0x0000FFFF, 0, 0, 27 },
Package() { 0x0000FFFF, 1, 0, 30 },
Package() { 0x0000FFFF, 2, 0, 28 },
Package() { 0x0000FFFF, 3, 0, 29 },
})
Name (PR03, Package() {
// [CB0I]: CB3DMA on IOSF
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [CB0J]: CB3DMA on IOSF
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
// [CB0K]: CB3DMA on IOSF
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
// [CB0L]: CB3DMA on IOSF
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR03, Package() {
// [CB0I]: CB3DMA on IOSF
Package() { 0x0000FFFF, 0, 0, 16 },
// [CB0J]: CB3DMA on IOSF
Package() { 0x0000FFFF, 1, 0, 17 },
// [CB0K]: CB3DMA on IOSF
Package() { 0x0000FFFF, 2, 0, 18 },
// [CB0L]: CB3DMA on IOSF
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH03, Package() {
// [CB0I]: CB3DMA on IOSF
Package() { 0x0000FFFF, 0, 0, 32 },
// [CB0J]: CB3DMA on IOSF
Package() { 0x0000FFFF, 1, 0, 36 },
// [CB0K]: CB3DMA on IOSF
Package() { 0x0000FFFF, 2, 0, 37 },
// [CB0L]: CB3DMA on IOSF
Package() { 0x0000FFFF, 3, 0, 38 },
})
Name (PR04, Package() {
// [SL04]: PCI Express Slot 4 on 2B on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR04, Package() {
// [SL04]: PCI Express Slot 4 on 2B on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH04, Package() {
// [SL04]: PCI Express Slot 4 on 2B on PCI0
Package() { 0x0000FFFF, 0, 0, 33 },
Package() { 0x0000FFFF, 1, 0, 37 },
Package() { 0x0000FFFF, 2, 0, 38 },
Package() { 0x0000FFFF, 3, 0, 36 },
})
Name (PR05, Package() {
// [SL05]: PCI Express Slot 5 on 2C on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR05, Package() {
// [SL05]: PCI Express Slot 5 on 2C on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH05, Package() {
// [SL05]: PCI Express Slot 5 on 2C on PCI0
Package() { 0x0000FFFF, 0, 0, 34 },
Package() { 0x0000FFFF, 1, 0, 37 },
Package() { 0x0000FFFF, 2, 0, 36 },
Package() { 0x0000FFFF, 3, 0, 38 },
})
Name (PR06, Package() {
// [SL06]: PCI Express Slot 6 on 2D on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR06, Package() {
// [SL06]: PCI Express Slot 6 on 2D on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH06, Package() {
// [SL06]: PCI Express Slot 6 on 2D on PCI0
Package() { 0x0000FFFF, 0, 0, 35 },
Package() { 0x0000FFFF, 1, 0, 36 },
Package() { 0x0000FFFF, 2, 0, 38 },
Package() { 0x0000FFFF, 3, 0, 37 },
})
Name (PR07, Package() {
// [SL07]: PCI Express Slot 7 on 3A on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR07, Package() {
// [SL07]: PCI Express Slot 7 on 3A on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH07, Package() {
// [SL07]: PCI Express Slot 7 on 3A on PCI0
Package() { 0x0000FFFF, 0, 0, 40 },
Package() { 0x0000FFFF, 1, 0, 44 },
Package() { 0x0000FFFF, 2, 0, 45 },
Package() { 0x0000FFFF, 3, 0, 46 },
})
Name (PR08, Package() {
// [SL08]: PCI Express Slot 8 on 3B on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR08, Package() {
// [SL08]: PCI Express Slot 8 on 3B on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH08, Package() {
// [SL08]: PCI Express Slot 8 on 3B on PCI0
Package() { 0x0000FFFF, 0, 0, 41 },
Package() { 0x0000FFFF, 1, 0, 45 },
Package() { 0x0000FFFF, 2, 0, 46 },
Package() { 0x0000FFFF, 3, 0, 44 },
})
Name (PR09, Package() {
// [SL09]: PCI Express Slot 9 on 3C on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR09, Package() {
// [SL09]: PCI Express Slot 9 on 3C on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH09, Package() {
// [SL09]: PCI Express Slot 9 on 3C on PCI0
Package() { 0x0000FFFF, 0, 0, 42 },
Package() { 0x0000FFFF, 1, 0, 45 },
Package() { 0x0000FFFF, 2, 0, 44 },
Package() { 0x0000FFFF, 3, 0, 46 },
})
Name (PR0A, Package() {
// [SL0A]: PCI Express Slot 10 on 3D on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0000FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0000FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0000FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (AR0A, Package() {
// [SL0A]: PCI Express Slot 10 on 3D on PCI0
Package() { 0x0000FFFF, 0, 0, 16 },
Package() { 0x0000FFFF, 1, 0, 17 },
Package() { 0x0000FFFF, 2, 0, 18 },
Package() { 0x0000FFFF, 3, 0, 19 },
})
Name (AH0A, Package() {
// [SL0A]: PCI Express Slot 10 on 3D on PCI0
Package() { 0x0000FFFF, 0, 0, 43 },
Package() { 0x0000FFFF, 1, 0, 44 },
Package() { 0x0000FFFF, 2, 0, 46 },
Package() { 0x0000FFFF, 3, 0, 45 },
})
// PCI Express Port 1A on PCI0
Device (BR1A) {
Name (_ADR, 0x00010000)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR01)
}
If (LEqual(APC1, One)) {
Return (AH01)
}
Return (AR01)
}
}
// PCI Express Port 1B on PCI0
Device (BR1B) {
Name (_ADR, 0x00010001)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR02)
}
If (LEqual(APC1, One)) {
Return (AH02)
}
Return (AR02)
}
}
// PCI Express Port 2A on PCI0
Device (BR2A) {
Name (_ADR, 0x00020000)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR03)
}
If (LEqual(APC1, One)) {
Return (AH03)
}
Return (AR03)
}
// CB3DMA on IOSF
Device (CB0I) {
Name (_ADR, 0x00000000)
}
// CB3DMA on IOSF
Device (CB0J) {
Name (_ADR, 0x00000001)
}
// CB3DMA on IOSF
Device (CB0K) {
Name (_ADR, 0x00000002)
}
// CB3DMA on IOSF
Device (CB0L) {
Name (_ADR, 0x00000003)
}
}
// PCI Express Port 2B on PCI0
Device (BR2B) {
Name (_ADR, 0x00020001)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR04)
}
If (LEqual(APC1, One)) {
Return (AH04)
}
Return (AR04)
}
}
// PCI Express Port 2C on PCI0
Device (BR2C) {
Name (_ADR, 0x00020002)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR05)
}
If (LEqual(APC1, One)) {
Return (AH05)
}
Return (AR05)
}
}
// PCI Express Port 2D on PCI0
Device (BR2D) {
Name (_ADR, 0x00020003)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR06)
}
If (LEqual(APC1, One)) {
Return (AH06)
}
Return (AR06)
}
}
// PCI Express Port 3A on PCI0
Device (BR3A) {
Name (_ADR, 0x00030000)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR07)
}
If (LEqual(APC1, One)) {
Return (AH07)
}
Return (AR07)
}
}
// PCI Express Port 3B on PCI0
Device (BR3B) {
Name (_ADR, 0x00030001)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR08)
}
If (LEqual(APC1, One)) {
Return (AH08)
}
Return (AR08)
}
}
// PCI Express Port 3C on PCI0
Device (BR3C) {
Name (_ADR, 0x00030002)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR09)
}
If (LEqual(APC1, One)) {
Return (AH09)
}
Return (AR09)
}
}
// PCI Express Port 3D on PCI0
Device (BR3D) {
Name (_ADR, 0x00030003)
Method (_PRW, 0) {
Return (Package (0x02) {0x09, 0x04})
}
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR0A)
}
If (LEqual(APC1, One)) {
Return (AH0A)
}
Return (AR0A)
}
}

349
src/soc/intel/fsp_broadwell_de/acpi/southcluster.asl
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@ -1,349 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/iomap.h>
#include <soc/irq.h>
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
Name(_BBN, 0)
Name (MCRS, ResourceTemplate() {
// Bus Numbers
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00fe, 0x0000, 0xff,,, PB00)
// IO Region 0
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
// PCI Config Space
Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
// IO Region 1
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
0x0000, 0x0d00, 0xefff, 0x0000, 0xE300,,, PI01)
// VGA memory (0xa0000-0xbffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
0x00020000,,, ASEG)
// OPROM reserved (0xc0000-0xc3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
0x00004000,,, OPR0)
// OPROM reserved (0xc4000-0xc7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
0x00004000,,, OPR1)
// OPROM reserved (0xc8000-0xcbfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
0x00004000,,, OPR2)
// OPROM reserved (0xcc000-0xcffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
0x00004000,,, OPR3)
// OPROM reserved (0xd0000-0xd3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
0x00004000,,, OPR4)
// OPROM reserved (0xd4000-0xd7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
0x00004000,,, OPR5)
// OPROM reserved (0xd8000-0xdbfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
0x00004000,,, OPR6)
// OPROM reserved (0xdc000-0xdffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
0x00004000,,, OPR7)
// BIOS Extension (0xe0000-0xe3fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
0x00004000,,, ESG0)
// BIOS Extension (0xe4000-0xe7fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
0x00004000,,, ESG1)
// BIOS Extension (0xe8000-0xebfff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
0x00004000,,, ESG2)
// BIOS Extension (0xec000-0xeffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000ec000, 0x000effff, 0x00000000,
0x00004000,,, ESG3)
// System BIOS (0xf0000-0xfffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-0xfeafffff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x90000000, 0xFEAFFFFF, 0x00000000,
0x6EB00000,,, PMEM)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfec00000, 0xfecfffff, 0x00000000,
0x00100000,,, APIC)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed00000, 0xfedfffff, 0x00000000,
0x00100000,,, PCHR)
QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
0x0000000000000000, // Granularity
0x0000380000000000, // Range Minimum
0x0000383FFFFFFFFF, // Range Maximum
0x0000000000000000, // Translation Offset
0x0000004000000000, // Length
,,, AddressRangeMemory, TypeStatic)
})
Method (_CRS, 0, Serialized) {
Return (MCRS)
}
/* Device Resource Consumption */
Device (PDRC) {
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 1)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, PSEG_BASE_ADDRESS, PSEG_BASE_SIZE)
Memory32Fixed(ReadWrite, IOXAPIC1_BASE_ADDRESS, IOXAPIC1_BASE_SIZE)
Memory32Fixed(ReadWrite, IOXAPIC2_BASE_ADDRESS, IOXAPIC2_BASE_SIZE)
Memory32Fixed(ReadWrite, PCH_BASE_ADDRESS, PCH_BASE_SIZE)
Memory32Fixed(ReadWrite, LXAPIC_BASE_ADDRESS, LXAPIC_BASE_SIZE)
Memory32Fixed(ReadWrite, FIRMWARE_BASE_ADDRESS, FIRMWARE_BASE_SIZE)
})
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Return(PDRS)
}
}
Method (_OSC, 4) {
/* Check for proper GUID */
If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
{
/* Let OS control everything */
Return (Arg3)
}
Else
{
/* Unrecognized UUID */
CreateDWordField (Arg3, 0, CDW1)
Or (CDW1, 4, CDW1)
Return (Arg3)
}
}
Name (PR00, Package() {
// [DMI0]: Legacy PCI Express Port 0 on PCI0
Package() { 0x0000FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [BR1A]: PCI Express Port 1A on PCI0
// [BR1B]: PCI Express Port 1B on PCI0
Package() { 0x0001FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [BR2A]: PCI Express Port 2A on PCI0
// [BR2B]: PCI Express Port 2B on PCI0
// [BR2C]: PCI Express Port 2C on PCI0
// [BR2D]: PCI Express Port 2D on PCI0
Package() { 0x0002FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [BR3A]: PCI Express Port 3A on PCI0
// [BR3B]: PCI Express Port 3B on PCI0
// [BR3C]: PCI Express Port 3C on PCI0
// [BR3D]: PCI Express Port 3D on PCI0
Package() { 0x0003FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [CB0A]: CB3DMA on PCI0
// [CB0E]: CB3DMA on PCI0
Package() { 0x0004FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [CB0B]: CB3DMA on PCI0
// [CB0F]: CB3DMA on PCI0
Package() { 0x0004FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
// [CB0C]: CB3DMA on PCI0
// [CB0G]: CB3DMA on PCI0
Package() { 0x0004FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
// [CB0D]: CB3DMA on PCI0
// [CB0H]: CB3DMA on PCI0
Package() { 0x0004FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
// [IIM0]: IIOMISC on PCI0
Package() { 0x0005FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0005FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0005FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0005FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
// [IID0]: IIODFX0 on PCI0
Package() { 0x0006FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0006FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0006FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0006FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
// [XHCI]: xHCI controller 1 on PCH
Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
// [HECI]: ME HECI on PCH
// [IDER]: ME IDE redirect on PCH
Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [HEC2]: ME HECI2 on PCH
// [MEKT]: MEKT on PCH
Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
// [GBEM]: GbE Controller VPRO
Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKE, 0 },
// [EHC2]: EHCI controller #2 on PCH
Package() { 0x001AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
// [ALZA]: High definition Audio Controller
Package() { 0x001BFFFF, 0, \_SB.PCI0.LPC0.LNKG, 0 },
// [RP01]: Pci Express Port 1 on PCH
// [RP05]: Pci Express Port 5 on PCH
Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [RP02]: Pci Express Port 2 on PCH
// [RP06]: Pci Express Port 6 on PCH
Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
// [RP03]: Pci Express Port 3 on PCH
// [RP07]: Pci Express Port 7 on PCH
Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
// [RP04]: Pci Express Port 4 on PCH
// [RP08]: Pci Express Port 8 on ICH
Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
// [EHC1]: EHCI controller #1 on PCH
Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
// [SAT1]: SATA controller 1 on PCH
// [SAT2]: SATA Host controller 2 on PCH
Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
// [SMBS]: SMBus controller on PCH
// [TERM]: Thermal Subsystem on ICH
Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
})
Name (AR00, Package() {
// [DMI0]: Legacy PCI Express Port 0 on PCI0
Package() { 0x0000FFFF, 0, 0, 47 },
// [BR1A]: PCI Express Port 1A on PCI0
// [BR1B]: PCI Express Port 1B on PCI0
Package() { 0x0001FFFF, 0, 0, 47 },
// [BR2A]: PCI Express Port 2A on PCI0
// [BR2B]: PCI Express Port 2B on PCI0
// [BR2C]: PCI Express Port 2C on PCI0
// [BR2D]: PCI Express Port 2D on PCI0
Package() { 0x0002FFFF, 0, 0, 47 },
// [BR3A]: PCI Express Port 3A on PCI0
// [BR3B]: PCI Express Port 3B on PCI0
// [BR3C]: PCI Express Port 3C on PCI0
// [BR3D]: PCI Express Port 3D on PCI0
Package() { 0x0003FFFF, 0, 0, 47 },
// [CB0A]: CB3DMA on PCI0
// [CB0E]: CB3DMA on PCI0
Package() { 0x0004FFFF, 0, 0, 31 },
// [CB0B]: CB3DMA on PCI0
// [CB0F]: CB3DMA on PCI0
Package() { 0x0004FFFF, 1, 0, 39 },
// [CB0C]: CB3DMA on PCI0
// [CB0G]: CB3DMA on PCI0
Package() { 0x0004FFFF, 2, 0, 31 },
// [CB0D]: CB3DMA on PCI0
// [CB0H]: CB3DMA on PCI0
Package() { 0x0004FFFF, 3, 0, 39 },
// [IIM0]: IIOMISC on PCI0
Package() { 0x0005FFFF, 0, 0, 16 },
Package() { 0x0005FFFF, 1, 0, 17 },
Package() { 0x0005FFFF, 2, 0, 18 },
Package() { 0x0005FFFF, 3, 0, 19 },
// [IID0]: IIODFX0 on PCI0
Package() { 0x0006FFFF, 0, 0, 16 },
Package() { 0x0006FFFF, 1, 0, 17 },
Package() { 0x0006FFFF, 2, 0, 18 },
Package() { 0x0006FFFF, 3, 0, 19 },
// [XHCI]: xHCI controller 1 on PCH
Package() { 0x0014FFFF, 3, 0, 19 },
// [HECI]: ME HECI on PCH
// [IDER]: ME IDE redirect on PCH
Package() { 0x0016FFFF, 0, 0, 16 },
// [HEC2]: ME HECI2 on PCH
// [MEKT]: MEKT on PCH
Package() { 0x0016FFFF, 1, 0, 17 },
// [GBEM]: GbE Controller VPRO
Package() { 0x0019FFFF, 0, 0, 20 },
// [EHC2]: EHCI controller #2 on PCH
Package() { 0x001AFFFF, 2, 0, 18 },
// [ALZA]: High definition Audio Controller
Package() { 0x001BFFFF, 0, 0, 22 },
// [RP01]: Pci Express Port 1 on PCH
// [RP05]: Pci Express Port 5 on PCH
Package() { 0x001CFFFF, 0, 0, 16 },
// [RP02]: Pci Express Port 2 on PCH
// [RP06]: Pci Express Port 6 on PCH
Package() { 0x001CFFFF, 1, 0, 17 },
// [RP03]: Pci Express Port 3 on PCH
// [RP07]: Pci Express Port 7 on PCH
Package() { 0x001CFFFF, 2, 0, 18 },
// [RP04]: Pci Express Port 4 on PCH
// [RP08]: Pci Express Port 8 on ICH
Package() { 0x001CFFFF, 3, 0, 19 },
// [EHC1]: EHCI controller #1 on PCH
Package() { 0x001DFFFF, 2, 0, 18 },
// [SAT1]: SATA controller 1 on PCH
// [SAT2]: SATA Host controller 2 on PCH
Package() { 0x001FFFFF, 0, 0, 16 },
// [SMBS]: SMBus controller on PCH
// [TERM]: Thermal Subsystem on ICH
Package() { 0x001FFFFF, 2, 0, 18 },
})
// Socket 0 Root bridge
Method (_PRT, 0) {
If (LEqual(PICM, Zero)) {
Return (PR00)
}
Return (AR00) // If you disable the IOxAPIC in IIO, you should return AR00
}
#include "lpc.asl"

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src/soc/intel/fsp_broadwell_de/acpi/uncore.asl
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@ -1,267 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Name (PRUN, Package() {
Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 },
Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 },
Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 },
Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 },
})
Name (ARUN, Package() {
Package() { 0x0008FFFF, 0, 0, 16 },
Package() { 0x0008FFFF, 1, 0, 17 },
Package() { 0x0008FFFF, 2, 0, 18 },
Package() { 0x0008FFFF, 3, 0, 19 },
Package() { 0x0009FFFF, 0, 0, 16 },
Package() { 0x0009FFFF, 1, 0, 17 },
Package() { 0x0009FFFF, 2, 0, 18 },
Package() { 0x0009FFFF, 3, 0, 19 },
Package() { 0x000AFFFF, 0, 0, 16 },
Package() { 0x000AFFFF, 1, 0, 17 },
Package() { 0x000AFFFF, 2, 0, 18 },
Package() { 0x000AFFFF, 3, 0, 19 },
Package() { 0x000BFFFF, 0, 0, 16 },
Package() { 0x000BFFFF, 1, 0, 17 },
Package() { 0x000BFFFF, 2, 0, 18 },
Package() { 0x000BFFFF, 3, 0, 19 },
Package() { 0x000CFFFF, 0, 0, 16 },
Package() { 0x000CFFFF, 1, 0, 17 },
Package() { 0x000CFFFF, 2, 0, 18 },
Package() { 0x000CFFFF, 3, 0, 19 },
Package() { 0x000DFFFF, 0, 0, 16 },
Package() { 0x000DFFFF, 1, 0, 17 },
Package() { 0x000DFFFF, 2, 0, 18 },
Package() { 0x000DFFFF, 3, 0, 19 },
Package() { 0x000EFFFF, 0, 0, 16 },
Package() { 0x000EFFFF, 1, 0, 17 },
Package() { 0x000EFFFF, 2, 0, 18 },
Package() { 0x000EFFFF, 3, 0, 19 },
Package() { 0x000FFFFF, 0, 0, 16 },
Package() { 0x000FFFFF, 1, 0, 17 },
Package() { 0x000FFFFF, 2, 0, 18 },
Package() { 0x000FFFFF, 3, 0, 19 },
Package() { 0x0010FFFF, 0, 0, 16 },
Package() { 0x0010FFFF, 1, 0, 17 },
Package() { 0x0010FFFF, 2, 0, 18 },
Package() { 0x0010FFFF, 3, 0, 19 },
Package() { 0x0011FFFF, 0, 0, 16 },
Package() { 0x0011FFFF, 1, 0, 17 },
Package() { 0x0011FFFF, 2, 0, 18 },
Package() { 0x0011FFFF, 3, 0, 19 },
Package() { 0x0012FFFF, 0, 0, 16 },
Package() { 0x0012FFFF, 1, 0, 17 },
Package() { 0x0012FFFF, 2, 0, 18 },
Package() { 0x0012FFFF, 3, 0, 19 },
Package() { 0x0013FFFF, 0, 0, 16 },
Package() { 0x0013FFFF, 1, 0, 17 },
Package() { 0x0013FFFF, 2, 0, 18 },
Package() { 0x0013FFFF, 3, 0, 19 },
Package() { 0x0014FFFF, 0, 0, 16 },
Package() { 0x0014FFFF, 1, 0, 17 },
Package() { 0x0014FFFF, 2, 0, 18 },
Package() { 0x0014FFFF, 3, 0, 19 },
Package() { 0x0016FFFF, 0, 0, 16 },
Package() { 0x0016FFFF, 1, 0, 17 },
Package() { 0x0016FFFF, 2, 0, 18 },
Package() { 0x0016FFFF, 3, 0, 19 },
Package() { 0x0017FFFF, 0, 0, 16 },
Package() { 0x0017FFFF, 1, 0, 17 },
Package() { 0x0017FFFF, 2, 0, 18 },
Package() { 0x0017FFFF, 3, 0, 19 },
Package() { 0x0018FFFF, 0, 0, 16 },
Package() { 0x0018FFFF, 1, 0, 17 },
Package() { 0x0018FFFF, 2, 0, 18 },
Package() { 0x0018FFFF, 3, 0, 19 },
Package() { 0x0019FFFF, 0, 0, 16 },
Package() { 0x0019FFFF, 1, 0, 17 },
Package() { 0x0019FFFF, 2, 0, 18 },
Package() { 0x0019FFFF, 3, 0, 19 },
Package() { 0x001CFFFF, 0, 0, 16 },
Package() { 0x001CFFFF, 1, 0, 17 },
Package() { 0x001CFFFF, 2, 0, 18 },
Package() { 0x001CFFFF, 3, 0, 19 },
Package() { 0x001DFFFF, 0, 0, 16 },
Package() { 0x001DFFFF, 1, 0, 17 },
Package() { 0x001DFFFF, 2, 0, 18 },
Package() { 0x001DFFFF, 3, 0, 19 },
Package() { 0x001EFFFF, 0, 0, 16 },
Package() { 0x001EFFFF, 1, 0, 17 },
Package() { 0x001EFFFF, 2, 0, 18 },
Package() { 0x001EFFFF, 3, 0, 19 },
Package() { 0x001FFFFF, 0, 0, 16 },
Package() { 0x001FFFFF, 1, 0, 17 },
Package() { 0x001FFFFF, 2, 0, 18 },
Package() { 0x001FFFFF, 3, 0, 19 },
})
Device (UNC0)
{
Name (_HID, EisaId ("PNP0A03"))
Name (_UID, 0x3F)
Method (_BBN, 0, NotSerialized)
{
Return (0xff)
}
Name (_ADR, 0x00)
Method (_STA, 0, NotSerialized)
{
Return (0xf)
}
Name (_CRS, ResourceTemplate ()
{
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, // Granularity
0x00FF, // Range Minimum
0x00FF, // Range Maximum
0x0000, // Translation Offset
0x0001, // Length
,, )
})
Method (_PRT, 0, NotSerialized)
{
If (LEqual (PICM, Zero))
{
Return (PRUN)
}
Return (ARUN)
}
}

23
src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c
View File

@ -1,23 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/intel/microcode/microcode.c>
static void bootblock_cpu_init(void)
{
/* Load microcode before any caching. */
intel_update_microcode_from_cbfs();
}

93
src/soc/intel/fsp_broadwell_de/chip.c
View File

@ -1,93 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <bootstate.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include "chip.h"
static void pci_domain_set_resources(struct device *dev)
{
assign_resources(dev->link_list);
}
#if CONFIG(HAVE_ACPI_TABLES)
static const char *domain_acpi_name(const struct device *dev)
{
if (dev->path.type == DEVICE_PATH_DOMAIN)
return "PCI0";
return NULL;
}
#endif
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = domain_acpi_name
#endif
};
static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = broadwell_de_init_cpus,
.scan_bus = NULL,
};
static void enable_dev(struct device *dev)
{
printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
dev_name(dev), dev->path.type);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
} else if (dev->path.type == DEVICE_PATH_PCI) {
/* Handle south cluster enablement. */
if (PCI_SLOT(dev->path.pci.devfn) > 0 &&
(dev->ops == NULL || dev->ops->enable == NULL)) {
southcluster_enable_dev(dev);
}
}
}
/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
static void soc_init(void *chip_info)
{
broadwell_de_init_pre_device();
}
struct chip_operations soc_intel_fsp_broadwell_de_ops = {
CHIP_NAME("Intel(R) Xeon(R) Processor D-1500 Product Family")
.enable_dev = enable_dev,
.init = soc_init,
};
struct pci_operations soc_pci_ops = {
.set_subsystem = &pci_dev_set_subsystem,
};

32
src/soc/intel/fsp_broadwell_de/chip.h
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
#include <arch/acpi.h>
/* The devicetree parser expects chip.h to reside directly in the path
* specified by the devicetree. */
struct soc_intel_fsp_broadwell_de_config {
/* PCIe completion timeout value */
int pcie_compltoval;
};
typedef struct soc_intel_fsp_broadwell_de_config config_t;
#endif /* _SOC_CHIP_H_ */

213
src/soc/intel/fsp_broadwell_de/cpu.c
View File

@ -1,213 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdlib.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/smm_reloc.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include <smbios.h>
#include <soc/broadwell_de.h>
#include <soc/lpc.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/smm.h>
/* MP initialization support. */
static const void *microcode_patch;
static void pre_mp_init(void)
{
x86_mtrr_check();
/* Enable the local CPU apics */
setup_lapic();
}
static int get_cpu_count(void)
{
const struct pattrs *pattrs = pattrs_get();
return pattrs->num_cpus;
}
static void per_cpu_smm_trigger(void)
{
/* Relocate the SMM handler. */
smm_relocate();
/* After SMM relocation a 2nd microcode load is required. */
intel_microcode_load_unlocked(microcode_patch);
}
static void get_microcode_info(const void **microcode, int *parallel)
{
const struct pattrs *pattrs = pattrs_get();
microcode_patch = pattrs->microcode_patch;
*microcode = pattrs->microcode_patch;
*parallel = 1;
}
static int cpu_config_tdp_levels(void)
{
msr_t platform_info;
/* Bits 34:33 indicate how many levels are supported. */
platform_info = rdmsr(MSR_PLATFORM_INFO);
return (platform_info.hi >> 1) & 3;
}
static void set_max_ratio(void)
{
msr_t msr, perf_ctl;
perf_ctl.hi = 0;
/* Check for configurable TDP option. */
if (cpu_config_tdp_levels()) {
/* Set to nominal TDP ratio. */
msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
perf_ctl.lo = (msr.lo & 0xff) << 8;
} else {
/* Platform Info Bits 15:8 give max ratio. */
msr = rdmsr(MSR_PLATFORM_INFO);
perf_ctl.lo = msr.lo & 0xff00;
}
wrmsr(IA32_PERF_CTL, perf_ctl);
}
unsigned int smbios_cpu_get_max_speed_mhz(void)
{
msr_t msr;
uint32_t uncore_max_ratio, turbo_max_ratio = 0;
/*
* Use turbo's max ratio if it is enabled, otherwise use
* uncore's max ratio.
*/
msr = rdmsr(MSR_UNCORE_RATIO_LIMIT);
uncore_max_ratio = msr.lo & 0x7f;
if (get_turbo_state() == TURBO_ENABLED) {
msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
turbo_max_ratio = msr.lo & 0xff; /* 1 core */
}
return MAX(uncore_max_ratio, turbo_max_ratio) * CPU_BCLK;
}
static void alt_smm_lock(void)
{
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
uint16_t smi_lock;
/* There is no register to lock SMRAM region on Broadwell-DE.
Use this function to lock the SMI control bits. */
printk(BIOS_DEBUG, "Locking SMM.\n");
smi_lock = pci_read_config16(dev, GEN_PMCON_1);
smi_lock |= (SMI_LOCK | SMI_LOCK_GP6 | SMI_LOCK_GP22);
pci_write_config16(dev, GEN_PMCON_1, smi_lock);
}
static void post_mp_init(void)
{
/* Set Max Ratio */
set_max_ratio();
/* Now that all APs have been relocated as well as the BSP let SMIs
start flowing. */
smm_southbridge_enable_smi();
/* Set SMI lock bits. */
alt_smm_lock();
}
static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_smm_info = smm_info,
.get_cpu_count = get_cpu_count,
.get_microcode_info = get_microcode_info,
.pre_mp_smm_init = smm_initialize,
.per_cpu_smm_trigger = per_cpu_smm_trigger,
.relocation_handler = smm_relocation_handler,
.post_mp_init = post_mp_init
};
void broadwell_de_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
if (mp_init_with_smm(cpu_bus, &mp_ops)) {
printk(BIOS_ERR, "MP initialization failure.\n");
}
}
static void configure_mca(void)
{
msr_t msr;
int i;
int num_banks;
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & 0xff;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
of these banks are core vs package scope. For now every CPU clears
every bank. */
msr.lo = msr.hi = 0;
for (i = 0; i < num_banks; i++) {
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4) + 1, msr);
wrmsr(IA32_MC0_STATUS + (i * 4) + 2, msr);
}
msr.lo = msr.hi = 0xffffffff;
for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_CTL + (i * 4), msr);
}
static void broadwell_de_core_init(struct device *cpu)
{
printk(BIOS_DEBUG, "Init Broadwell-DE core.\n");
configure_mca();
}
static struct device_operations cpu_dev_ops = {
.init = broadwell_de_core_init,
};
static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, 0x50661 },
{ X86_VENDOR_INTEL, 0x50662 },
{ X86_VENDOR_INTEL, 0x50663 },
{ X86_VENDOR_INTEL, 0x50664 },
{ 0, 0 },
};
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

140
src/soc/intel/fsp_broadwell_de/fsp/Kconfig
View File

@ -1,140 +0,0 @@
config BROADWELL_DE_FSP_SPECIFIC_OPTIONS
def_bool y
select PLATFORM_USES_FSP1_0
select USE_GENERIC_FSP_CAR_INC
select FSP_USES_UPD
config FSP_FILE
string
default "3rdparty/fsp/BroadwellDEFspBinPkg/FspBin/BROADWELLDE_FSP.bin"
help
The path and filename of the Intel FSP binary for this platform.
config FSP_HEADER_PATH
string
default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/"
config FSP_SRC_PATH
string
default "$(top)/3rdparty/fsp/BroadwellDEFspBinPkg/include/fspsupport.c"
config FSP_LOC
hex
default 0xffeb0000
help
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
The Broadwell-DE FSP is built with a preferred base address of
0xffeb0000.
config DCACHE_RAM_BASE
hex
default 0xfe100000
help
This address needs to match the setup performed inside FSP.
On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.
config DCACHE_RAM_SIZE
hex
default 0x8000
help
The DCACHE is shared between FSP itself and the rest of the coreboot
stages. A size of 0x8000 works fine while providing enough space for
features like VBOOT in verstage. Further increase to a power of two
aligned value leads to errors in FSP.
config FSP_MEMORY_DOWN
bool "Enable Memory Down"
default n
help
Load SPD data from ROM instead of trying to read from SMBus.
If the platform has DIMM sockets, say N. If memory is down, say Y and
supply the appropriate SPD data for each Channel/DIMM.
config FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT
bool "Channel 0, DIMM 0 Present"
default n
depends on FSP_MEMORY_DOWN
help
Select Y if Channel 0, DIMM 0 is present.
config FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE
string "Channel 0, DIMM 0 SPD File"
default "spd_ch0_dimm0.bin"
depends on FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT
help
Path to the file which contains the SPD data for Channel 0, DIMM 0.
config FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT
bool "Channel 0, DIMM 1 Present"
default n
depends on FSP_MEMORY_DOWN
help
Select Y if Channel 0, DIMM 1 is present.
config FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE
string "Channel 0, DIMM 1 SPD File"
default "spd_ch0_dimm1.bin"
depends on FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT
help
Path to the file which contains the SPD data for Channel 0, DIMM 1.
config FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT
bool "Channel 1, DIMM 0 Present"
default n
depends on FSP_MEMORY_DOWN
help
Select Y if Channel 1, DIMM 0 is present.
config FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE
string "Channel 1, DIMM 0 SPD File"
default "spd_ch1_dimm0.bin"
depends on FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT
help
Path to the file which contains the SPD data for Channel 1, DIMM 0.
config FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT
bool "Channel 1, DIMM 1 Present"
default n
depends on FSP_MEMORY_DOWN
help
Select Y if Channel 1, DIMM 1 is present.
config FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE
string "Channel 1, DIMM 1 SPD File"
default "spd_ch1_dimm1.bin"
depends on FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT
help
Path to the file which contains the SPD data for Channel 1, DIMM 1.
config FSP_HYPERTHREADING
bool "Enable Hyper-Threading"
default y
help
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
config FSP_EHCI1_ENABLE
bool "EHCI1 Enable"
default n
help
Enable EHCI controller 1
config FSP_EHCI2_ENABLE
bool "EHCI2 Enable"
default n
help
Enable EHCI controller 2
config FSP_DEBUG_LEVEL
int "FSP debug level (0-3)"
default 0
range 0 3
help
Select the debug level, where:
0: DISABLED
1: MINIMUM
2: NORMAL
3: MAXIMUM

17
src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc
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romstage-y += chipset_fsp_util.c
cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT) += spd_ch0_dimm0.bin
spd_ch0_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE))
spd_ch0_dimm0.bin-type := spd
cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT) += spd_ch0_dimm1.bin
spd_ch0_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE))
spd_ch0_dimm1.bin-type := spd
cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT) += spd_ch1_dimm0.bin
spd_ch1_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE))
spd_ch1_dimm0.bin-type := spd
cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT) += spd_ch1_dimm1.bin
spd_ch1_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE))
spd_ch1_dimm1.bin-type := spd

142
src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <string.h>
#include <console/console.h>
#include <bootstate.h>
#include <cbfs.h>
#include <cbmem.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <fsp.h>
#include "../chip.h"
/* Copy the default UPD region and settings to a buffer for modification */
static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
{
VPD_DATA_REGION *VpdDataRgnPtr;
UPD_DATA_REGION *UpdDataRgnPtr;
VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset + FspInfo->ImageBase);
UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
}
typedef struct soc_intel_fsp_broadwell_de_config config_t;
/**
* Update the UPD data based on values from devicetree.cb
*
* @param UpdData Pointer to the UPD Data structure
*/
static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
{
/*
* Serial Port
*/
if (CONFIG(INTEGRATED_UART)) {
UpdData->SerialPortConfigure = 1;
/* values are from FSP .bsf file */
if (CONFIG(CONSOLE_SERIAL_9600))
UpdData->SerialPortBaudRate = 8;
else if (CONFIG(CONSOLE_SERIAL_19200))
UpdData->SerialPortBaudRate = 9;
else if (CONFIG(CONSOLE_SERIAL_38400))
UpdData->SerialPortBaudRate = 10;
else if (CONFIG(CONSOLE_SERIAL_57600))
UpdData->SerialPortBaudRate = 11;
else if (CONFIG(CONSOLE_SERIAL_115200))
UpdData->SerialPortBaudRate = 12;
}
if (!CONFIG(CONSOLE_SERIAL))
UpdData->SerialPortType = 0;
UpdData->DebugOutputLevel = CONFIG_FSP_DEBUG_LEVEL;
/*
* Memory Down
*/
if (CONFIG(FSP_MEMORY_DOWN)) {
UpdData->MemDownEnable = 1;
if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT))
UpdData->MemDownCh0Dimm0SpdPtr
= (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_SPD, NULL);
if (CONFIG(FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT))
UpdData->MemDownCh0Dimm1SpdPtr
= (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_SPD, NULL);
if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT))
UpdData->MemDownCh1Dimm0SpdPtr
= (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_SPD, NULL);
if (CONFIG(FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT))
UpdData->MemDownCh1Dimm1SpdPtr
= (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_SPD, NULL);
} else {
UpdData->MemDownEnable = 0;
}
printk(FSP_INFO_LEVEL, "Memory Down Support: %s\n",
UpdData->MemDownEnable ? "Enabled" : "Disabled");
/*
* Fast Boot
*/
if (CONFIG(ENABLE_MRC_CACHE))
UpdData->MemFastBoot = 1;
else
UpdData->MemFastBoot = 0;
/*
* Hyper-Threading
*/
if (CONFIG(FSP_HYPERTHREADING))
UpdData->HyperThreading = 1;
else
UpdData->HyperThreading = 0;
/* Enable USB */
if (CONFIG(FSP_EHCI1_ENABLE))
UpdData->Ehci1Enable = 1;
else
UpdData->Ehci1Enable = 0;
if (CONFIG(FSP_EHCI2_ENABLE))
UpdData->Ehci2Enable = 1;
else
UpdData->Ehci2Enable = 0;
}
/* Set up the Broadwell-DE specific structures for the call into the FSP */
void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr)
{
FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr;
/* Initialize the UPD Data */
GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr);
pFspInitParams->NvsBufferPtr = NULL;
#if CONFIG(ENABLE_MRC_CACHE)
/* Find the fastboot cache that was saved in the ROM */
pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
#endif
return;
}

35
src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h
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@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2015-2016 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef CHIPSET_FSP_UTIL_H
#define CHIPSET_FSP_UTIL_H
#include <fsp.h>
#define FSP_INFO_HEADER_GUID \
{ \
0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
}
/*
* The FSP Image ID is different for each platform's FSP and
* can be used to verify that the right FSP binary is loaded.
* For the Broadwell-DE FSP, the Image Id is "BDX-DE".
*/
#define FSP_IMAGE_ID_DWORD0 ((unsigned int)(FSP_IMAGE_ID))
#define FSP_IMAGE_ID_DWORD1 ((unsigned int)(FSP_IMAGE_ID >> 32))
#endif /* CHIPSET_FSP_UTIL_H */

109
src/soc/intel/fsp_broadwell_de/gpio.c
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@ -1,109 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <gpio.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
#include <soc/iomap.h>
#include <soc/gpio.h>
/* Use a wrapper for register addresses for different banks. */
const static struct gpio_config_regs regs[GPIO_NUM_BANKS] = {
[0] = { .use_sel = GPIO_1_USE_SEL, .io_sel = GPIO_1_IO_SEL,
.level = GPIO_1_LVL, .nmi_en = GPIO_1_NMI_EN,
.blink_en = GPIO_1_BLINK, .invert_input = GPIO_1_INVERT },
[1] = { .use_sel = GPIO_2_USE_SEL, .io_sel = GPIO_2_IO_SEL,
.level = GPIO_2_LVL, .nmi_en = GPIO_2_NMI_EN,
.blink_en = REG_INVALID, .invert_input = REG_INVALID },
[2] = { .use_sel = GPIO_3_USE_SEL, .io_sel = GPIO_3_IO_SEL,
.level = GPIO_3_LVL, .nmi_en = GPIO_3_NMI_EN,
.blink_en = REG_INVALID, .invert_input = REG_INVALID },
};
#define SETUP_GPIO_REG(reg, bit, bank) { uint32_t val; \
val = inl(GPIO_BASE_ADDRESS + regs[(bank)].reg); \
val &= ~(1 << (bit)); \
val |= ((pin->reg) << (bit)); \
outl(val, GPIO_BASE_ADDRESS + regs[(bank)].reg); }
/* Initialize the GPIOs as defined on mainboard level. */
void init_gpios(const struct gpio_config config[])
{
uint8_t bank, bit;
const struct gpio_config *pin;
if (!config)
return;
/* Set up every GPIO in the table to the requested function. */
for (pin = config; pin->use_sel != GPIO_LIST_END; pin++) {
/* Skip unsupported GPIO numbers. */
if (pin->num > MAX_GPIO_NUM || pin->num == 13)
continue;
bank = pin->num / 32;
bit = pin->num % 32;
if (pin->use_sel == GPIO_MODE_GPIO) {
/* Setting level register first avoids possible short
* pulses on the pin if the output level differs from
* the register default value.
*/
if (pin->io_sel == GPIO_OUTPUT)
SETUP_GPIO_REG(level, bit, bank);
/* Now set the GPIO direction and NMI selection. */
SETUP_GPIO_REG(io_sel, bit, bank);
SETUP_GPIO_REG(nmi_en, bit, bank);
}
/* Now set the pin mode as requested */
SETUP_GPIO_REG(use_sel, bit, bank);
/* The extended functions like inverting and blinking are only
* supported by GPIOs on bank 0.
*/
if (bank)
continue;
/* Blinking is available only for outputs */
if (pin->io_sel == GPIO_OUTPUT)
SETUP_GPIO_REG(blink_en, bit, bank);
/* Inverting is available only for inputs */
if (pin->io_sel == GPIO_INPUT)
SETUP_GPIO_REG(invert_input, bit, bank);
}
}
/* Get GPIO pin value */
int gpio_get(gpio_t gpio)
{
uint8_t bank, bit;
bank = gpio / 32;
bit = gpio % 32;
return (inl(GPIO_BASE_ADDRESS + regs[bank].level) & (1 << bit)) ? 1 : 0;
}
/* Set GPIO pin value */
void gpio_set(gpio_t gpio, int value)
{
uint32_t reg;
uint8_t bank, bit;
bank = gpio / 32;
bit = gpio % 32;
reg = inl(GPIO_BASE_ADDRESS + regs[bank].level);
reg &= ~(1 << bit);
reg |= (!!value << bit);
outl(reg, GPIO_BASE_ADDRESS + regs[bank].level);
}

32
src/soc/intel/fsp_broadwell_de/include/soc/acpi.h
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@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2016-2018 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_ACPI_H_
#define _SOC_ACPI_H_
#include <arch/acpi.h>
void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
uint16_t get_pmbase(void);
unsigned long vtd_write_acpi_tables(struct device *const dev,
unsigned long current,
struct acpi_rsdp *const rsdp);
unsigned long southcluster_write_acpi_tables(struct device *device,
unsigned long start,
acpi_rsdp_t *rsdp);
#endif /* _SOC_ACPI_H_ */

46
src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
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@ -1,46 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017-2018 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_BROADWELL_DE_H_
#define _SOC_BROADWELL_DE_H_
uintptr_t sa_get_tseg_base(void);
size_t sa_get_tseg_size(void);
#define VTBAR_OFFSET 0x180
#define VTBAR_MASK 0xffffe000
#define VTBAR_ENABLED 0x01
#define VTBAR_SIZE 0x2000
#define SMM_FEATURE_CONTROL 0x58
#define SMM_CPU_SAVE_EN (1 << 1)
#define TSEG_BASE 0xa8 /* TSEG base */
#define TSEG_LIMIT 0xac /* TSEG limit */
#define IIO_LTDPR 0x290
#define DPR_LOCK (1 << 0)
#define DPR_EPM (1 << 2)
#define DPR_PRS (1 << 1)
#define DPR_SIZE_MASK 0xff0
#define DPR_SIZE_SHIFT 4
#define DPR_ADDR_MASK 0xfff00000
#define DPR_ADDR_SHIFT 20
/* CPU bus clock is fixed at 100MHz */
#define CPU_BCLK 100
#endif /* _SOC_BROADWELL_DE_H_ */

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src/soc/intel/fsp_broadwell_de/include/soc/gpio.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef FSP_BROADWELL_DE_GPIO_H_
#define FSP_BROADWELL_DE_GPIO_H_
#include <stdint.h>
/* Chipset owned GPIO configuration registers */
#define GPIO_1_USE_SEL 0x00
#define GPIO_1_IO_SEL 0x04
#define GPIO_1_LVL 0x0c
#define GPIO_1_BLINK 0x18
#define GPIO_1_NMI_EN 0x28
#define GPIO_1_INVERT 0x2c
#define GPIO_2_USE_SEL 0x30
#define GPIO_2_IO_SEL 0x34
#define GPIO_2_LVL 0x38
#define GPIO_2_NMI_EN 0x3c
#define GPIO_3_USE_SEL 0x40
#define GPIO_3_IO_SEL 0x44
#define GPIO_3_LVL 0x48
#define GPIO_3_NMI_EN 0x50
#define REG_INVALID 0xff
/* The pin can either be a GPIO or connected to the native function. */
#define GPIO_MODE_NATIVE 0
#define GPIO_MODE_GPIO 1
/* Once configured as GPIO the pin can be an input or an output. */
#define GPIO_OUTPUT 0
#define GPIO_INPUT 1
#define GPIO_NMI_EN 1
/* For output GPIO mode the pin can either drive high or low level. */
#define GPIO_OUT_LEVEL_LOW 0
#define GPIO_OUT_LEVEL_HIGH 1
/* The following functions are only valid for GPIO bank 1. */
#define GPIO_OUT_BLINK 1
#define GPIO_IN_INVERT 1
#define GPIO_NUM_BANKS 3
#define MAX_GPIO_NUM 75 /* 0 based GPIO number */
#define GPIO_LIST_END 0xff
/* Define possible GPIO configurations. */
#define PCH_GPIO_END \
{ .use_sel = GPIO_LIST_END }
#define PCH_GPIO_NATIVE(gpio) { \
.num = (gpio), \
.use_sel = GPIO_MODE_NATIVE }
#define PCH_GPIO_INPUT(gpio) { \
.num = (gpio), \
.use_sel = GPIO_MODE_GPIO, \
.io_sel = GPIO_INPUT }
#define PCH_GPIO_INPUT_INVERT(gpio) { \
.num = (gpio), \
.use_sel = GPIO_MODE_GPIO, \
.io_sel = GPIO_INPUT, \
.invert_input = GPIO_IN_INVERT }
#define PCH_GPIO_INPUT_NMI(gpio) { \
.num = (gpio), \
.use_sel = GPIO_MODE_GPIO, \
.io_sel = GPIO_INPUT, \
.nmi_en = GPIO_NMI_EN }
#define PCH_GPIO_OUT_LOW(gpio) { \
.num = (gpio), \
.use_sel = GPIO_MODE_GPIO, \
.io_sel = GPIO_OUTPUT, \
.level = GPIO_OUT_LEVEL_LOW }
#define PCH_GPIO_OUT_HIGH(gpio) { \
.num = (gpio), \
.use_sel = GPIO_MODE_GPIO, \
.io_sel = GPIO_OUTPUT, \
.level = GPIO_OUT_LEVEL_HIGH }
#define PCH_GPIO_OUT_BLINK(gpio) { \
.num = (gpio), \
.use_sel = GPIO_MODE_GPIO, \
.io_sel = GPIO_OUTPUT, \
.blink_en = GPIO_OUT_BLINK }
struct gpio_config {
uint8_t num;
uint8_t use_sel;
uint8_t io_sel;
uint8_t level;
uint8_t blink_en;
uint8_t nmi_en;
uint8_t invert_input;
} __packed;
/* Unfortunately the register layout is not linear between different GPIO banks.
* In addition not every bank has all the functions so that some registers might
* be missing on a particular bank. To make the code better readable introduce a
* wrapper structure for the register addresses for every bank.
*/
struct gpio_config_regs {
uint8_t use_sel;
uint8_t io_sel;
uint8_t level;
uint8_t nmi_en;
uint8_t blink_en;
uint8_t invert_input;
};
/* Define gpio_t here to be able to use src/include/gpio.h for gpio_set() and
gpio_get().*/
typedef uint8_t gpio_t;
/* Configure GPIOs with mainboard provided settings */
void init_gpios(const struct gpio_config config[]);
#endif /* FSP_BROADWELL_DE_GPIO_H_ */

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src/soc/intel/fsp_broadwell_de/include/soc/iomap.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_IOMAP_H_
#define _SOC_IOMAP_H_
/*
* Memory Mapped IO bases.
*/
/* PCI Configuration Space */
#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
#define MCFG_BASE_SIZE 0x10000000
/* Transactions in this range will abort */
#define ABORT_BASE_ADDRESS 0xfeb00000
#define ABORT_BASE_SIZE 0x00010000
/* PSEG */
#define PSEG_BASE_ADDRESS 0xfeb80000
#define PSEG_BASE_SIZE 0x00080000
/* IOxAPIC */
#define IOXAPIC1_BASE_ADDRESS 0xfec00000
#define IOXAPIC1_BASE_SIZE 0x00100000
#define IOXAPIC2_BASE_ADDRESS 0xfec01000
#define IOXAPIC2_BASE_SIZE 0x00100000
/* PCH (HPET/LT/TPM/Others) */
#define PCH_BASE_ADDRESS 0xfed00000
#define PCH_BASE_SIZE 0x00100000
/* Local XAPIC */
#define LXAPIC_BASE_ADDRESS 0xfee00000
#define LXAPIC_BASE_SIZE 0x00100000
/* High Performance Event Timer */
#define HPET_BASE_ADDRESS 0xfed00000
#define HPET_BASE_SIZE 0x400
/* Firmware */
#define FIRMWARE_BASE_ADDRESS 0xff000000
#define FIRMWARE_BASE_SIZE 0x01000000
/*
* IO Port bases.
*/
/* ACPI Base Address */
#define ACPI_BASE_ADDRESS 0x400
#define ACPI_BASE_SIZE 0x80
/* GPIO Base Address */
#define GPIO_BASE_ADDRESS 0x500
#define GPIO_BASE_SIZE 0x80
#endif /* _SOC_IOMAP_H_ */

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src/soc/intel/fsp_broadwell_de/include/soc/irq.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_IRQ_H_
#define _SOC_IRQ_H_
#define PIRQA_APIC_IRQ 16
#define PIRQB_APIC_IRQ 17
#define PIRQC_APIC_IRQ 18
#define PIRQD_APIC_IRQ 19
#define PIRQE_APIC_IRQ 20
#define PIRQF_APIC_IRQ 21
#define PIRQG_APIC_IRQ 22
#define PIRQH_APIC_IRQ 23
/* PIC IRQ settings. */
#define PIRQ_PIC_IRQ3 0x3
#define PIRQ_PIC_IRQ4 0x4
#define PIRQ_PIC_IRQ5 0x5
#define PIRQ_PIC_IRQ6 0x6
#define PIRQ_PIC_IRQ7 0x7
#define PIRQ_PIC_IRQ9 0x9
#define PIRQ_PIC_IRQ10 0xa
#define PIRQ_PIC_IRQ11 0xb
#define PIRQ_PIC_IRQ12 0xc
#define PIRQ_PIC_IRQ14 0xe
#define PIRQ_PIC_IRQ15 0xf
#define PIRQ_PIC_IRQDISABLE 0x80
#define PIRQ_PIC_UNKNOWN_UNUSED 0xff
/* Overloaded term, but these values determine the per device route. */
#define PIRQA 0
#define PIRQB 1
#define PIRQC 2
#define PIRQD 3
#define PIRQE 4
#define PIRQF 5
#define PIRQG 6
#define PIRQH 7
#define ACPI_CNTL_OFFSET 0x44
#define SCIS_MASK 0x07
#define SCIS_IRQ9 0x00
#define SCIS_IRQ10 0x01
#define SCIS_IRQ11 0x02
#define SCIS_IRQ20 0x04
#define SCIS_IRQ21 0x05
#define SCIS_IRQ22 0x06
#define SCIS_IRQ23 0x07
/* In each mainboard directory there should exist a header file irqroute.h that
* defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
* consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */
#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
#include <stdint.h>
#define NUM_OF_PCI_DEVS 32
#define NUM_PIRQS 8
struct broadwell_de_irq_route {
/* Per device configuration. */
uint16_t pcidev[NUM_OF_PCI_DEVS];
/* Route path for each internal PIRQx in PIC mode. */
uint8_t pic[NUM_PIRQS];
};
extern const struct broadwell_de_irq_route global_broadwell_de_irq_route;
#define DEFINE_IRQ_ROUTES \
const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \
.pcidev = { PCI_DEV_PIRQ_ROUTES, }, \
.pic = { PIRQ_PIC_ROUTES, }, \
}
#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
[dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)
#define PIRQ_PIC(pirq_, pic_irq_) \
[PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
#endif /* _SOC_IRQ_H_ */

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src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_LPC_H_
#define _SOC_LPC_H_
#include <arch/acpi.h>
/* LPC Interface Bridge PCI Configuration Registers */
#define GPIO_BASE_ADR_OFFSET 0x48
#define GPIO_CTRL_OFFSET 0x4c
#define GPIO_DECODE_ENABLE (1 << 4)
#define REVID 0x08
#define PIRQ_RCR1 0x60
#define SIRQ_CNTL 0x64
#define SIRQ_EN 0x80
#define SIRQ_MODE_QUIET 0x00
#define SIRQ_MODE_CONT 0x40
#define PIRQ_RCR2 0x68
#define LPC_IO_DEC 0x80
#define LPC_EN 0x82
#define LPC_GEN1_DEC 0x84
#define LPC_GEN2_DEC 0x88
#define LPC_GEN3_DEC 0x8c
#define LPC_GEN4_DEC 0x90
#define GEN_PMCON_1 0xA0
#define SMI_LOCK (1 << 4)
#define SMI_LOCK_GP6 (1 << 5)
#define SMI_LOCK_GP22 (1 << 6)
#define GEN_PMCON_2 0xA2
#define GEN_PMCON_3 0xA4
#define RTC_PWR_STS (1 << 2)
/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
#define LPC_DEFAULT_IO_RANGE_LOWER 0
#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
/* IO Mapped registers behind ACPI_BASE_ADDRESS */
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
#define USB_STS (1 << 13)
#define PRBTNOR_STS (1 << 11)
#define RTC_STS (1 << 10)
#define PWRBTN_STS (1 << 8)
#define GBL_STS (1 << 5)
#define TMROF_STS (1 << 0)
#define PM1_EN 0x02
#define PCIEXPWAK_DIS (1 << 14)
#define RTC_EN (1 << 10)
#define PWRBTN_EN (1 << 8)
#define GBL_EN (1 << 5)
#define TMROF_EN (1 << 0)
#define PM1_CNT 0x04
#define GBL_RLS (1 << 2)
#define BM_RLD (1 << 1)
#define SCI_EN (1 << 0)
#define PM1_TMR 0x08
#define GPE0_STS 0x20
#define PCI_EXP_STS (1 << 9)
#define RI_STS (1 << 8)
#define SMB_WAK_STS (1 << 7)
#define TCOSCI_STS (1 << 6)
#define SWGPE_STS (1 << 2)
#define HOT_PLUG_STS (1 << 1)
#define GPE0_EN 0x28
#define SMI_EN 0x30
#define XHCI_SMI_EN (1 << 31)
#define ME_SMI_EN (1 << 30)
#define GPIO_UNLOCK_SMI_EN (1 << 27)
#define INTEL_USB2_EN (1 << 18)
#define LEGACY_USB2_EN (1 << 17)
#define PERIODIC_EN (1 << 14)
#define TCO_EN (1 << 13)
#define MCSMI_EN (1 << 11)
#define BIOS_RLS (1 << 7)
#define SWSMI_TMR_EN (1 << 6)
#define APMC_EN (1 << 5)
#define SLP_SMI_EN (1 << 4)
#define LEGACY_USB_EN (1 << 3)
#define BIOS_EN (1 << 2)
#define EOS (1 << 1)
#define GBL_SMI_EN (1 << 0)
#define SMI_STS 0x34
#define ALT_GPIO_SMI 0x38
#define UPRWC 0x3c
#define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable
#define GPE_CTRL 0x40
#define PM2A_CNT_BLK 0x50
#define TCO_RLD 0x60
#define TCO_STS 0x64
#define SECOND_TO_STS (1 << 17)
#define TCO_TIMEOUT (1 << 3)
#define TCO1_CNT 0x68
#define TCO_LOCK (1 << 12)
#define TCO_TMR_HALT (1 << 11)
#define TCO_TMR 0x70
/* PM1_CNT */
void enable_pm1_control(uint32_t mask);
void disable_pm1_control(uint32_t mask);
/* PM1 */
uint16_t clear_pm1_status(void);
void enable_pm1(uint16_t events);
uint32_t clear_smi_status(void);
/* SMI */
void enable_smi(uint32_t mask);
void disable_smi(uint32_t mask);
#endif /* _SOC_LPC_H_ */

30
src/soc/intel/fsp_broadwell_de/include/soc/memory.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_MEMORY_H_
#define _SOC_MEMORY_H_
/* EDS vol 2, 9.2.24 */
#define REG_MC_BIOS_REQ 0x98
#define REG_MC_BIOS_REQ_FREQ_MSK ((1u << 6) - 1)
#define REG_MC_MULTIPLIER 133.33f
#define IMC_MAX_CHANNELS 2
#define SPD_SLAVE_ADDR(chan, slot) (2 * chan + slot)
void save_dimm_info(void);
#endif

42
src/soc/intel/fsp_broadwell_de/include/soc/msr.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_MSR_H_
#define _SOC_MSR_H_
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
#define MSR_TURBO_RATIO_LIMIT 0x1ad
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
#define MSR_UNCORE_RATIO_LIMIT 0x620
#define MSR_CONFIG_TDP_NOMINAL 0x648
#define SMM_MCA_CAP_MSR 0x17d
#define SMM_CPU_SVRSTR_BIT 57
#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
/* SMM save state MSRs */
#define SMBASE_MSR 0xc20
#define IEDBASE_MSR 0xc22
/* MTRR_CAP_MSR bits */
#define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12)
#define MSR_PRMRR_PHYS_BASE 0x1f4
#define MSR_PRMRR_PHYS_MASK 0x1f5
#endif /* _SOC_MSR_H_ */

52
src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_PATTRS_H_
#define _SOC_PATTRS_H_
#include <stdint.h>
#include <cpu/x86/msr.h>
/*
* The pattrs structure is a common place to stash pertinent information
* about the processor or platform. Instead of going to the source (msrs, cpuid)
* every time an attribute is needed use the pattrs structure.
*/
struct pattrs {
msr_t platform_id;
msr_t platform_info;
uint32_t cpuid;
int revid;
int stepping;
const void *microcode_patch;
int address_bits;
int num_cpus;
};
/*
* This is just to hide the abstraction w/o relying on how the underlying
* storage is allocated.
*/
#define PATTRS_GLOB_NAME __global_pattrs
#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME
extern DEFINE_PATTRS;
static inline const struct pattrs *pattrs_get(void)
{
return &PATTRS_GLOB_NAME;
}
#endif /* _SOC_PATTRS_H_ */

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src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_PCI_DEVS_H_
#define _SOC_PCI_DEVS_H_
#include <device/pci_def.h>
#define BUS0 0
#define SOC_DEV 0
#define SOC_FUNC 0
/* DMI2/PCIe link to PCH */
#define PCIE_IIO_PORT_0_DEV 0x00
#define PCIE_IIO_PORT_0_FUNC 0x00
/* IOU2, x8 PCIe Gen3 port */
#define PCIE_IIO_PORT_1_DEV 0x01
#define PCIE_IIO_PORT_1A_FUNC 0x00
#define PCIE_IIO_PORT_1B_FUNC 0x01
/* IOU0: Internal IOSF bridge to 10 GbE and CBDMA */
#define PCIE_IIO_PORT_2_DEV 0x02
#define PCIE_IIO_PORT_2A_FUNC 0x00
#define PCIE_IIO_PORT_2B_FUNC 0x01
#define PCIE_IIO_PORT_2C_FUNC 0x02
#define PCIE_IIO_PORT_2D_FUNC 0x03
/* IOU1: x16 PCIe Gen3 port */
#define PCIE_IIO_PORT_3_DEV 0x03
#define PCIE_IIO_PORT_3A_FUNC 0x00
#define PCIE_IIO_PORT_3B_FUNC 0x01
#define PCIE_IIO_PORT_3C_FUNC 0x02
#define PCIE_IIO_PORT_3D_FUNC 0x03
#define VTD_DEV 5
#define VTD_FUNC 0
#define IIO_DEVFN_VTD PCI_DEVFN(VTD_DEV, VTD_FUNC)
#define VTD_PCI_DEV PCI_DEV(BUS0, VTD_DEV, VTD_FUNC)
#define LPC_DEV 31
#define LPC_FUNC 0
#define PCH_DEVFN_LPC PCI_DEVFN(LPC_DEV, LPC_FUNC)
#define SATA_DEV 31
#define SATA_FUNC 2
#define SMBUS_DEV 31
#define SMBUS_FUNC 3
#define SATA2_DEV 31
#define SATA2_FUNC 5
#define EHCI1_DEV 29
#define EHCI1_FUNC 0
#define EHCI2_DEV 26
#define EHCI2_FUNC 0
#define XHCI_DEV 20
#define XHCI_FUNC 0
#define XHCI_FUS_REG 0xE0
#define XHCI_FUNC_DISABLE (1 << 0)
#define XHCI_USB2PR_REG 0xD0
#define GBE_DEV 25
#define GBE_FUNC 0
#define ME_DEV 22
#define ME_FUNC 0
#define HDA_DEV 27
#define HDA_FUNC 0
/* Ports from PCH block with adjustable burification settings */
#define PCIE_DEV 28
#define PCIE_PORT1_DEV PCIE_DEV
#define PCIE_PORT1_FUNC 0
#define PCIE_PORT2_DEV PCIE_DEV
#define PCIE_PORT2_FUNC 1
#define PCIE_PORT3_DEV PCIE_DEV
#define PCIE_PORT3_FUNC 2
#define PCIE_PORT4_DEV PCIE_DEV
#define PCIE_PORT4_FUNC 3
#define PCIE_PORT5_DEV PCIE_DEV
#define PCIE_PORT5_FUNC 4
#define PCIE_PORT6_DEV PCIE_DEV
#define PCIE_PORT6_FUNC 5
#define PCIE_PORT7_DEV PCIE_DEV
#define PCIE_PORT7_FUNC 6
#define PCIE_PORT8_DEV PCIE_DEV
#define PCIE_PORT8_FUNC 7
/* The SMM device is located on bus 0xff (QPI) */
#define QPI_BUS 0xff
#define SMM_DEV 0x10
#define SMM_FUNC 0x06
#define IMC_DEV0 19
#define IMC_FUNC0 0
#define IMC_DEV PCI_DEV(QPI_BUS, IMC_DEV0, IMC_FUNC0)
#define PCU1_DEV 30
#define PCU1_FUNC 01
#define UBOX_DEV 16
#define UBOX_FUNC 7
#define SOC_DEVID 0x2F00
#define SOC_DEVID_ES2 0x6F00
#define VTD_DEVID 0x6f28
#define LPC_DEVID 0x8C42
#define LPC_DEVID_ES2 0x8C54
#define AHCI_DEVID 0x8C02
#define SMBUS_DEVID 0x8C22
#define EHCI1_DEVID 0x8C26
#define EHCI2_DEVID 0x8C2D
#define XHCI_DEVID 0x8C31
#define GBE_DEVID 0x8C33
#define ME_DEVID 0x8C3A
#define HDA_DEVID 0x8C20
#define PCIE_PORT1_DEVID 0x8C10
#define PCIE_PORT2_DEVID 0x8C12
#define PCIE_PORT3_DEVID 0x8C14
#define PCIE_PORT4_DEVID 0x8C16
#define PCIE_PORT5_DEVID 0x8C18
#define PCIE_PORT6_DEVID 0x8C1A
#define PCIE_PORT7_DEVID 0x8C1C
#define PCIE_PORT8_DEVID 0x8C1E
#endif /* _SOC_PCI_DEVS_H_ */

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src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_RAMSTAGE_H_
#define _SOC_RAMSTAGE_H_
#include <device/device.h>
/* The broadwell_de_init_pre_device() function is called prior to device
* initialization, but it's after console and cbmem has been reinitialized. */
void broadwell_de_init_pre_device(void);
void broadwell_de_init_cpus(struct device *dev);
void southcluster_enable_dev(struct device *dev);
void broadwell_de_set_dpr(const uintptr_t addr, const size_t size);
void broadwell_de_lock_dpr(void);
extern struct pci_operations soc_pci_ops;
#endif /* _SOC_RAMSTAGE_H_ */

28
src/soc/intel/fsp_broadwell_de/include/soc/romstage.h
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@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_ROMSTAGE_H_
#define _SOC_ROMSTAGE_H_
#include <stdint.h>
#include <fsp.h>
#define NUM_ROMSTAGE_TS 4
void early_mainboard_romstage_entry(void);
void late_mainboard_romstage_entry(void);
#endif /* _SOC_ROMSTAGE_H_ */

48
src/soc/intel/fsp_broadwell_de/include/soc/smbus.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
* Copyright (C) 2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _BROADWELL_SMBUS_H_
#define _BROADWELL_SMBUS_H_
/* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20
#define HOSTC 0x40
#define HST_EN (1 << 0)
#define SMB_RCV_SLVA 0x09
/* SMBus I/O bits. */
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
#define SMBXMITADD 0x4
#define SMBHSTDAT0 0x5
#define SMBHSTDAT1 0x6
#define SMBBLKDAT 0x7
#define SMBTRNSADD 0x9
#define SMBSLVDATA 0xa
#define SMLINK_PIN_CTL 0xe
#define SMBUS_PIN_CTL 0xf
#define SMBUS_TIMEOUT (10 * 1000 * 100)
#define SMBUS_SLAVE_ADDR 0x24
int do_smbus_read_byte(unsigned int smbus_base, unsigned int device,
unsigned int address);
int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
unsigned int address, unsigned int data);
#endif

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src/soc/intel/fsp_broadwell_de/include/soc/smm.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _BROADWELL_SMM_H_
#define _BROADWELL_SMM_H_
#include <stdint.h>
#include <cpu/x86/msr.h>
struct smm_relocation_params {
uintptr_t ied_base;
size_t ied_size;
msr_t smrr_base;
msr_t smrr_mask;
msr_t prmrr_base;
msr_t prmrr_mask;
/* The smm_save_state_in_msrs field indicates if SMM save state
locations live in MSRs. This indicates to the CPUs how to adjust
the SMMBASE and IEDBASE. */
int smm_save_state_in_msrs;
};
#endif

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src/soc/intel/fsp_broadwell_de/include/soc/ubox.h
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* As per "Intel Xeon Processor D-1500 Product Family" volume 2,
* "The UBOX [Processor Utility Box] is the piece of processor logic that deals with
* the non mainstream flows in the system. This includes transactions like the register
* accesses, interrupt flows, lock flows and events. In addition, the UBOX houses
* coordination for the performance architecture, and also houses scratchpad and
* semaphore registers."
*
* In other words, this is a one-die block that has all the useful magic registers.
*/
#ifndef _BROADWELL_UBOX_H_
#define _BROADWELL_UBOX_H_
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/vtd.h>
#define UBOX_UART_ENABLE 0xf8
#define UBOX_UART_ENABLE_PORT0 (1u << 0)
#define UBOX_UART_ENABLE_PORT1 (1u << 1)
#define UBOX_SC_RESET_STATUS 0xc8
#define UBOX_SC_BYPASS (1u << 3)
#define UBOX_DEVHIDE0 0xb0
void iio_hide(DEVTREE_CONST struct device *dev);
#endif

35
src/soc/intel/fsp_broadwell_de/include/soc/vtd.h
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@ -1,35 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _BROADWELL_VTD_H_
#define _BROADWELL_VTD_H_
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#define VTD_CPUBUSNO 0x108
#define VTD_CPUBUSNO_BUS0_MASK 0xff
#define VTD_CPUBUSNO_BUS0_SHIFT 0
#define VTD_CPUBUSNO_BUS1_MASK 0xff
#define VTD_CPUBUSNO_BUS1_SHIFT 8
#define VTD_CPUBUSNO_ISVALID (1u << 16)
#define VTD_DFX1 0x804
#define VTD_DFX1_RANGE_3F8_DISABLE (1u << 29)
#define VTD_DFX1_RANGE_2F8_DISABLE (1u << 30)
uint8_t get_busno1(void);
#endif

53
src/soc/intel/fsp_broadwell_de/iou_complto.c
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@ -1,53 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Arista Networks, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <soc/intel/fsp_broadwell_de/chip.h>
#include <soc/pci_devs.h>
#define DEVCTL2 0xb8
static void iou_init(struct device *dev)
{
/* Use config from device always present in static devicetree. */
const config_t *config = config_of_soc();
u16 devctl2;
/* pcie completion timeout
EDS Vol 2, Section 7.2.54 */
devctl2 = pci_read_config16(dev, DEVCTL2);
devctl2 = (devctl2 & ~0xf) | (config->pcie_compltoval & 0xf);
pci_write_config16(dev, DEVCTL2, devctl2);
}
static struct device_operations iou_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
.init = iou_init,
};
static const unsigned short iou_device_ids[] = {
0x6f02, 0x6f08, 0 };
static const struct pci_driver iou_driver __pci_driver = {
.ops = &iou_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = iou_device_ids,
};

60
src/soc/intel/fsp_broadwell_de/memmap.c
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@ -1,60 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <cbmem.h>
#include <cpu/x86/smm.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <soc/broadwell_de.h>
#include <soc/pci_devs.h>
#include <device/pci_ops.h>
void *cbmem_top_chipset(void)
{
return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR);
}
/*
* Get TSEG base.
*/
uintptr_t sa_get_tseg_base(void)
{
const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC);
/* All regions concerned for have 1 MiB alignment. */
return ALIGN_DOWN(pci_read_config32(dev, TSEG_BASE), 1 * MiB);
}
size_t sa_get_tseg_size(void)
{
const pci_devfn_t dev = PCI_DEV(BUS0, VTD_DEV, VTD_FUNC);
/* All regions concerned for have 1 MiB alignment. */
size_t ret = ALIGN_DOWN(pci_read_config32(dev, TSEG_LIMIT), 1 * MiB);
/* Lower 20bit of TSEG_LIMIT are don't care, need to add 1MiB */
ret += 1 * MiB;
/* Subtract base to get the size */
return ret - sa_get_tseg_base();
}
void smm_region(uintptr_t *start, size_t *size)
{
*start = sa_get_tseg_base();
*size = sa_get_tseg_size();
}

156
src/soc/intel/fsp_broadwell_de/northcluster.c
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@ -1,156 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2016-2018 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/acpi.h>
static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 384;
static void add_fixed_resources(struct device *dev, int index)
{
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
pcie_config_base = MCFG_BASE_ADDRESS;
pcie_config_size = MCFG_BASE_SIZE;
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);
resource = new_resource(dev, index++);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
resource = new_resource(dev, index++); /* Local APIC */
resource->base = LAPIC_DEFAULT_BASE;
resource->size = 0x00001000;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k);
}
static void mc_add_dram_resources(struct device *dev)
{
u32 fsp_mem_base, fsp_mem_len;
u32 tseg_base, tseg_length;
u32 rsv_base, rsv_length;
u32 tolm;
int index = 0;
uint64_t highmem_size = 0;
fsp_mem_base = GetFspReservedMemory(FspHobListPtr, &fsp_mem_len);
highmem_size = GetUsableHighMemTop(FspHobListPtr) - 0x100000000L;
tseg_base = GetTsegReservedMemory(FspHobListPtr, &tseg_length);
tolm = GetPhysicalLowMemTop(FspHobListPtr);
printk(BIOS_DEBUG, "\n\n");
printk(BIOS_DEBUG, "fsp_mem_base: 0x%.8x\n", fsp_mem_base);
printk(BIOS_DEBUG, "fsp_mem_len: 0x%.8x\n", fsp_mem_len);
printk(BIOS_DEBUG, "tseg_base: 0x%.8x\n", tseg_base);
printk(BIOS_DEBUG, "tseg_len: 0x%.8x\n", tseg_length);
printk(BIOS_DEBUG, "highmem_size: 0x%.8x %.8x\n",
(u32)(highmem_size>>32),
(u32)(highmem_size&0xffffffff));
printk(BIOS_DEBUG, "tolm: 0x%.8x\n", tolm);
printk(BIOS_DEBUG, "Top of system low memory: 0x%08x\n", tolm);
printk(BIOS_DEBUG, "FSP memory location: 0x%x\n (size: %dM)\n",
fsp_mem_base, fsp_mem_len >> 20);
printk(BIOS_DEBUG, "tseg: 0x%08x (size: 0x%.8x)\n",
tseg_base, tseg_length);
/* Report the memory regions. */
ram_resource(dev, index++, 0, legacy_hole_base_k);
ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k,
((fsp_mem_base >> 10) - (legacy_hole_base_k + legacy_hole_size_k)));
/* Mark SMM & FSP regions reserved */
mmio_resource(dev, index++, tseg_base >> 10, tseg_length >> 10);
mmio_resource(dev, index++, fsp_mem_base >> 10, fsp_mem_len >> 10);
/* Reserve MMIO space */
rsv_base = fsp_mem_base + fsp_mem_len;
rsv_length = tseg_base - rsv_base;
if (rsv_length) {
mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10);
printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n",
rsv_base, rsv_length);
}
rsv_base = tseg_base + tseg_length;
rsv_length = tolm - rsv_base;
if (rsv_length) {
mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10);
printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n",
rsv_base, rsv_length);
}
if (highmem_size) {
ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10);
}
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
highmem_size >> 20);
add_fixed_resources(dev, index);
}
static void nc_read_resources(struct device *dev)
{
/* Call the normal read_resources */
pci_dev_read_resources(dev);
/* Calculate and add DRAM resources. */
mc_add_dram_resources(dev);
}
static void nc_enable(struct device *dev)
{
print_fsp_info();
}
static struct device_operations nc_ops = {
.read_resources = nc_read_resources,
.acpi_fill_ssdt_generator = generate_cpu_entries,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = NULL,
.enable = &nc_enable,
.scan_bus = 0,
.ops_pci = &soc_pci_ops,
};
static const struct pci_driver nc_driver __pci_driver = {
.ops = &nc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = SOC_DEVID,
};
static const struct pci_driver nc_driver_es2 __pci_driver = {
.ops = &nc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = SOC_DEVID_ES2,
};

173
src/soc/intel/fsp_broadwell_de/pmutil.c
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@ -1,173 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Helper functions for dealing with power management registers
* and the differences between PCH variants.
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
/* Print status bits with descriptive names */
static void print_status_bits(u32 status, const char *const bit_names[])
{
int i;
if (!status)
return;
for (i = 31; i >= 0; i--) {
if (status & (1 << i)) {
if (bit_names[i])
printk(BIOS_DEBUG, "%s ", bit_names[i]);
else
printk(BIOS_DEBUG, "BIT%d ", i);
}
}
}
/* Enable events in PM1 control register */
void enable_pm1_control(u32 mask)
{
u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt |= mask;
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
}
/* Disable events in PM1 control register */
void disable_pm1_control(u32 mask)
{
u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
pm1_cnt &= ~mask;
outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
}
/* Clear and return PM1 status register */
static u16 reset_pm1_status(void)
{
u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);
return pm1_sts;
}
/* Print PM1 status bits */
static u16 print_pm1_status(u16 pm1_sts)
{
static const char *const pm1_sts_bits[] = {
[0] = "TMROF",
[4] = "BM",
[5] = "GBL",
[8] = "PWRBTN",
[10] = "RTC",
[11] = "PRBTNOR",
[14] = "PCIEXPWAK",
[15] = "WAK",
};
if (!pm1_sts)
return 0;
printk(BIOS_SPEW, "PM1_STS: ");
print_status_bits(pm1_sts, pm1_sts_bits);
printk(BIOS_SPEW, "\n");
return pm1_sts;
}
/* Print, clear, and return PM1 status */
u16 clear_pm1_status(void)
{
return print_pm1_status(reset_pm1_status());
}
/* Set the PM1 register to events */
void enable_pm1(u16 events)
{
outw(events, ACPI_BASE_ADDRESS + PM1_EN);
}
/* Clear and return SMI status register */
static u32 reset_smi_status(void)
{
u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
return smi_sts;
}
/* Print SMI status bits */
static u32 print_smi_status(u32 smi_sts)
{
static const char *const smi_sts_bits[] = {
[2] = "BIOS",
[3] = "LEGACY_USB",
[4] = "SLP_SMI",
[5] = "APM",
[6] = "SWSMI_TMR",
[8] = "PM1",
[9] = "GPE0",
[10] = "GPI",
[11] = "MCSMI",
[12] = "DEVMON",
[13] = "TCO",
[14] = "PERIODIC",
[15] = "SERIRQ_SMI",
[16] = "SMBUS_SMI",
[17] = "LEGACY_USB2",
[18] = "INTEL_USB2",
[20] = "PCI_EXP_SMI",
[21] = "MONITOR",
[26] = "SPI",
[27] = "GPIO_UNLOCK"
};
if (!smi_sts)
return 0;
printk(BIOS_DEBUG, "SMI_STS: ");
print_status_bits(smi_sts, smi_sts_bits);
printk(BIOS_DEBUG, "\n");
return smi_sts;
}
/* Print, clear, and return SMI status */
u32 clear_smi_status(void)
{
return print_smi_status(reset_smi_status());
}
/* Enable SMI event */
void enable_smi(u32 mask)
{
u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
smi_en |= mask;
outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
}
/* Disable SMI event */
void disable_smi(u32 mask)
{
u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
smi_en &= ~mask;
outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
}

129
src/soc/intel/fsp_broadwell_de/ramstage.c
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@ -1,129 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdlib.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <soc/lpc.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/broadwell_de.h>
/* Global PATTRS */
DEFINE_PATTRS;
#define SHOW_PATTRS 1
static void detect_num_cpus(struct pattrs *attrs)
{
msr_t core_thread_count = rdmsr(MSR_CORE_THREAD_COUNT);
attrs->num_cpus = core_thread_count.lo & 0xffff;
}
static inline void fill_in_msr(msr_t *msr, int idx)
{
*msr = rdmsr(idx);
if (SHOW_PATTRS) {
printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n",
idx, msr->hi, msr->lo);
}
}
static const char *stepping_str[] = {
"U0", "V1", "V2", "Y0"
};
static void fill_in_pattrs(void)
{
struct device *dev;
struct pattrs *attrs = (struct pattrs *)pattrs_get();
attrs->cpuid = cpuid_eax(1);
attrs->stepping = (attrs->cpuid & 0x0F) - 1;
dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
attrs->revid = pci_read_config8(dev, REVID);
attrs->microcode_patch = intel_microcode_find();
attrs->address_bits = cpuid_eax(0x80000008) & 0xff;
detect_num_cpus(attrs);
if (SHOW_PATTRS) {
printk(BIOS_DEBUG, "CPUID: %08x\n", attrs->cpuid);
printk(BIOS_DEBUG, "Cores: %d\n", attrs->num_cpus);
printk(BIOS_DEBUG, "Stepping: %s\n", (attrs->stepping >= ARRAY_SIZE(stepping_str))
? "??" : stepping_str[attrs->stepping]);
printk(BIOS_DEBUG, "Revision ID: %02x\n", attrs->revid);
}
fill_in_msr(&attrs->platform_id, IA32_PLATFORM_ID);
fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO);
}
void broadwell_de_init_pre_device(void)
{
fill_in_pattrs();
}
/*
* Set DPR region.
*/
void broadwell_de_set_dpr(const uintptr_t addr, const size_t size)
{
struct device *dev;
uint32_t dpr_reg;
/*
* DMA Protected Range can be reserved below TSEG for PCODE patch
* or TXT/BootGuard related data. Rather than reporting a base address
* the DPR register reports the TOP of the region, which is the same
* as TSEG base. The region size is reported in MiB in bits 11:4.
*/
dev = pcidev_on_root(VTD_DEV, VTD_FUNC);
dpr_reg = pci_read_config32(dev, IIO_LTDPR);
if (dpr_reg & DPR_LOCK) {
printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n");
return;
}
dpr_reg &= ~(DPR_ADDR_MASK | DPR_SIZE_MASK);
dpr_reg |= addr & DPR_ADDR_MASK;
dpr_reg |= (size >> (20 - DPR_SIZE_SHIFT)) & DPR_SIZE_MASK;
dpr_reg |= DPR_EPM;
pci_write_config32(dev, IIO_LTDPR, dpr_reg);
}
/*
* Lock DPR register.
*/
void broadwell_de_lock_dpr(void)
{
struct device *dev;
uint32_t dpr_reg;
dev = pcidev_on_root(VTD_DEV, VTD_FUNC);
dpr_reg = pci_read_config32(dev, IIO_LTDPR);
if (dpr_reg & DPR_LOCK) {
printk(BIOS_ERR, "ERROR: HOSTBRIDGE[DPR] is already locked\n");
return;
}
dpr_reg |= DPR_LOCK;
pci_write_config32(dev, IIO_LTDPR, dpr_reg);
}

4
src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc
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@ -1,4 +0,0 @@
romstage-y += romstage.c
romstage-y += memory.c
$(obj)/soc/intel/fsp_broadwell_de/romstage/romstage.romstage.o : $(obj)/build.h

61
src/soc/intel/fsp_broadwell_de/romstage/memory.c
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@ -1,61 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <device/pci_ops.h>
#include <device/dram/ddr4.h>
#include <soc/pci_devs.h>
#include <soc/memory.h>
#include <spd_bin.h>
static uint32_t get_memory_dclk(void)
{
uint32_t reg32 =
pci_mmio_read_config32(PCI_DEV(QPI_BUS, PCU1_DEV, PCU1_FUNC), REG_MC_BIOS_REQ);
return (reg32 & REG_MC_BIOS_REQ_FREQ_MSK) * REG_MC_MULTIPLIER;
}
void save_dimm_info(void)
{
int index = 0;
uint32_t dclk_mhz = 0;
/*
* When talking to SPD chips through IMC slave offset of 0x50 is automagically added
* by hardware. Real-world slave numbers translate to: 0xa0, 0xa2, 0xa4, 0xa6.
*/
struct spd_block blk = {.addr_map = {SPD_SLAVE_ADDR(0, 0), SPD_SLAVE_ADDR(0, 1),
SPD_SLAVE_ADDR(1, 0), SPD_SLAVE_ADDR(1, 1)} };
get_spd_smbus(&blk);
dump_spd_info(&blk);
dclk_mhz = get_memory_dclk();
/*
* The platform is limited to 2 channels and max 2 dimms per channel.
* It doesn't look like DDR3 is supported so we assume memory is all DDR4.
*/
for (int channel = 0; channel < IMC_MAX_CHANNELS; channel++) {
for (int slot = 0; slot < CONFIG_DIMM_MAX / IMC_MAX_CHANNELS; slot++) {
dimm_attr dimm = {0};
u8 *spd_data = blk.spd_array[index];
if (spd_decode_ddr4(&dimm, spd_data) == SPD_STATUS_OK)
spd_add_smbios17_ddr4(channel, slot, dclk_mhz, &dimm);
index++;
}
}
}

216
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
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@ -1,216 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <device/pci_ops.h>
#include <arch/cbfs.h>
#include <cbmem.h>
#include <console/console.h>
#include <console/usb.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <program_loading.h>
#include <timestamp.h>
#include <version.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <pc80/mc146818rtc.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/memory.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/gpio.h>
#include <soc/vtd.h>
#include <soc/ubox.h>
#include <build.h>
static void init_rtc(void)
{
u16 gen_pmcon3 = pci_read_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), GEN_PMCON_3);
if (gen_pmcon3 & RTC_PWR_STS) {
printk(BIOS_DEBUG, "RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
}
cmos_init(gen_pmcon3 & RTC_PWR_STS);
}
/* Set up IO address range and enable it for the GPIO block. */
static void setup_gpio_io_address(void)
{
pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_BASE_ADR_OFFSET,
GPIO_BASE_ADDRESS);
pci_write_config8(PCI_DEV(0, LPC_DEV, LPC_FUNC), GPIO_CTRL_OFFSET,
GPIO_DECODE_ENABLE);
}
static void enable_integrated_uart(uint8_t port)
{
uint32_t ubox_uart_en = 0, dfx1 = 0;
pci_devfn_t ubox_dev;
/* UBOX sits on CPUBUSNO(1) */
ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC);
uint32_t reset_sts = pci_mmio_read_config32(ubox_dev, UBOX_SC_RESET_STATUS);
/* In case we are in bypass mode do nothing */
if (reset_sts & UBOX_SC_BYPASS)
return;
dfx1 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_DFX1);
ubox_uart_en = pci_mmio_read_config32(ubox_dev, UBOX_UART_ENABLE);
switch (port) {
case 0:
ubox_uart_en |= UBOX_UART_ENABLE_PORT0;
dfx1 |= VTD_DFX1_RANGE_3F8_DISABLE;
break;
case 1:
ubox_uart_en |= UBOX_UART_ENABLE_PORT1;
dfx1 |= VTD_DFX1_RANGE_2F8_DISABLE;
break;
default:
printk(BIOS_ERR, "incorrect port number\n");
return;
}
/* Disable decoding and enable the port we want */
pci_mmio_write_config32(VTD_PCI_DEV, VTD_DFX1, dfx1);
pci_mmio_write_config32(ubox_dev, UBOX_UART_ENABLE, ubox_uart_en);
}
static void early_iio_hide(void)
{
DEVTREE_CONST struct device *dev;
const pci_devfn_t iio_rootport[] = {
PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1A_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_1_DEV, PCIE_IIO_PORT_1B_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2A_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2B_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2C_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_2_DEV, PCIE_IIO_PORT_2D_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3A_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3B_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3C_FUNC),
PCI_DEVFN(PCIE_IIO_PORT_3_DEV, PCIE_IIO_PORT_3D_FUNC),
};
/* Walk through IIO root ports and hide if it is disabled in devtree */
for (int i = 0; i < ARRAY_SIZE(iio_rootport); i++) {
dev = pcidev_path_on_bus(BUS0, iio_rootport[i]);
if (dev && !dev->enabled) {
printk(BIOS_DEBUG, "Hiding IIO root port: %d:%d.%d\n",
BUS0,
PCI_SLOT(iio_rootport[i]),
PCI_FUNC(iio_rootport[i]));
iio_hide(dev);
}
}
}
/* Entry from cache-as-ram.inc. */
void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
{
post_code(0x40);
timestamp_init(get_initial_timestamp());
timestamp_add_now(TS_START_ROMSTAGE);
if (!CONFIG(INTEGRATED_UART)) {
/* Enable decoding of I/O locations for Super I/O devices */
pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
LPC_IO_DEC, 0x0010);
pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
LPC_EN, 0x340f);
} else {
enable_integrated_uart(CONFIG_UART_FOR_CONSOLE);
}
/* Call into mainboard. */
post_code(0x41);
early_mainboard_romstage_entry();
post_code(0x42);
console_init();
init_rtc();
setup_gpio_io_address();
/* Hide before MemoryInit since hiding later seems to break FSP */
early_iio_hide();
timestamp_add_now(TS_BEFORE_INITRAM);
post_code(0x48);
/*
* Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB
* structure.
*/
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************
* The FSP early_init function returns to this function.
* Memory is set up and the stack is set by the FSP.
*/
void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr)
{
void *cbmem_hob_ptr;
post_code(0x4a);
timestamp_add_now(TS_AFTER_INITRAM);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
/* FSP reconfigures USB, so reinit it to have debug */
if (CONFIG(USBDEBUG_IN_PRE_RAM))
usbdebug_hw_init(true);
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
post_code(0x4b);
late_mainboard_romstage_entry();
post_code(0x4d);
cbmem_recovery(0);
/* Save the HOB pointer in CBMEM to be used in ramstage*/
cbmem_hob_ptr = cbmem_add(CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
if (cbmem_hob_ptr == NULL)
die("Could not allocate cbmem for HOB pointer");
*(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr;
if (!CONFIG(FSP_MEMORY_DOWN))
save_dimm_info();
if (CONFIG(SMM_TSEG))
smm_list_regions();
/* Load the ramstage. */
post_code(0x4e);
run_ramstage();
while (1);
}
uint64_t get_initial_timestamp(void)
{
return 0;
}

58
src/soc/intel/fsp_broadwell_de/smbus-imc.c
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@ -1,58 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Facebook, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stddef.h>
#include <device/pci_def.h>
#include <device/early_smbus.h>
#include <intelblocks/imc.h>
#include <soc/pci_devs.h>
#include <spd.h>
/* read word, return value on success */
uint16_t smbus_read_word(u32 smbus_dev, u8 addr, u8 offset)
{
uint16_t res = 0;
if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_EEPROM, IMC_DATA_WORD,
IMC_CONTROLLER_ID0, IMC_READ, &res)
== 0) {
return res;
}
return 0;
}
/* read byte, return value on success */
uint8_t smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
{
uint16_t res = 0;
if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_EEPROM, IMC_DATA_BYTE,
IMC_CONTROLLER_ID0, IMC_READ, &res)
== 0) {
return res;
}
return 0;
}
/* write byte, return 0 on success, -1 otherwise */
uint8_t smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value)
{
if (imc_smbus_spd_xfer(IMC_DEV, addr, offset, IMC_DEVICE_WP_EEPROM, IMC_DATA_BYTE,
IMC_CONTROLLER_ID0, IMC_WRITE, &value)
== 0) {
return 0;
}
return -1;
}

96
src/soc/intel/fsp_broadwell_de/smbus.c
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@ -1,96 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2016 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <device/device.h>
#include <device/smbus.h>
#include <device/smbus_def.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/smbus.h>
static void pch_smbus_init(struct device *dev)
{
struct resource *res;
/* Set Receive Slave Address */
res = find_resource(dev, PCI_BASE_ADDRESS_4);
if (res)
outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
}
static void pch_smbus_enable(struct device *dev)
{
uint8_t reg8;
reg8 = pci_read_config8(dev, HOSTC);
reg8 |= HST_EN;
pci_write_config8(dev, HOSTC, reg8);
}
static int lsmbus_read_byte(struct device *dev, uint8_t address)
{
uint16_t device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(struct device *dev, uint8_t address, uint8_t data)
{
uint16_t device;
struct resource *res;
struct bus *pbus;
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, data);
}
static struct smbus_bus_operations lops_smbus_bus = {
.read_byte = lsmbus_read_byte,
.write_byte = lsmbus_write_byte,
};
static struct device_operations smbus_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.scan_bus = scan_smbus,
.init = pch_smbus_init,
.enable = pch_smbus_enable,
.ops_smbus_bus = &lops_smbus_bus,
};
static const unsigned short pci_device_ids[] = {
SMBUS_DEVID,
0
};
static const struct pci_driver pch_smbus __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

150
src/soc/intel/fsp_broadwell_de/smbus_common.c
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@ -1,150 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
#include <device/smbus_def.h>
#include <device/pci.h>
#include <soc/ramstage.h>
#include <soc/smbus.h>
static void smbus_delay(void)
{
inb(0x80);
}
static int smbus_wait_until_ready(u16 smbus_base)
{
unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
if (--loops == 0)
break;
byte = inb(smbus_base + SMBHSTSTAT);
} while (byte & 1);
return loops ? 0 : -1;
}
static int smbus_wait_until_done(u16 smbus_base)
{
unsigned int loops = SMBUS_TIMEOUT;
unsigned char byte;
do {
smbus_delay();
if (--loops == 0)
break;
byte = inb(smbus_base + SMBHSTSTAT);
} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
return loops ? 0 : -1;
}
int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, unsigned int address)
{
unsigned char global_status_register;
unsigned char byte;
if (smbus_wait_until_ready(smbus_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
/* Setup transaction */
/* Disable interrupts */
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
/* Set the device I'm talking to */
outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
/* Set the command/address... */
outb(address & 0xff, smbus_base + SMBHSTCMD);
/* Set up for a byte data read */
outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
(smbus_base + SMBHSTCTL));
/* Clear any lingering errors, so the transaction will run */
outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
/* Clear the data byte... */
outb(0, smbus_base + SMBHSTDAT0);
/* Start the command */
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
if (smbus_wait_until_done(smbus_base) < 0) {
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inb(smbus_base + SMBHSTSTAT);
/* Ignore the "In Use" status... */
global_status_register &= ~(3 << 5);
/* Read results of transaction */
byte = inb(smbus_base + SMBHSTDAT0);
if (global_status_register != (1 << 1)) {
return SMBUS_ERROR;
}
return byte;
}
int do_smbus_write_byte(unsigned int smbus_base, unsigned int device,
unsigned int address, unsigned int data)
{
unsigned char global_status_register;
if (smbus_wait_until_ready(smbus_base) < 0)
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
/* Setup transaction */
/* Disable interrupts */
outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
/* Set the device I'm talking to */
outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD);
/* Set the command/address... */
outb(address & 0xff, smbus_base + SMBHSTCMD);
/* Set up for a byte data read */
outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
(smbus_base + SMBHSTCTL));
/* Clear any lingering errors, so the transaction will run */
outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
/* Clear the data byte... */
outb(data, smbus_base + SMBHSTDAT0);
/* Start the command */
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
if (smbus_wait_until_done(smbus_base) < 0) {
printk(BIOS_ERR, "SMBUS transaction timeout\n");
return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
global_status_register = inb(smbus_base + SMBHSTSTAT);
/* Ignore the "In Use" status... */
global_status_register &= ~(3 << 5);
/* Read results of transaction */
if (global_status_register != (1 << 1)) {
printk(BIOS_ERR, "SMBUS transaction error\n");
return SMBUS_ERROR;
}
return 0;
}

90
src/soc/intel/fsp_broadwell_de/smi.c
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@ -1,90 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <cpu/intel/smm_reloc.h>
#include <arch/io.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/smm.h>
void smm_southbridge_clear_state(void)
{
u32 smi_en;
printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", ACPI_BASE_ADDRESS);
smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
if (smi_en & APMC_EN) {
printk(BIOS_INFO, "SMI# handler already enabled?\n");
return;
}
printk(BIOS_DEBUG, "\n");
/* Dump and clear status registers */
clear_smi_status();
clear_pm1_status();
}
static void southbridge_clear_smi_status(void);
void smm_southbridge_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Clear all possible set SMI status bits
before enabling SMIs. */
southbridge_clear_smi_status();
/* Enable SMI generation:
- on SERIRQ-SMI (is always enabled) */
enable_smi(EOS | GBL_SMI_EN);
}
static void __unused southbridge_trigger_smi(void)
{
/*
* There are several methods of raising a controlled SMI# via
* software, among them:
* - Writes to io 0xb2 (APMC)
* - Writes to the Local Apic ICR with Delivery mode SMI.
*
* Using the local apic is a bit more tricky. According to
* AMD Family 11 Processor BKDG no destination shorthand must be
* used.
* The whole SMM initialization is quite a bit hardware specific, so
* I'm not too worried about the better of the methods at the moment
*/
/* Raise an SMI interrupt */
printk(BIOS_SPEW, " ... raise SMI#\n");
outb(0x00, 0xb2);
}
static void southbridge_clear_smi_status(void)
{
/* Clear SMI status */
clear_smi_status();
/* Clear PM1 status */
clear_pm1_status();
/* Set EOS bit so other SMIs can occur. */
enable_smi(EOS);
}

106
src/soc/intel/fsp_broadwell_de/smihandler.c
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@ -1,106 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <types.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
#include <spi-generic.h>
#include <soc/lpc.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/smm.h>
/**
* @brief Set the EOS bit
*/
void southbridge_smi_set_eos(void)
{
enable_smi(EOS);
}
static void southbridge_smi_serirq(void)
{
}
typedef void (*smi_handler_t)(void);
static smi_handler_t southbridge_smi[32] = {
NULL, // [0] reserved
NULL, // [1] reserved
NULL, // [2] BIOS_STS
NULL, // [3] LEGACY_USB_STS
NULL, // [4] SLP_SMI_STS
NULL, // [5] APM_STS
NULL, // [6] SWSMI_TMR_STS
NULL, // [7] reserved
NULL, // [8] PM1_STS
NULL, // [9] GPE0_STS
NULL, // [10] GPI_STS
NULL, // [11] MCSMI_STS
NULL, // [12] DEVMON_STS
NULL, // [13] TCO_STS
NULL, // [14] PERIODIC_STS
southbridge_smi_serirq, // [15] SERIRQ_SMI_STS
NULL, // [16] SMBUS_SMI_STS
NULL, // [17] LEGACY_USB2_STS
NULL, // [18] INTEL_USB2_STS
NULL, // [19] reserved
NULL, // [20] PCI_EXP_SMI_STS
NULL, // [21] MONITOR_STS
NULL, // [22] reserved
NULL, // [23] reserved
NULL, // [24] reserved
NULL, // [25] EL_SMI_STS
NULL, // [26] SPI_STS
NULL, // [27] reserved
NULL, // [28] reserved
NULL, // [29] reserved
NULL, // [30] reserved
NULL // [31] reserved
};
/**
* @brief Interrupt handler for SMI#
*
* @param smm_revision revision of the smm state save map
*/
void southbridge_smi_handler(void)
{
int i;
u32 smi_sts;
/* We need to clear the SMI status registers, or we won't see what's
happening in the following calls. */
smi_sts = clear_smi_status();
/* Call SMI sub handler for each of the status bits */
for (i = 0; i < 31; i++) {
if (smi_sts & (1 << i)) {
if (southbridge_smi[i]) {
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
"SMI_STS[%d] occurred, but no "
"handler available.\n", i);
}
}
}
}

306
src/soc/intel/fsp_broadwell_de/smmrelocate.c
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@ -1,306 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <types.h>
#include <string.h>
#include <device/pci.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/em64t101_save_state.h>
#include <cpu/intel/smm_reloc.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/smm.h>
#include <soc/broadwell_de.h>
/* This gets filled in and used during relocation. */
static struct smm_relocation_params smm_reloc_params;
static inline void write_smrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
}
static inline void write_prmrr(struct smm_relocation_params *relo_params)
{
printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
}
static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
struct smm_relocation_params *relo_params)
{
u32 smbase;
u32 iedbase;
/* The relocated handler runs with all CPUs concurrently. Therefore
stagger the entry points adjusting SMBASE downwards by save state
size * CPU num. */
smbase = staggered_smbase;
iedbase = relo_params->ied_base;
printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n",
smbase, iedbase);
/*
* All threads need to set IEDBASE and SMBASE to the relocated
* handler region. However, the save state location depends on the
* smm_save_state_in_msrs field in the relocation parameters. If
* smm_save_state_in_msrs is non-zero then the CPUs are relocating
* the SMM handler in parallel, and each CPUs save state area is
* located in their respective MSR space. If smm_save_state_in_msrs
* is zero then the SMM relocation is happening serially so the
* save state is at the same default location for all CPUs.
*/
if (relo_params->smm_save_state_in_msrs) {
msr_t smbase_msr;
msr_t iedbase_msr;
smbase_msr.lo = smbase;
smbase_msr.hi = 0;
/* According the BWG the IEDBASE MSR is in bits 63:32. It's
not clear why it differs from the SMBASE MSR. */
iedbase_msr.lo = 0;
iedbase_msr.hi = iedbase;
wrmsr(SMBASE_MSR, smbase_msr);
wrmsr(IEDBASE_MSR, iedbase_msr);
} else {
em64t101_smm_state_save_area_t *save_state;
save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
sizeof(*save_state));
save_state->smbase = smbase;
save_state->iedbase = iedbase;
}
}
/* Returns 1 if SMM MSR save state was set. */
static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
{
msr_t smm_mca_cap;
smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
uint32_t smm_feature_control;
pci_devfn_t dev = PCI_DEV(QPI_BUS, SMM_DEV, SMM_FUNC);
/*
* SMM_FEATURE_CONTROL on Broadwell-DE is not located in
* MSR range but in PCI config space. The used PCI device is
* located on bus 0xff, which has no root bridge and hence is
* not scanned by PCI scan. Use MMIO config access to read the
* needed 32 bit register.
*/
smm_feature_control = pci_read_config32(dev,
SMM_FEATURE_CONTROL);
smm_feature_control |= SMM_CPU_SAVE_EN;
pci_write_config32(dev,
SMM_FEATURE_CONTROL, smm_feature_control);
relo_params->smm_save_state_in_msrs = 1;
}
return relo_params->smm_save_state_in_msrs;
}
/*
* The relocation work is actually performed in SMM context, but the code
* resides in the ramstage module. This occurs by trampolining from the default
* SMRAM entry point to here.
*/
void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase)
{
msr_t mtrr_cap;
struct smm_relocation_params *relo_params = &smm_reloc_params;
printk(BIOS_DEBUG, "In relocation handler: CPU %d\n", cpu);
/* Determine if the processor supports saving state in MSRs. If so,
enable it before the non-BSPs run so that SMM relocation can occur
in parallel in the non-BSP CPUs. */
if (cpu == 0) {
/*
* If smm_save_state_in_msrs is 1 then that means this is the
* 2nd time through the relocation handler for the BSP.
* Parallel SMM handler relocation is taking place. However,
* it is desired to access other CPUs save state in the real
* SMM handler. Therefore, disable the SMM save state in MSRs
* feature.
*/
if (relo_params->smm_save_state_in_msrs) {
uint32_t smm_feature_control;
pci_devfn_t dev = PCI_DEV(QPI_BUS, SMM_DEV, SMM_FUNC);
/*
* SMM_FEATURE_CONTROL on Broadwell-DE is not located in
* MSR range but in PCI config space. The used PCI
* device is located on bus 0xff, which has no root
* bridge and hence is not scanned by PCI scan.
* Use MMIO config access to read the needed 32 bit
* register.
*/
smm_feature_control = pci_read_config32(dev,
SMM_FEATURE_CONTROL);
smm_feature_control &= ~SMM_CPU_SAVE_EN;
pci_write_config32(dev, SMM_FEATURE_CONTROL,
smm_feature_control);
} else if (bsp_setup_msr_save_state(relo_params))
/*
* Just return from relocation handler if MSR save
* state is enabled. In that case the BSP will come
* back into the relocation handler to setup the new
* SMBASE as well disabling SMM save state in MSRs.
*/
return;
}
/* Make appropriate changes to the save state map. */
update_save_state(cpu, curr_smbase, staggered_smbase, relo_params);
/* Write PRMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
if (mtrr_cap.lo & SMRR_SUPPORTED)
write_smrr(relo_params);
if (mtrr_cap.lo & PRMRR_SUPPORTED)
write_prmrr(relo_params);
}
static void fill_in_relocation_params(struct smm_relocation_params *params)
{
uintptr_t tseg_base;
size_t tseg_size;
u32 prmrr_base;
u32 prmrr_size;
int phys_bits;
/* All range registers are aligned to 4KiB */
const u32 rmask = ~((1 << 12) - 1);
/* Some of the range registers are dependent on the number of physical
address bits supported. */
phys_bits = cpuid_eax(0x80000008) & 0xff;
/*
* The range bounded by the TSEG_BASE and TSEG_LIMIT registers
* encompasses the SMRAM range as well as the IED range.
* However, the SMRAM available to the handler is 4MiB since the IEDRAM
* lives TSEG_BASE + 4MiB.
*
* Note that address bits 19:0 are ignored and not compared.
* The result is that BASE[19:0] is effectively 00000h and LIMIT is
* effectively FFFFFh.
*/
smm_region(&tseg_base, &tseg_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* The PRMRR is at IEDBASE + 2MiB */
prmrr_base = (params->ied_base + (2 << 20)) & rmask;
prmrr_size = params->ied_size - (2 << 20);
/* PRMRR has 46 bits of valid address aligned to 4KiB. It's dependent
on the number of physical address bits supported. */
params->prmrr_base.lo = prmrr_base | MTRR_TYPE_WRBACK;
params->prmrr_base.hi = 0;
params->prmrr_mask.lo = (~(prmrr_size - 1) & rmask)
| MTRR_PHYS_MASK_VALID;
params->prmrr_mask.hi = (1 << (phys_bits - 32)) - 1;
}
static void setup_ied_area(struct smm_relocation_params *params)
{
char *ied_base;
struct ied_header ied = {
.signature = "INTEL RSVD",
.size = params->ied_size,
.reserved = {0},
};
ied_base = (void *)params->ied_base;
/* Place IED header at IEDBASE. */
memcpy(ied_base, &ied, sizeof(ied));
/* Zero out 32KiB at IEDBASE + 1MiB */
memset(ied_base + (1 << 20), 0, (32 << 10));
}
void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
size_t *smm_save_state_size)
{
printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
fill_in_relocation_params(&smm_reloc_params);
smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
setup_ied_area(&smm_reloc_params);
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
}
void smm_initialize(void)
{
/* Clear the SMM state in the southbridge. */
smm_southbridge_clear_state();
/* Run the relocation handler for on the BSP to check and set up
parallel SMM relocation. */
smm_initiate_relocation();
if (smm_reloc_params.smm_save_state_in_msrs)
printk(BIOS_DEBUG, "Doing parallel SMM relocation.\n");
}
/*
* The default SMM entry can happen in parallel or serially. If the
* default SMM entry is done in parallel the BSP has already setup
* the saving state to each CPU's MSRs. At least one save state size
* is required for the initial SMM entry for the BSP to determine if
* parallel SMM relocation is even feasible.
*/
void smm_relocate(void)
{
/*
* If smm_save_state_in_msrs is non-zero then parallel SMM relocation
* shall take place. Run the relocation handler a second time on the
* BSP to do the final move. For APs, a relocation handler always
* needs to be run.
*/
if (smm_reloc_params.smm_save_state_in_msrs)
smm_initiate_relocation_parallel();
else if (!boot_cpu())
smm_initiate_relocation();
}

301
src/soc/intel/fsp_broadwell_de/southcluster.c
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@ -1,301 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <pc80/i8254.h>
#include <pc80/i8259.h>
#include <pc80/isa-dma.h>
#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/acpi.h>
#include <soc/ubox.h>
#include "chip.h"
typedef struct soc_intel_fsp_broadwell_de_config config_t;
static inline void
add_mmio_resource(struct device *dev, int i, unsigned long addr,
unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
}
static void sc_add_mmio_resources(struct device *dev)
{
add_mmio_resource(dev, 0xfeb0,
ABORT_BASE_ADDRESS,
ABORT_BASE_SIZE);
add_mmio_resource(dev, 0xfeb8,
PSEG_BASE_ADDRESS,
PSEG_BASE_SIZE);
add_mmio_resource(dev, 0xfec0,
IOXAPIC1_BASE_ADDRESS,
IOXAPIC1_BASE_SIZE);
add_mmio_resource(dev, 0xfec1,
IOXAPIC2_BASE_ADDRESS,
IOXAPIC2_BASE_SIZE);
add_mmio_resource(dev, 0xfed0,
PCH_BASE_ADDRESS,
PCH_BASE_SIZE);
add_mmio_resource(dev, 0xfee0,
LXAPIC_BASE_ADDRESS,
LXAPIC_BASE_SIZE);
add_mmio_resource(dev, 0xff00,
FIRMWARE_BASE_ADDRESS,
FIRMWARE_BASE_SIZE);
}
/*
* Write PCI config space IRQ assignments. PCI devices have the INT_LINE
* (0x3C) and INT_PIN (0x3D) registers which report interrupt routing
* information to operating systems and drivers. The INT_PIN register is
* generally read only and reports which interrupt pin A - D it uses. The
* INT_LINE register is configurable and reports which IRQ (generally the
* PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling
* on devices that are downstream on a PCI bridge into account.
*
* This function will loop through all enabled PCI devices and program the
* INT_LINE register with the correct PIC IRQ number for the INT_PIN that it
* uses. It then configures each interrupt in the pic to be level triggered.
*/
static void write_pci_config_irqs(void)
{
struct device *irq_dev;
struct device *targ_dev;
uint8_t int_line = 0;
uint8_t original_int_pin = 0;
uint8_t new_int_pin = 0;
uint16_t current_bdf = 0;
uint16_t parent_bdf = 0;
uint8_t pirq = 0;
uint8_t device_num = 0;
const struct broadwell_de_irq_route *ir = &global_broadwell_de_irq_route;
if (ir == NULL) {
printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because"
" 'global_broadwell_de_irq_route' structure does not exist\n");
return;
}
/*
* Loop through all enabled devices and program their
* INT_LINE, INT_PIN registers from values taken from
* the Interrupt Route registers in the ILB
*/
printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
(!irq_dev->enabled))
continue;
current_bdf = irq_dev->path.pci.devfn |
irq_dev->bus->secondary << 8;
/*
* Step 1: Get the INT_PIN and device structure to look for
* in the pirq_data table defined in the mainboard directory.
*/
targ_dev = NULL;
new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev);
if (targ_dev == NULL || new_int_pin < 1)
continue;
/* Get the original INT_PIN for record keeping */
original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
parent_bdf = targ_dev->path.pci.devfn
| targ_dev->bus->secondary << 8;
device_num = PCI_SLOT(parent_bdf);
if (ir->pcidev[device_num] == 0) {
printk(BIOS_WARNING,
"Warning: PCI Device %d does not have an IRQ entry, skipping it\n",
device_num);
continue;
}
/* Find the PIRQ that is attached to the INT_PIN this device uses */
pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF;
/* Get the INT_LINE this device/function will use */
int_line = ir->pic[pirq];
if (int_line != PIRQ_PIC_IRQDISABLE) {
/* Set this IRQ to level triggered since it is used by a PCI device */
i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
/* Set the Interrupt Line register in PCI config space */
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
} else {
/* Set the Interrupt line register as "unknown or unused" */
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE,
PIRQ_PIC_UNKNOWN_UNUSED);
}
printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n",
original_int_pin, pin_to_str(original_int_pin));
if (parent_bdf != current_bdf)
printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n",
new_int_pin, pin_to_str(new_int_pin));
printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n"
"\tINT_LINE\t: 0x%X (IRQ %d)\n",
'A' + pirq, int_line, int_line);
}
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
static void sc_pirq_init(struct device *dev)
{
int i;
const uint8_t *pirq = global_broadwell_de_irq_route.pic;
printk(BIOS_DEBUG, "Programming PIRQ[A-H] Routing Control Register\n");
for (i = 0; i < 8; i++) {
pci_write_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4), pirq[i]);
printk(BIOS_DEBUG, " PIRQ[%c]: %.2x\n"
, 'A'+i
, pci_read_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4))
);
}
}
static void sc_add_io_resources(struct device *dev)
{
struct resource *res;
u8 io_index = 0;
/*
* Add the default claimed IO range for the LPC device
* and mark it as subtractive decode.
*/
res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = LPC_DEFAULT_IO_RANGE_LOWER;
res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add the resource for GPIOs */
res = new_resource(dev, GPIO_BASE_ADR_OFFSET);
res->base = GPIO_BASE_ADDRESS;
res->size = GPIO_BASE_SIZE;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* There is a separated enable-bit in GPIO_CTRL-register. It was set
* already in romstage but FSP was active in the meantime and could have
* cleared it. Set it here again to enable allocated IO-space for sure.
*/
pci_write_config8(dev, GPIO_CTRL_OFFSET, GPIO_DECODE_ENABLE);
}
static void sc_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
sc_add_mmio_resources(dev);
sc_add_io_resources(dev);
}
static void sc_init(struct device *dev)
{
printk(BIOS_DEBUG, "soc: southcluster_init\n");
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
/* Program Serial IRQ register. */
pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_CONT);
if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) {
/* If SERIRQ have to operate in quiet mode, it should have been
run in continuous mode for at least one frame first. Use I/O
access to achieve the delay of at least one LPC cycle. */
outb(inb(0x80), 0x80);
pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_QUIET);
}
sc_pirq_init(dev);
write_pci_config_irqs();
isa_dma_init();
setup_i8259();
setup_i8254();
}
/*
* Common code for the south cluster devices.
*/
void southcluster_enable_dev(struct device *dev)
{
uint32_t reg32;
if (dev->enabled)
return;
const int slot = PCI_SLOT(dev->path.pci.devfn);
const int func = PCI_FUNC(dev->path.pci.devfn);
printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, func);
/* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
}
#if CONFIG(HAVE_ACPI_TABLES)
static const char *lpc_acpi_name(const struct device *dev)
{
if (dev->path.pci.devfn == PCH_DEVFN_LPC)
return "LPC0";
else
return NULL;
}
#endif
static struct device_operations device_ops = {
.read_resources = sc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = NULL,
.write_acpi_tables = southcluster_write_acpi_tables,
.init = sc_init,
.enable = southcluster_enable_dev,
.scan_bus = scan_static_bus,
.ops_pci = &soc_pci_ops,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = lpc_acpi_name,
#endif
};
static const struct pci_driver southcluster __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = LPC_DEVID,
};
static const struct pci_driver southcluster_es2 __pci_driver = {
.ops = &device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = LPC_DEVID_ES2,
};

28
src/soc/intel/fsp_broadwell_de/tsc_freq.c
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@ -1,28 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <soc/msr.h>
#include <soc/broadwell_de.h>
unsigned long tsc_freq_mhz(void)
{
msr_t platform_info;
platform_info = rdmsr(MSR_PLATFORM_INFO);
return CPU_BCLK * ((platform_info.lo >> 8) & 0xff);
}

30
src/soc/intel/fsp_broadwell_de/ubox.c
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@ -1,30 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Facebook Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define __SIMPLE_DEVICE__
#include <stdint.h>
#include <soc/ubox.h>
void iio_hide(DEVTREE_CONST struct device *dev)
{
pci_devfn_t ubox_dev;
uint8_t slot, func;
slot = PCI_SLOT(dev->path.pci.devfn);
func = PCI_FUNC(dev->path.pci.devfn);
ubox_dev = PCI_DEV(get_busno1(), UBOX_DEV, UBOX_FUNC);
pci_or_config32(ubox_dev, UBOX_DEVHIDE0 + func * 4, 1 << slot);
}

59
src/soc/intel/fsp_broadwell_de/vtd.c
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@ -1,59 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <soc/pci_devs.h>
#include <soc/acpi.h>
#include <soc/vtd.h>
#include <soc/broadwell_de.h>
#if ENV_RAMSTAGE
static void vtd_read_resources(struct device *dev)
{
uint32_t vtbar;
/* Add fixed MMIO resource for VT-d which was set up by the FSP. */
vtbar = pci_read_config32(dev, VTBAR_OFFSET);
if (vtbar & VTBAR_ENABLED) {
mmio_resource(dev, VTBAR_OFFSET,
(vtbar & VTBAR_MASK) / KiB, VTBAR_SIZE / KiB);
}
}
static struct device_operations vtd_ops = {
.read_resources = vtd_read_resources,
.set_resources = DEVICE_NOOP,
.write_acpi_tables = vtd_write_acpi_tables,
};
static const struct pci_driver vtd_driver __pci_driver = {
.ops = &vtd_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = VTD_DEVID,
};
#endif
uint8_t get_busno1(void)
{
uint32_t reg32;
/* Figure out what bus number is assigned for CPUBUSNO(1) */
reg32 = pci_mmio_read_config32(VTD_PCI_DEV, VTD_CPUBUSNO);
return ((reg32 >> VTD_CPUBUSNO_BUS1_SHIFT) & VTD_CPUBUSNO_BUS1_MASK);
}