sravan/system76-coreboot
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Rename almost all occurences of LinuxBIOS to coreboot.

Browse Source 
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2008-01-18 15:08:58 +00:00
committed by Stefan Reinauer
parent 7e61e45402
commit f8ee1806ac
388 changed files with 1718 additions and 1718 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
src/arch/i386/Config.lb
View File

@@ -22,12 +22,12 @@ else
end
makerule all
depends "linuxbios.rom"
depends "coreboot.rom"
end
makerule floppy
depends "all"
action "mcopy -o linuxbios.rom a:"
action "mcopy -o coreboot.rom a:"
end
makerule nrv2b
@@ -55,7 +55,7 @@ end
# this one example shows the mess that has occurred. People are now mixing
# conditional if in the make style with if in the config language style.
# The -1 is linux standard.
# I don't much like it but it is the mode nowadays. So linuxbios will change
# I don't much like it but it is the mode nowadays. So coreboot will change
# what a mess. -- RGM
# catch the case where there is no compression
makedefine PAYLOAD-1:=payload
@@ -70,16 +70,16 @@ if CONFIG_PRECOMPRESSED_PAYLOAD
end
if USE_FAILOVER_IMAGE
makedefine LINUXBIOS_APC:=
makedefine LINUXBIOS_RAM_ROM:=
makedefine COREBOOT_APC:=
makedefine COREBOOT_RAM_ROM:=
makerule linuxbios.rom
depends "linuxbios.strip"
makerule coreboot.rom
depends "coreboot.strip"
action "cp $< $@"
end
else
makerule linuxbios.rom
depends "linuxbios.strip buildrom $(PAYLOAD-1)"
makerule coreboot.rom
depends "coreboot.strip buildrom $(PAYLOAD-1)"
action "./buildrom $< $@ $(PAYLOAD-1) $(ROM_IMAGE_SIZE) $(ROM_SECTION_SIZE)"
end
end
@@ -98,10 +98,10 @@ if CONFIG_USE_INIT
action "$(OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
end
makerule linuxbios
depends "crt0.o init.o $(LINUXBIOS_APC) $(LINUXBIOS_RAM_ROM) ldscript.ld"
makerule coreboot
depends "crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
action "$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
action "$(CROSS_COMPILE)nm -n linuxbios | sort > linuxbios.map"
action "$(CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
end
end

2
src/arch/i386/boot/acpi.c
View File

@@ -1,5 +1,5 @@
/*
* LinuxBIOS ACPI Table support
* coreboot ACPI Table support
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2004 SUSE LINUX AG
* (C) 2005 Stefan Reinauer

20
src/arch/i386/boot/boot.c
View File

@@ -113,8 +113,8 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" addl 12(%%esp), %%eax\n\t"
" addl 8(%%esp), %%eax\n\t"
" movl %%eax, 20(%%esp)\n\t"
/* Place a copy of linuxBIOS in it's new location */
/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
/* Place a copy of coreboot in it's new location */
/* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 12(%%esp), %%edi\n\t"
" addl 8(%%esp), %%edi\n\t"
" movl 16(%%esp), %%esi\n\t"
@@ -122,16 +122,16 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
/* Adjust the stack pointer to point into the new linuxBIOS image */
/* Adjust the stack pointer to point into the new coreboot image */
" addl 20(%%esp), %%esp\n\t"
/* Adjust the instruction pointer to point into the new linuxBIOS image */
/* Adjust the instruction pointer to point into the new coreboot image */
" movl $1f, %%eax\n\t"
" addl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"
"1: \n\t"
/* Copy the linuxBIOS bounce buffer over linuxBIOS */
/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
/* Copy the coreboot bounce buffer over coreboot */
/* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 16(%%esp), %%edi\n\t"
" movl 12(%%esp), %%esi\n\t"
" movl 8(%%esp), %%ecx\n\t"
@@ -147,8 +147,8 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" cli \n\t"
" cld \n\t"
/* Copy the saved copy of linuxBIOS where linuxBIOS runs */
/* Move ``longs'' the linuxBIOS size is 4 byte aligned */
/* Copy the saved copy of coreboot where coreboot runs */
/* Move ``longs'' the coreboot size is 4 byte aligned */
" movl 16(%%esp), %%edi\n\t"
" movl 12(%%esp), %%esi\n\t"
" addl 8(%%esp), %%esi\n\t"
@@ -156,10 +156,10 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
" shrl $2, %%ecx\n\t"
" rep movsl\n\t"
/* Adjust the stack pointer to point into the old linuxBIOS image */
/* Adjust the stack pointer to point into the old coreboot image */
" subl 20(%%esp), %%esp\n\t"
/* Adjust the instruction pointer to point into the old linuxBIOS image */
/* Adjust the instruction pointer to point into the old coreboot image */
" movl $1f, %%eax\n\t"
" subl 20(%%esp), %%eax\n\t"
" jmp *%%eax\n\t"

34
src/arch/i386/boot/linuxbios_table.c
View File

@@ -122,16 +122,16 @@ void lb_strings(struct lb_header *header)
uint32_t tag;
const char *string;
} strings[] = {
{ LB_TAG_VERSION, linuxbios_version, },
{ LB_TAG_EXTRA_VERSION, linuxbios_extra_version, },
{ LB_TAG_BUILD, linuxbios_build, },
{ LB_TAG_COMPILE_TIME, linuxbios_compile_time, },
{ LB_TAG_COMPILE_BY, linuxbios_compile_by, },
{ LB_TAG_COMPILE_HOST, linuxbios_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
{ LB_TAG_COMPILER, linuxbios_compiler, },
{ LB_TAG_LINKER, linuxbios_linker, },
{ LB_TAG_ASSEMBLER, linuxbios_assembler, },
{ LB_TAG_VERSION, coreboot_version, },
{ LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
{ LB_TAG_BUILD, coreboot_build, },
{ LB_TAG_COMPILE_TIME, coreboot_compile_time, },
{ LB_TAG_COMPILE_BY, coreboot_compile_by, },
{ LB_TAG_COMPILE_HOST, coreboot_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
{ LB_TAG_COMPILER, coreboot_compiler, },
{ LB_TAG_LINKER, coreboot_linker, },
{ LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
@@ -201,7 +201,7 @@ unsigned long lb_table_fini(struct lb_header *head)
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n",
printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n",
head, rec, head->table_checksum);
return (unsigned long)rec;
}
@@ -315,8 +315,8 @@ static void lb_add_memory_range(struct lb_memory *mem,
lb_cleanup_memory_ranges(mem);
}
/* Routines to extract part so the linuxBIOS table or
* information from the linuxBIOS table after we have written it.
/* Routines to extract part so the coreboot table or
* information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
*/
@@ -348,7 +348,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
return mem;
}
unsigned long write_linuxbios_table(
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
@@ -383,7 +383,7 @@ unsigned long write_linuxbios_table(
rec_dest = lb_new_record(head);
rec_src = (struct lb_record *)(void *)&option_table;
memcpy(rec_dest, rec_src, rec_src->size);
/* Create cmos checksum entry in linuxbios table */
/* Create cmos checksum entry in coreboot table */
lb_cmos_checksum(head);
}
#endif
@@ -401,9 +401,9 @@ unsigned long write_linuxbios_table(
/* Note:
* I assume that there is always memory at immediately after
* the low_table_end. This means that after I setup the linuxbios table.
* the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
* size of the linuxbios table.
* size of the coreboot table.
*/
/* Record our motheboard */

14
src/arch/i386/boot/linuxbios_table.h
View File

@@ -1,10 +1,10 @@
#ifndef LINUXBIOS_TABLE_H
#define LINUXBIOS_TABLE_H
#ifndef COREBOOT_TABLE_H
#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
/* This file holds function prototypes for building the linuxbios table. */
unsigned long write_linuxbios_table(
/* This file holds function prototypes for building the coreboot table. */
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
@@ -19,11 +19,11 @@ void lb_memory_range(struct lb_memory *mem,
struct lb_mainboard *lb_mainboard(struct lb_header *header);
unsigned long lb_table_fini(struct lb_header *header);
/* Routines to extract part so the linuxBIOS table or information
* from the linuxBIOS table.
/* Routines to extract part so the coreboot table or information
* from the coreboot table.
*/
struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
#endif /* LINUXBIOS_TABLE_H */
#endif /* COREBOOT_TABLE_H */

8
src/arch/i386/boot/tables.c
View File

@@ -23,7 +23,7 @@ struct gdtarg {
// Copy GDT to new location and reload it
// 2003-07 by SONE Takeshi
// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
// Ported from Etherboot to coreboot 2005-08 by Steve Magnani
void move_gdt(unsigned long newgdt)
{
uint16_t num_gdt_bytes = &gdt_end - &gdt;
@@ -58,7 +58,7 @@ struct lb_memory *write_tables(void)
/* Write ACPI tables */
/* write them in the rom area because DSDT can be large (8K on epia-m) which
* pushes linuxbios table out of first 4K if set up in low table area
* pushes coreboot table out of first 4K if set up in low table area
*/
rom_table_end = write_acpi_tables(rom_table_end);
rom_table_end = (rom_table_end+1023) & ~1023;
@@ -105,8 +105,8 @@ struct lb_memory *write_tables(void)
move_gdt(low_table_end);
low_table_end += &gdt_end - &gdt;
/* The linuxbios table must be in 0-4K or 960K-1M */
write_linuxbios_table(low_table_start, low_table_end,
/* The coreboot table must be in 0-4K or 960K-1M */
write_coreboot_table(low_table_start, low_table_end,
rom_table_start, rom_table_end);
return get_lb_mem();

2
src/arch/i386/include/arch/acpi.h
View File

@@ -1,5 +1,5 @@
/*
* Initial LinuxBIOS ACPI Support - headers and defines.
* coreboot ACPI Support - headers and defines.
*
* written by Stefan Reinauer <stepan@openbios.org>
* (C) 2004 SUSE LINUX AG

2
src/arch/i386/include/arch/romcc_io.h
View File

@@ -84,7 +84,7 @@ static inline int log2f(int value)
typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */
/* FIXME: We need to make the LinuxBIOS to run at 64bit mode, So when read/write memory above 4G,
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
*/

8
src/arch/i386/init/crt0.S.lb
View File

@@ -16,7 +16,7 @@
*
* - Converted to gas assembly, and refitted to work with etherboot.
* Eric Biederman 20 Aug 2002
* - Merged the nrv2b decompressor into crt0.base of LinuxBIOS
* - Merged the nrv2b decompressor into crt0.base of coreboot
* Eric Biederman 26 Sept 2002
*/
@@ -65,7 +65,7 @@ __main:
cld /* clear direction flag */
/* copy linuxBIOS from it's initial load location to
/* copy coreboot from it's initial load location to
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
@@ -215,8 +215,8 @@ crt_console_tx_string:
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
.section ".rom.data"
str_copying_to_ram: .string "Copying LinuxBIOS to RAM.\r\n"
str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
str_pre_main: .string "Jumping to coreboot.\r\n"
.previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */

6
src/arch/i386/init/ldscript.lb
View File

@@ -7,7 +7,7 @@
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : coreboot text
* : readonly text
*/
/*
@@ -32,14 +32,14 @@ ENTRY(_start)
*/
TARGET(binary)
INPUT(linuxbios_ram.rom)
INPUT(coreboot_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
coreboot_ram.rom(*)
_eram = . ;
}

4
src/arch/i386/init/ldscript_apc.lb
View File

@@ -1,9 +1,9 @@
INPUT(linuxbios_apc.rom)
INPUT(coreboot_apc.rom)
SECTIONS
{
.apcrom . : {
_apcrom = .;
linuxbios_apc.rom(*)
coreboot_apc.rom(*)
_eapcrom = .;
}
_iseg_apc = DCACHE_RAM_BASE;

2
src/arch/i386/init/ldscript_failover.lb
View File

@@ -7,7 +7,7 @@
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : coreboot text
* : readonly text
*/
/*

6
src/arch/i386/init/ldscript_fallback.lb
View File

@@ -7,7 +7,7 @@
* : heap
* : stack
* _ROMBASE
* : linuxbios text
* : coreboot text
* : readonly text
*/
/*
@@ -32,14 +32,14 @@ ENTRY(_start)
*/
TARGET(binary)
INPUT(linuxbios_ram.rom)
INPUT(coreboot_ram.rom)
SECTIONS
{
. = _ROMBASE;
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
coreboot_ram.rom(*)
_eram = . ;
}

4
src/arch/i386/lib/c_start.S
View File

@@ -251,8 +251,8 @@ gdtaddr:
.data
/* This is the gdt for GCC part of LinuxBIOS.
* It is different from the gdt in ROMCC/ASM part of LinuxBIOS
/* This is the gdt for GCC part of coreboot.
* It is different from the gdt in ROMCC/ASM part of coreboot
* which is defined in entry32.inc */
gdt:
/* selgdt 0, unused */

12
src/arch/i386/lib/console.c
View File

@@ -19,19 +19,19 @@ static void __console_tx_byte(unsigned char byte)
#endif /* CONFIG_USE_PRINTK_IN_CAR */
#ifndef LINUXBIOS_EXTRA_VERSION
#define LINUXBIOS_EXTRA_VERSION ""
#ifndef COREBOOT_EXTRA_VERSION
#define COREBOOT_EXTRA_VERSION ""
#endif
static void console_init(void)
{
static const char console_test[] =
"\r\n\r\nLinuxBIOS-"
LINUXBIOS_VERSION
LINUXBIOS_EXTRA_VERSION
"\r\n\r\ncoreboot-"
COREBOOT_VERSION
COREBOOT_EXTRA_VERSION
" "
LINUXBIOS_BUILD
COREBOOT_BUILD
" starting...\r\n";
print_info(console_test);
}

4
src/arch/ppc/Config.lb
View File

@@ -1,7 +1,7 @@
ldscript init/ldscript.lb
makerule linuxbios.rom
depends "linuxbios"
makerule coreboot.rom
depends "coreboot"
action "cp $< $@"
end

2
src/arch/ppc/boot/boot.c
View File

@@ -29,7 +29,7 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer)
*/
flush_dcache();
/* On ppc we don't currently support loading over LinuxBIOS.
/* On ppc we don't currently support loading over coreboot.
* So ignore the buffer.
*/

32
src/arch/ppc/boot/linuxbios_table.c
View File

@@ -104,16 +104,16 @@ void lb_strings(struct lb_header *header)
uint32_t tag;
const uint8_t *string;
} strings[] = {
{ LB_TAG_VERSION, linuxbios_version, },
{ LB_TAG_EXTRA_VERSION, linuxbios_extra_version, },
{ LB_TAG_BUILD, linuxbios_build, },
{ LB_TAG_COMPILE_TIME, linuxbios_compile_time, },
{ LB_TAG_COMPILE_BY, linuxbios_compile_by, },
{ LB_TAG_COMPILE_HOST, linuxbios_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, linuxbios_compile_domain, },
{ LB_TAG_COMPILER, linuxbios_compiler, },
{ LB_TAG_LINKER, linuxbios_linker, },
{ LB_TAG_ASSEMBLER, linuxbios_assembler, },
{ LB_TAG_VERSION, coreboot_version, },
{ LB_TAG_EXTRA_VERSION, coreboot_extra_version, },
{ LB_TAG_BUILD, coreboot_build, },
{ LB_TAG_COMPILE_TIME, coreboot_compile_time, },
{ LB_TAG_COMPILE_BY, coreboot_compile_by, },
{ LB_TAG_COMPILE_HOST, coreboot_compile_host, },
{ LB_TAG_COMPILE_DOMAIN, coreboot_compile_domain, },
{ LB_TAG_COMPILER, coreboot_compiler, },
{ LB_TAG_LINKER, coreboot_linker, },
{ LB_TAG_ASSEMBLER, coreboot_assembler, },
};
unsigned int i;
for(i = 0; i < sizeof(strings)/sizeof(strings[0]); i++) {
@@ -183,7 +183,7 @@ unsigned long lb_table_fini(struct lb_header *head)
head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
head->header_checksum = 0;
head->header_checksum = compute_ip_checksum(head, sizeof(*head));
printk_debug("Wrote linuxbios table at: %p - %p checksum %lx\n",
printk_debug("Wrote coreboot table at: %p - %p checksum %lx\n",
head, rec, head->table_checksum);
return (unsigned long)rec;
}
@@ -297,8 +297,8 @@ static void lb_add_memory_range(struct lb_memory *mem,
lb_cleanup_memory_ranges(mem);
}
/* Routines to extract part so the linuxBIOS table or
* information from the linuxBIOS table after we have written it.
/* Routines to extract part so the coreboot table or
* information from the coreboot table after we have written it.
* Currently get_lb_mem relies on a global we can change the
* implementaiton.
*/
@@ -330,7 +330,7 @@ static struct lb_memory *build_lb_mem(struct lb_header *head)
return mem;
}
unsigned long write_linuxbios_table(
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end)
{
@@ -363,9 +363,9 @@ unsigned long write_linuxbios_table(
/* Note:
* I assume that there is always memory at immediately after
* the low_table_end. This means that after I setup the linuxbios table.
* the low_table_end. This means that after I setup the coreboot table.
* I can trivially fixup the reserved memory ranges to hold the correct
* size of the linuxbios table.
* size of the coreboot table.
*/
/* Record our motheboard */

14
src/arch/ppc/boot/linuxbios_table.h
View File

@@ -1,12 +1,12 @@
#ifndef LINUXBIOS_TABLE_H
#define LINUXBIOS_TABLE_H
#ifndef COREBOOT_TABLE_H
#define COREBOOT_TABLE_H
#include <boot/linuxbios_tables.h>
struct mem_range;
/* This file holds function prototypes for building the linuxbios table. */
unsigned long write_linuxbios_table(
/* This file holds function prototypes for building the coreboot table. */
unsigned long write_coreboot_table(
unsigned long low_table_start, unsigned long low_table_end,
unsigned long rom_table_start, unsigned long rom_table_end);
@@ -21,11 +21,11 @@ void lb_memory_range(struct lb_memory *mem,
struct lb_mainboard *lb_mainboard(struct lb_header *header);
unsigned long lb_table_fini(struct lb_header *header);
/* Routines to extract part so the linuxBIOS table or information
* from the linuxBIOS table.
/* Routines to extract part so the coreboot table or information
* from the coreboot table.
*/
struct lb_memory *get_lb_mem(void);
extern struct cmos_option_table option_table;
#endif /* LINUXBIOS_TABLE_H */
#endif /* COREBOOT_TABLE_H */

4
src/arch/ppc/boot/tables.c
View File

@@ -18,8 +18,8 @@ write_tables(void)
low_table_start = 0;
low_table_end = 16;
/* The linuxbios table must be in 0-4K or 960K-1M */
write_linuxbios_table(
/* The coreboot table must be in 0-4K or 960K-1M */
write_coreboot_table(
low_table_start, low_table_end,
rom_table_start, rom_table_end);

14
src/arch/ppc/init/ldscript.lb
View File

@@ -5,7 +5,7 @@
* _RESET : reset vector (may be at top of ROM)
* _EXCEPTIONS_VECTORS : exception table
*
* _ROMSTART : linuxbios text
* _ROMSTART : coreboot text
* : payload text
*
* _RAMBASE : address to copy payload
@@ -26,7 +26,7 @@ OUTPUT_FORMAT("elf32-powerpc")
ENTRY(_start)
TARGET(binary)
INPUT(linuxbios_ram.rom)
INPUT(coreboot_ram.rom)
SECTIONS
{
/*
@@ -54,7 +54,7 @@ SECTIONS
}
/*
* Absolute location of LinuxBIOS initialization code in ROM.
* Absolute location of coreboot initialization code in ROM.
*/
. = _ROMSTART;
.rom . : {
@@ -63,7 +63,7 @@ SECTIONS
*(.text);
*(.rom.data);
*(.rodata);
*(EXCLUDE_FILE(linuxbios_ram.rom) .data);
*(EXCLUDE_FILE(coreboot_ram.rom) .data);
. = ALIGN(16);
_erom = .;
}
@@ -71,16 +71,16 @@ SECTIONS
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/*
* Ram is the LinuxBIOS code that runs from RAM.
* Ram is the coreboot code that runs from RAM.
*/
.ram . : {
_ram = . ;
linuxbios_ram.rom(*)
coreboot_ram.rom(*)
_eram = . ;
}
/*
* Absolute location of where LinuxBIOS will be relocated in RAM.
* Absolute location of where coreboot will be relocated in RAM.
*/
_iseg = _RAMBASE;
_eiseg = _iseg + SIZEOF(.ram);