Add gigabyte/m57sli support to Kconfig.
Whitespace fixes to devicetree.cb Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Harald Gutmann
Patrick Georgi
parent
37ea341079
commit
f9ef2081ba
@ -21,8 +21,9 @@
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choice
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prompt "Mainboard model"
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depends on VENDOR_GIGABYTE
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source "src/mainboard/gigabyte/ga-6bxc/Kconfig"
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source "src/mainboard/gigabyte/m57sli/Kconfig"
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endchoice
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153
src/mainboard/gigabyte/m57sli/Kconfig
Normal file
153
src/mainboard/gigabyte/m57sli/Kconfig
Normal file
@ -0,0 +1,153 @@
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config BOARD_GIGABYTE_M57SLI
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bool "M57SLI"
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select ARCH_X86
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select CPU_AMD_K8
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select CPU_AMD_SOCKET_AM2
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_NVIDIA_MCP55
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select SUPERIO_ITE_IT8716F
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select PIRQ_TABLE
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select USE_PRINTK_IN_CAR
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select USE_DCACHE_RAM
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select HAVE_HARD_RESET
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select HAVE_HIGH_TABLES
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select IOAPIC
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select MEM_TRAIN_SEQ
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select SB_HT_CHAIN_UNITID_OFFSET_ONLY
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select HAVE_ACPI_TABLES
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select K8_REV_F_SUPPORT
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select PCI_ROM_RUN
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select CONSOLE_VGA
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select HAVE_FANCTL
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config MAINBOARD_DIR
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string
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default gigabyte/m57sli
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depends on BOARD_GIGABYTE_M57SLI
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_GIGABYTE_M57SLI
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config DCACHE_RAM_SIZE
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hex
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default 0x08000
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depends on BOARD_GIGABYTE_M57SLI
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x01000
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depends on BOARD_GIGABYTE_M57SLI
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config APIC_ID_OFFSET
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hex
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default 16
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depends on BOARD_GIGABYTE_M57SLI
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config SB_HT_CHAIN_ON_BUS0
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int
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default 2
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depends on BOARD_GIGABYTE_M57SLI
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config LB_CKS_RANGE_START
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int
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default 49
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depends on BOARD_GIGABYTE_M57SLI
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config LB_CKS_RANGE_END
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int
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default 122
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depends on BOARD_GIGABYTE_M57SLI
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config LB_CKS_LOC
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int
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default 123
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depends on BOARD_GIGABYTE_M57SLI
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config MAINBOARD_PART_NUMBER
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string
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default "m57sli"
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depends on BOARD_GIGABYTE_M57SLI
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config PCI_64BIT_PREF_MEM
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config HAVE_FALLBACK_BOOT
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config USE_FALLBACK_IMAGE
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x100000
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depends on BOARD_GIGABYTE_M57SLI
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config USE_FAILOVER_IMAGE
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config MAX_CPUS
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int
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default 2
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depends on BOARD_GIGABYTE_M57SLI
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config MAX_PHYSICAL_CPUS
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int
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default 1
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depends on BOARD_GIGABYTE_M57SLI
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config AP_CODE_IN_CAR
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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depends on BOARD_GIGABYTE_M57SLI
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x0
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depends on BOARD_GIGABYTE_M57SLI
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config USE_INIT
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config SERIAL_CPU_INIT
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config WAIT_BEFORE_CPUS_INIT
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bool
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default n
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depends on BOARD_GIGABYTE_M57SLI
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1022
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depends on BOARD_GIGABYTE_M57SLI
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x2b80
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depends on BOARD_GIGABYTE_M57SLI
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67
src/mainboard/gigabyte/m57sli/Makefile.inc
Normal file
67
src/mainboard/gigabyte/m57sli/Makefile.inc
Normal file
@ -0,0 +1,67 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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## MA 02110-1301 USA
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##
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driver-y += mainboard.o
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#needed by irq_tables and mptable and acpi_tables
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obj-y += get_bus_conf.o
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obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
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obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
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obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o
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obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
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obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
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obj-$(CONFIG_HAVE_FANCTL) += fanctl.o
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# This is part of the conversion to init-obj and away from included code.
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initobj-y += crt0.o
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crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
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crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
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crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
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crt0-y += ../../../../src/arch/i386/lib/id.inc
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crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
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crt0-y += auto.inc
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ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
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ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
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ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
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ldscript-y += ../../../../src/arch/i386/lib/id.lds
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ldscript-y += ../../../../src/arch/i386/lib/failover.lds
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ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
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ifdef POST_EVALUATION
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$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
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iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
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mv $(obj)/dsdt.hex $@
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$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
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$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@
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$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
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$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
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perl -e 's/\.rodata/.rom.data/g' -pi $@
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perl -e 's/\.text/.section .rom.text/g' -pi $@
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endif
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@ -1,202 +1,175 @@
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chip northbridge/amd/amdk8/root_complex
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device apic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8 #mc0
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device pci 18.0 on
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# devices on link 0, link 0 == LDT 0
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chip southbridge/nvidia/mcp55
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device pci 0.0 on end # HT
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device pci 1.0 on # LPC
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chip superio/ite/it8716f
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# Floppy and any LDN
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device pnp 2e.0 off
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# Watchdog from CLKIN, CLKIN = 24 MHz
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irq 0x23 = 0x11
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device apic_cluster 0 on
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chip cpu/amd/socket_AM2
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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chip northbridge/amd/amdk8
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device pci 18.0 on
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chip southbridge/nvidia/mcp55
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device pci 0.0 on end
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device pci 1.0 on
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chip superio/ite/it8716f
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# Floppy and any LDN
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device pnp 2e.0 on
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# Watchdog from CLKIN, CLKIN = 24 MHz
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irq 0x23 = 0x11
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# Serial Flash (SPI only)
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#0x24 = 0x1a
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x290
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO, SPI flash
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# pin 84 is not GP10
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irq 0x25 = 0x0
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# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
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irq 0x26 = 0x43
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# pin 13 is GP35
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irq 0x27 = 0x20
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# pin 70 is not GP46
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#irq 0x28 = 0x0
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# pin 6,3,128,127,126 is GP63,64,65,66,67
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irq 0x29 = 0x81
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# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
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#irq 0x2c = 0x1f
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# Simple I/O base
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io 0x62 = 0x800
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# Serial Flash I/O (SPI only)
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io 0x64 = 0x820
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# watch dog force timeout (parallel flash only)
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#irq 0x71 = 0x1
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# No WDT interrupt
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irq 0x72 = 0x0
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# GPIO pin set 1 disable internal pullup
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irq 0xb8 = 0x0
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# GPIO pin set 5 enable internal pullup
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irq 0xbc = 0x01
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# SIO pin set 1 alternate function
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#irq 0xc0 = 0x0
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# SIO pin set 2 mixed function
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irq 0xc1 = 0x43
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# SIO pin set 3 mixed function
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irq 0xc2 = 0x20
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# SIO pin set 4 alternate function
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#irq 0xc3 = 0x0
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# SIO pin set 1 input mode
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#irq 0xc8 = 0x0
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# SIO pin set 2 input mode
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irq 0xc9 = 0x0
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# SIO pin set 4 input mode
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#irq 0xcb = 0x0
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# Generate SMI# on EC IRQ
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#irq 0xf0 = 0x10
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# SMI# level trigger
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#irq 0xf1 = 0x40
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# HWMON alert beep pin location
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irq 0xf6 = 0x28
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 10
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end
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device pnp 2e.9 off # GAME
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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#0x24 = 0x1a
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x290
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO, SPI flash
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# pin 84 is not GP10
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irq 0x25 = 0x0
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# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
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irq 0x26 = 0x43
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# pin 13 is GP35
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irq 0x27 = 0x20
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# pin 70 is not GP46
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#irq 0x28 = 0x0
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# pin 6,3,128,127,126 is GP63,64,65,66,67
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irq 0x29 = 0x81
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# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
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#irq 0x2c = 0x1f
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# Simple I/O base
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io 0x62 = 0x800
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# Serial Flash I/O (SPI only)
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io 0x64 = 0x820
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# watch dog force timeout (parallel flash only)
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#irq 0x71 = 0x1
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# No WDT interrupt
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irq 0x72 = 0x0
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# GPIO pin set 1 disable internal pullup
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irq 0xb8 = 0x0
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# GPIO pin set 5 enable internal pullup
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irq 0xbc = 0x01
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# SIO pin set 1 alternate function
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#irq 0xc0 = 0x0
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# SIO pin set 2 mixed function
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irq 0xc1 = 0x43
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# SIO pin set 3 mixed function
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irq 0xc2 = 0x20
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# SIO pin set 4 alternate function
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#irq 0xc3 = 0x0
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# SIO pin set 1 input mode
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#irq 0xc8 = 0x0
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# SIO pin set 2 input mode
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irq 0xc9 = 0x0
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# SIO pin set 4 input mode
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#irq 0xcb = 0x0
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# Generate SMI# on EC IRQ
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#irq 0xf0 = 0x10
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# SMI# level trigger
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#irq 0xf1 = 0x40
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# HWMON alert beep pin location
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irq 0xf6 = 0x28
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 10
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end
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device pnp 2e.9 off # GAME
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io 0x60 = 0x220
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end
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device pnp 2e.a off # CIR
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end
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end
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device pci 1.1 on # SM 0
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chip drivers/generic/generic #dimm 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic #dimm 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic #dimm 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic #dimm 0-1-1
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device i2c 53 on end
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end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
#WTF?!? We already have device pci 1.1 in the section above
|
||||
device pci 1.1 on # SM 1
|
||||
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
|
||||
# chip drivers/generic/generic #PCIXA Slot1
|
||||
# device i2c 50 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot1
|
||||
# device i2c 51 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCIXB Slot2
|
||||
# device i2c 52 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #PCI Slot1
|
||||
# device i2c 53 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Master MCP55 PCI-E
|
||||
# device i2c 54 on end
|
||||
# end
|
||||
# chip drivers/generic/generic #Slave MCP55 PCI-E
|
||||
# device i2c 55 on end
|
||||
# end
|
||||
chip drivers/generic/generic #MAC EEPROM
|
||||
device i2c 51 on end
|
||||
end
|
||||
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on end # PCI
|
||||
device pci 6.1 on end # AZA
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 off end # NIC
|
||||
device pci a.0 on end # PCI E 5
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
end
|
||||
device pci 1.1 on
|
||||
chip drivers/generic/generic #dimm 0-0-0
|
||||
device i2c 50 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-0-1
|
||||
device i2c 51 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-0
|
||||
device i2c 52 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 0-1-1
|
||||
device i2c 53 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-0
|
||||
device i2c 54 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-0-1
|
||||
device i2c 55 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-0
|
||||
device i2c 56 on end
|
||||
end
|
||||
chip drivers/generic/generic #dimm 1-1-1
|
||||
device i2c 57 on end
|
||||
end
|
||||
end # SM
|
||||
device pci 2.0 on end # USB 1.1
|
||||
device pci 2.1 on end # USB 2
|
||||
device pci 4.0 on end # IDE
|
||||
device pci 5.0 on end # SATA 0
|
||||
device pci 5.1 on end # SATA 1
|
||||
device pci 5.2 on end # SATA 2
|
||||
device pci 6.0 on end # PCI
|
||||
device pci 6.1 on end # AUDIO
|
||||
device pci 8.0 on end # NIC
|
||||
device pci 9.0 off end # N/A
|
||||
device pci a.0 on end # PCI E 5
|
||||
device pci b.0 on end # PCI E 4
|
||||
device pci c.0 on end # PCI E 3
|
||||
device pci d.0 on end # PCI E 2
|
||||
device pci e.0 on end # PCI E 1
|
||||
device pci f.0 on end # PCI E 0
|
||||
register "ide0_enable" = "1"
|
||||
register "sata0_enable" = "1"
|
||||
register "sata1_enable" = "1"
|
||||
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
|
||||
register "mac_eeprom_addr" = "0x51"
|
||||
end
|
||||
end # device pci 18.0
|
||||
end #device pci 18.0
|
||||
device pci 18.0 on end # Link 1
|
||||
device pci 18.0 on end
|
||||
device pci 18.1 on end
|
||||
device pci 18.2 on end
|
||||
device pci 18.3 on end
|
||||
end # mc0
|
||||
|
||||
end # PCI domain
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 on end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 off end # io
|
||||
# end
|
||||
|
||||
# chip drivers/generic/debug
|
||||
# device pnp 0.0 off end # chip name
|
||||
# device pnp 0.1 on end # pci_regs_all
|
||||
# device pnp 0.2 on end # mem
|
||||
# device pnp 0.3 off end # cpuid
|
||||
# device pnp 0.4 on end # smbus_regs_all
|
||||
# device pnp 0.5 off end # dual core msr
|
||||
# device pnp 0.6 off end # cache size
|
||||
# device pnp 0.7 off end # tsc
|
||||
# device pnp 0.8 off end # io
|
||||
# device pnp 0.9 off end # io
|
||||
# end
|
||||
|
||||
end #root_complex
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user