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Add gigabyte/m57sli support to Kconfig.

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Whitespace fixes to devicetree.cb

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Harald Gutmann 2009-10-03 21:06:53 +00:00 committed by Patrick Georgi
parent 37ea341079
commit f9ef2081ba
4 changed files with 383 additions and 189 deletions
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1
src/mainboard/gigabyte/Kconfig
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@ -23,6 +23,7 @@ choice
depends on VENDOR_GIGABYTE
source "src/mainboard/gigabyte/ga-6bxc/Kconfig"
source "src/mainboard/gigabyte/m57sli/Kconfig"
endchoice

153
src/mainboard/gigabyte/m57sli/Kconfig Normal file
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@ -0,0 +1,153 @@
config BOARD_GIGABYTE_M57SLI
bool "M57SLI"
select ARCH_X86
select CPU_AMD_K8
select CPU_AMD_SOCKET_AM2
select NORTHBRIDGE_AMD_AMDK8
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_ITE_IT8716F
select PIRQ_TABLE
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
select HAVE_HARD_RESET
select HAVE_HIGH_TABLES
select IOAPIC
select MEM_TRAIN_SEQ
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select HAVE_ACPI_TABLES
select K8_REV_F_SUPPORT
select PCI_ROM_RUN
select CONSOLE_VGA
select HAVE_FANCTL
config MAINBOARD_DIR
string
default gigabyte/m57sli
depends on BOARD_GIGABYTE_M57SLI
config DCACHE_RAM_BASE
hex
default 0xc8000
depends on BOARD_GIGABYTE_M57SLI
config DCACHE_RAM_SIZE
hex
default 0x08000
depends on BOARD_GIGABYTE_M57SLI
config DCACHE_RAM_GLOBAL_VAR_SIZE
hex
default 0x01000
depends on BOARD_GIGABYTE_M57SLI
config APIC_ID_OFFSET
hex
default 16
depends on BOARD_GIGABYTE_M57SLI
config SB_HT_CHAIN_ON_BUS0
int
default 2
depends on BOARD_GIGABYTE_M57SLI
config LB_CKS_RANGE_START
int
default 49
depends on BOARD_GIGABYTE_M57SLI
config LB_CKS_RANGE_END
int
default 122
depends on BOARD_GIGABYTE_M57SLI
config LB_CKS_LOC
int
default 123
depends on BOARD_GIGABYTE_M57SLI
config MAINBOARD_PART_NUMBER
string
default "m57sli"
depends on BOARD_GIGABYTE_M57SLI
config PCI_64BIT_PREF_MEM
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config HAVE_FALLBACK_BOOT
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config USE_FALLBACK_IMAGE
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
depends on BOARD_GIGABYTE_M57SLI
config USE_FAILOVER_IMAGE
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config MAX_CPUS
int
default 2
depends on BOARD_GIGABYTE_M57SLI
config MAX_PHYSICAL_CPUS
int
default 1
depends on BOARD_GIGABYTE_M57SLI
config AP_CODE_IN_CAR
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config HT_CHAIN_UNITID_BASE
hex
default 0x0
depends on BOARD_GIGABYTE_M57SLI
config HT_CHAIN_END_UNITID_BASE
hex
default 0x0
depends on BOARD_GIGABYTE_M57SLI
config USE_INIT
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config SERIAL_CPU_INIT
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config WAIT_BEFORE_CPUS_INIT
bool
default n
depends on BOARD_GIGABYTE_M57SLI
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
default 0x1022
depends on BOARD_GIGABYTE_M57SLI
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
default 0x2b80
depends on BOARD_GIGABYTE_M57SLI

67
src/mainboard/gigabyte/m57sli/Makefile.inc Normal file
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@ -0,0 +1,67 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2008 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##
driver-y += mainboard.o
#needed by irq_tables and mptable and acpi_tables
obj-y += get_bus_conf.o
obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o
obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += dsdt.o
obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.o
obj-$(CONFIG_HAVE_FANCTL) += fanctl.o
# This is part of the conversion to init-obj and away from included code.
initobj-y += crt0.o
crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
crt0-y += ../../../../src/arch/i386/lib/id.inc
crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
crt0-y += auto.inc
ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
ldscript-y += ../../../../src/arch/i386/lib/id.lds
ldscript-y += ../../../../src/arch/i386/lib/failover.lds
ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb
ifdef POST_EVALUATION
$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
mv $(obj)/dsdt.hex $@
$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@
$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h
$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@
perl -e 's/\.rodata/.rom.data/g' -pi $@
perl -e 's/\.text/.section .rom.text/g' -pi $@
endif

49
src/mainboard/gigabyte/m57sli/devicetree.cb
View File

@ -5,15 +5,14 @@ chip northbridge/amd/amdk8/root_complex
end
end
device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0
chip northbridge/amd/amdk8
device pci 18.0 on
# devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/mcp55
device pci 0.0 on end # HT
device pci 1.0 on # LPC
device pci 0.0 on end
device pci 1.0 on
chip superio/ite/it8716f
# Floppy and any LDN
device pnp 2e.0 off
device pnp 2e.0 on
# Watchdog from CLKIN, CLKIN = 24 MHz
irq 0x23 = 0x11
# Serial Flash (SPI only)
@ -30,7 +29,7 @@ chip northbridge/amd/amdk8/root_complex
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 off # Parallel Port
device pnp 2e.3 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
@ -100,10 +99,11 @@ chip northbridge/amd/amdk8/root_complex
device pnp 2e.9 off # GAME
io 0x60 = 0x220
end
device pnp 2e.a off end # CIR
device pnp 2e.a off # CIR
end
end
device pci 1.1 on # SM 0
end
device pci 1.1 on
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
@ -129,32 +129,6 @@ chip northbridge/amd/amdk8/root_complex
device i2c 57 on end
end
end # SM
#WTF?!? We already have device pci 1.1 in the section above
device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
# end
# chip drivers/generic/generic #Master MCP55 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic #Slave MCP55 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
end
end # SM
device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE
@ -162,9 +136,9 @@ chip northbridge/amd/amdk8/root_complex
device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2
device pci 6.0 on end # PCI
device pci 6.1 on end # AZA
device pci 6.1 on end # AUDIO
device pci 8.0 on end # NIC
device pci 9.0 off end # NIC
device pci 9.0 off end # N/A
device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3
@ -179,12 +153,10 @@ chip northbridge/amd/amdk8/root_complex
end
end #device pci 18.0
device pci 18.0 on end # Link 1
device pci 18.0 on end
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end # mc0
end # PCI domain
# chip drivers/generic/debug
@ -199,4 +171,5 @@ chip northbridge/amd/amdk8/root_complex
# device pnp 0.8 off end # io
# device pnp 0.9 off end # io
# end
end #root_complex