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rush: Add dp related parameters

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Add these parameters so that they can be specified in devicetree.

BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and rush

Change-Id: I77ee16263e1ce6a8c32b3cd203c1b8a499514a8e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3b254936e696f81ca7eeeb7f6968a5350352b59
Original-Change-Id: Iba47afe95c3889047a82582730be7a253fae76e7
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/238940
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9611
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jimmy Zhang
2015-01-06 11:49:34 -08:00
committed by Patrick Georgi
parent a43db197f3
commit fb391fa24c
1 changed files with 25 additions and 1 deletions
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26
src/soc/nvidia/tegra132/chip.h
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@@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright 2014 Google Inc. * Copyright 2015 Google Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -69,7 +69,31 @@ struct soc_nvidia_tegra132_config {
int refresh; /* display refresh rate */ int refresh; /* display refresh rate */
int pixel_clock; /* dc pixel clock source rate */ int pixel_clock; /* dc pixel clock source rate */
u32 panel_bits_per_pixel;
/* dp specific fields */
struct {
/* pwm to use to set display contrast */
int pwm;
/* HPD related timing */
int vdd_to_hpd_delay_ms;
int hpd_unplug_min_us;
int hpd_plug_min_us;
int hpd_irq_min_us;
/* The minimum link configuraton settings */
u32 lane_count;
u32 enhanced_framing;
u32 link_bw;
u32 drive_current;
u32 preemphasis;
u32 postcursor;
} dp;
int win_opt; int win_opt;
void *dc_data;
}; };
#endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */ #endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */