soc/intel/cannonlake: Clean up device enablement configuration
Clean up by using is_devfn_enabled(). Change-Id: I9a4984a096e72025e161bf117b70a7c59f2bb094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82118 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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committed by
Felix Singer
parent
5ed9fe9497
commit
fbf260a0d5
@@ -255,10 +255,9 @@ int soc_madt_sci_irq_polarity(int sci)
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static unsigned long soc_fill_dmar(unsigned long current)
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{
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struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
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uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
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bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
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const bool emit_igd = igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten;
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const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten;
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if (emit_igd) {
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unsigned long tmp = current;
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@@ -268,11 +267,10 @@ static unsigned long soc_fill_dmar(unsigned long current)
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acpi_dmar_drhd_fixup(tmp, current);
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}
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struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
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uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
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bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
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if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
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if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
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@@ -32,8 +32,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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* Probe for no IGD and disable InternalGfx and panel power to prevent a
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* crash in FSP-M.
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*/
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled;
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const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
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if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) {
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/* Set IGD stolen size to 64MB. */
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m_cfg->InternalGfx = 1;
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@@ -90,25 +89,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
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}
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dev = pcidev_path_on_root(PCH_DEVFN_ISH);
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/* If ISH is enabled, enable ISH elements */
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if (!dev)
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m_cfg->PchIshEnable = 0;
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else
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m_cfg->PchIshEnable = dev->enabled;
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m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH);
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/* If HDA is enabled, enable HDA elements */
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dev = pcidev_path_on_root(PCH_DEVFN_HDA);
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if (!dev)
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m_cfg->PchHdaEnable = 0;
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else
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m_cfg->PchHdaEnable = dev->enabled;
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m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
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/* Enable IPU only if the device is enabled */
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m_cfg->SaIpuEnable = 0;
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dev = pcidev_path_on_root(SA_DEVFN_IPU);
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if (dev)
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m_cfg->SaIpuEnable = dev->enabled;
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m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU);
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/* SATA Gen3 strength */
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for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) {
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@@ -136,12 +121,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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tconfig->DisableHeciRetry = config->DisableHeciRetry;
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#endif
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/* Enable SMBus controller based on config */
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dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
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if (!dev)
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m_cfg->SmbusEnable = 0;
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else
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m_cfg->SmbusEnable = dev->enabled;
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m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);
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/* Set debug probe type */
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m_cfg->PlatformDebugConsent =
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