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Intel: Move MCRS ResourceTemplate outside of _CRS method

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On Broadwell, this reduces the number of 'remarks' in the IASL build
from 222 to 3.

Fixes these remarks:
Object is not referenced (Name is within method [_CRS])

The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method.  Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.

This change was made for fsp_baytrail in commit 2eaa0d49
fsp_baytrail: Fix ACPI 'Object is not referenced' warnings

Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth 2015-08-18 16:56:05 -06:00 committed by Patrick Georgi
parent 035926c0a6
commit fc706437cb
9 changed files with 996 additions and 1005 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
View File

@ -30,9 +30,6 @@ Name(_BBN, 0)
External (BMBD)
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -123,10 +120,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
}) // End MCRS
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM

11
src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
View File

@ -239,9 +239,6 @@ Device (MCHC)
}
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -332,10 +329,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM

11
src/northbridge/intel/gm45/acpi/hostbridge.asl
View File

@ -103,9 +103,6 @@ Device (MCHC)
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -220,10 +217,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region:
// Enter actual TOLUD. The TOLUD register contains bits 20-31 of

11
src/northbridge/intel/haswell/acpi/hostbridge.asl
View File

@ -321,9 +321,6 @@ Device (MCHC)
}
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -438,10 +435,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM

11
src/northbridge/intel/i945/acpi/hostbridge.asl
View File

@ -103,9 +103,6 @@ Device (MCHC)
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -220,10 +217,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region:
// Enter actual TOLUD. The TOLUD register contains bits 27-31 of

11
src/northbridge/intel/nehalem/acpi/hostbridge.asl
View File

@ -201,9 +201,6 @@ Device (MCHC)
}
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -318,10 +315,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM

11
src/northbridge/intel/sandybridge/acpi/hostbridge.asl
View File

@ -239,9 +239,6 @@ Device (MCHC)
}
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -356,10 +353,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM

11
src/northbridge/intel/sch/acpi/hostbridge.asl
View File

@ -103,9 +103,6 @@ Device (MCHC)
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -220,10 +217,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region:
// Enter actual TOLUD. The TOLUD register contains bits 27-31 of

11
src/soc/intel/broadwell/acpi/systemagent.asl
View File

@ -43,9 +43,6 @@ Device (MCHC)
}
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
Name (MCRS, ResourceTemplate()
{
// Bus Numbers
@ -160,10 +157,12 @@ Method (_CRS, 0, Serialized)
0x00005000,,, TPMR)
})
Method (_CRS, 0, Serialized)
{
// Find PCI resource area in MCRS
CreateDwordField(MCRS, PM01._MIN, PMIN)
CreateDwordField(MCRS, PM01._MAX, PMAX)
CreateDwordField(MCRS, PM01._LEN, PLEN)
CreateDwordField(MCRS, ^PM01._MIN, PMIN)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
// Fix up PCI memory region
// Start with Top of Lower Usable DRAM