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Casually disable TBT RTD3

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Change-Id: Ia20aded6de9769d9e69a374e67b7ceb569169bc5
This commit is contained in:
Jeremy Soller
2020-12-03 20:39:14 -07:00
parent 8d4dd30363
commit fd716f3457
1 changed files with 6 additions and 6 deletions
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12
src/soc/intel/tigerlake/acpi/tcss.asl
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@@ -635,13 +635,13 @@ Scope (\_SB.PCI0)
Method (_ON, 0) Method (_ON, 0)
{ {
TG0N() //TODO TG0N()
} }
Method (_OFF, 0) Method (_OFF, 0)
{ {
If (\_SB.PCI0.TDM0.SD3C == 0) { If (\_SB.PCI0.TDM0.SD3C == 0) {
TG0F() //TODO TG0F()
} }
} }
} }
@@ -655,13 +655,13 @@ Scope (\_SB.PCI0)
Method (_ON, 0) Method (_ON, 0)
{ {
TG1N() //TODO TG1N()
} }
Method (_OFF, 0) Method (_OFF, 0)
{ {
If (\_SB.PCI0.TDM1.SD3C == 0) { If (\_SB.PCI0.TDM1.SD3C == 0) {
TG1F() //TODO TG1F()
} }
} }
} }
@@ -766,13 +766,13 @@ Scope (\_SB.PCI0)
Method (_ON, 0) Method (_ON, 0)
{ {
\_SB.PCI0.TCON() //TODO \_SB.PCI0.TCON()
STAT = 1 STAT = 1
} }
Method (_OFF, 0) Method (_OFF, 0)
{ {
\_SB.PCI0.TCOF() //TODO \_SB.PCI0.TCOF()
STAT = 0 STAT = 0
} }
} }