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AGESA f12 vendorcode: Remove unused sources

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Change-Id: Ia22c96ee19babb3fc64d57966ea923eb5ec4b48f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki 2017-08-29 13:08:43 +03:00
parent c87c6e68a3
commit fd77d714f9
231 changed files with 0 additions and 36015 deletions
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81
src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaEnv.c
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@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH HD Audio Controller
*
* Init Azalia Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 47028 $ @e \$Date: 2011-02-15 03:00:55 +0800 (Tue, 15 Feb 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_AZALIA_AZALIAENV_FILECODE
//
// Declaration of local functions
//
/**
* FchInitEnvAzalia - Config Azalia controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAzalia (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, 0);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, BIT0);
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG4C, AccessWidth8, ~BIT0, BIT0, StdHeader);
if ( LocalCfgPtr->Azalia.AzaliaMsiEnable) {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG44, AccessWidth32, ~BIT8, BIT8, StdHeader);
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG60, AccessWidth32, ~BIT16, BIT16, StdHeader);
}
}
}

59
src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaLate.c
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@ -1,59 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH HD Audio Controller
*
* Init Azalia Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_AZALIA_AZALIALATE_FILECODE
/**
* FchInitLateAzalia - Prepare Azalia controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateAzalia (
IN VOID *FchDataPtr
)
{
}

528
src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaMid.c
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@ -1,528 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH HD Audio Controller
*
* Init Azalia Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 47028 $ @e \$Date: 2011-02-15 03:00:55 +0800 (Tue, 15 Feb 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_AZALIA_AZALIAMID_FILECODE
//
// Declaration of local functions
//
VOID
ConfigureAzaliaPinCmd (
IN FCH_DATA_BLOCK *FchDataPtr,
IN UINT32 BAR0,
IN UINT8 ChannelNum
);
VOID
ConfigureAzaliaSetConfigD4Dword (
IN CODEC_ENTRY *TempAzaliaCodecEntryPtr,
IN UINT32 ChannelNumDword,
IN UINT32 BAR0,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* FchInitMidAzalia - Config Azalia controller after PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidAzalia (
IN VOID *FchDataPtr
)
{
UINT8 Data;
UINT8 Index;
BOOLEAN EnableAzalia;
UINT32 PinRouting;
UINT8 ChannelNum;
UINT8 AzaliaTempVariableByte;
UINT16 AzaliaTempVariableWord;
UINT32 BAR0;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
EnableAzalia = FALSE;
ChannelNum = 0;
AzaliaTempVariableByte = 0;
AzaliaTempVariableWord = 0;
BAR0 = 0;
if ( LocalCfgPtr->Azalia.AzaliaEnable == AzDisable ) {
return;
} else {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG04, AccessWidth8, ~BIT1, BIT1, StdHeader);
if ( LocalCfgPtr->Azalia.AzaliaSsid != NULL ) {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Azalia.AzaliaSsid, StdHeader);
}
ReadPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG10, AccessWidth32, &BAR0, StdHeader);
if ( BAR0 != 0 ) {
if ( BAR0 != 0xFFFFFFFF ) {
BAR0 &= ~(0x03FFF);
EnableAzalia = TRUE;
}
}
}
if ( EnableAzalia ) {
//
// Get SDIN Configuration
//
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG167, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG168, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG169, AccessWidth8, 0, 0x01);
}
if ( LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3 == 2 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x00);
} else {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG170, AccessWidth8, 0, 0x01);
}
//
// INT#A Azalia resource
//
Data = 0x93; /// Azalia APIC index
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader);
Data = 0x10; /// IRQ16 (INTA#)
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader);
Index = 11;
do {
ReadMem ( BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
AzaliaTempVariableByte |= BIT0;
WriteMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
FchStall (1000, StdHeader);
ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
Index--;
} while ((! (AzaliaTempVariableByte & BIT0)) && (Index > 0) );
if ( Index == 0 ) {
return;
}
FchStall (1000, StdHeader);
ReadMem ( BAR0 + FCH_AZ_BAR_REG0E, AccessWidth16, &AzaliaTempVariableWord);
if ( AzaliaTempVariableWord & 0x0F ) {
//
//at least one azalia codec found
//
//PinRouting = LocalCfgPtr->Azalia.AZALIA_CONFIG.AzaliaSdinPin;
//new structure need make up PinRouting
//need adjust later!!!
//
PinRouting = 0;
PinRouting = (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin3;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin2;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin1;
PinRouting <<= 8;
PinRouting |= (UINT32 )LocalCfgPtr->Azalia.AzaliaConfig.AzaliaSdin0;
do {
if ( ( ! (PinRouting & BIT0) ) && (PinRouting & BIT1) ) {
ConfigureAzaliaPinCmd (LocalCfgPtr, BAR0, ChannelNum);
}
PinRouting >>= 8;
ChannelNum++;
} while ( ChannelNum != 4 );
} else {
//
//No Azalia codec found
//
if ( LocalCfgPtr->Azalia.AzaliaEnable != AzEnable ) {
EnableAzalia = FALSE; ///set flag to disable Azalia
}
}
}
if ( EnableAzalia ) {
//
//redo clear reset
//
do {
AzaliaTempVariableWord = 0;
WriteMem ( BAR0 + FCH_AZ_BAR_REG0C, AccessWidth16, &AzaliaTempVariableWord);
ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
AzaliaTempVariableByte &= ~(BIT0);
WriteMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
ReadMem (BAR0 + FCH_AZ_BAR_REG08, AccessWidth8, &AzaliaTempVariableByte);
} while ( AzaliaTempVariableByte & BIT0 );
if ( LocalCfgPtr->Azalia.AzaliaSnoop == 1 ) {
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG42, AccessWidth8, 0xFF, BIT1 + BIT0, StdHeader);
}
} else {
//
//disable Azalia controller
//
RwPci ((AZALIA_BUS_DEV_FUN << 16) + FCH_AZ_REG04, AccessWidth16, 0, 0, StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGEB, AccessWidth8, ~BIT0, 0);
}
}
/**
* Pin Config for ALC880, ALC882 and ALC883.
*
*
*
*/
CODEC_ENTRY AzaliaCodecAlc882Table[] =
{
{0x14, 0x01014010},
{0x15, 0x01011012},
{0x16, 0x01016011},
{0x17, 0x01012014},
{0x18, 0x01A19030},
{0x19, 0x411111F0},
{0x1a, 0x01813080},
{0x1b, 0x411111F0},
{0x1C, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x01441150},
{0x1f, 0x01C46160},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0262.
*
*
*
*/
CODEC_ENTRY AzaliaCodecAlc262Table[] =
{
{0x14, 0x01014010},
{0x15, 0x411111F0},
{0x16, 0x411111F0},
{0x18, 0x01A19830},
{0x19, 0x02A19C40},
{0x1a, 0x01813031},
{0x1b, 0x02014C20},
{0x1c, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x0144111E},
{0x1f, 0x01C46150},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0269.
*
*
*
*/
CODEC_ENTRY AzaliaCodecAlc269Table[] =
{
{0x12, 0x99A308F0},
{0x14, 0x99130010},
{0x15, 0x0121101F},
{0x16, 0x99036120},
{0x18, 0x01A19850},
{0x19, 0x99A309F0},
{0x1a, 0x01813051},
{0x1b, 0x0181405F},
{0x1d, 0x40134601},
{0x1e, 0x01442130},
{0x11, 0x99430140},
{0x20, 0x0030FFFF},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0861.
*
*
*
*/
CODEC_ENTRY AzaliaCodecAlc861Table[] =
{
{0x01, 0x8086C601},
{0x0B, 0x01014110},
{0x0C, 0x01813140},
{0x0D, 0x01A19941},
{0x0E, 0x411111F0},
{0x0F, 0x02214420},
{0x10, 0x02A1994E},
{0x11, 0x99330142},
{0x12, 0x01451130},
{0x1F, 0x411111F0},
{0x20, 0x411111F0},
{0x23, 0x411111F0},
{0xff, 0xffffffff}
};
/**
* Pin Config for ALC0889.
*
*
*
*/
CODEC_ENTRY AzaliaCodecAlc889Table[] =
{
{0x11, 0x411111F0},
{0x14, 0x01014010},
{0x15, 0x01011012},
{0x16, 0x01016011},
{0x17, 0x01013014},
{0x18, 0x01A19030},
{0x19, 0x411111F0},
{0x1a, 0x411111F0},
{0x1b, 0x411111F0},
{0x1C, 0x411111F0},
{0x1d, 0x411111F0},
{0x1e, 0x01442150},
{0x1f, 0x01C42160},
{0xff, 0xffffffff}
};
/**
* Pin Config for ADI1984.
*
*
*
*/
CODEC_ENTRY AzaliaCodecAd1984Table[] =
{
{0x11, 0x0221401F},
{0x12, 0x90170110},
{0x13, 0x511301F0},
{0x14, 0x02A15020},
{0x15, 0x50A301F0},
{0x16, 0x593301F0},
{0x17, 0x55A601F0},
{0x18, 0x55A601F0},
{0x1A, 0x91F311F0},
{0x1B, 0x014511A0},
{0x1C, 0x599301F0},
{0xff, 0xffffffff}
};
/**
* FrontPanel Config table list
*
*
*
*/
CODEC_ENTRY FrontPanelAzaliaCodecTableList[] =
{
{0x19, 0x02A19040},
{0x1b, 0x02214020},
{0xff, 0xffffffff}
};
/**
* Current HD Audio support codec list
*
*
*
*/
CODEC_TBL_LIST AzaliaCodecTableList[] =
{
{0x010ec0880, &AzaliaCodecAlc882Table[0]},
{0x010ec0882, &AzaliaCodecAlc882Table[0]},
{0x010ec0883, &AzaliaCodecAlc882Table[0]},
{0x010ec0885, &AzaliaCodecAlc882Table[0]},
{0x010ec0889, &AzaliaCodecAlc889Table[0]},
{0x010ec0262, &AzaliaCodecAlc262Table[0]},
{0x010ec0269, &AzaliaCodecAlc269Table[0]},
{0x010ec0861, &AzaliaCodecAlc861Table[0]},
{0x011d41984, &AzaliaCodecAd1984Table[0]},
{ (UINT32) 0x0FFFFFFFF, (CODEC_ENTRY*) (UINTN)0x0FFFFFFFF}
};
/**
* ConfigureAzaliaPinCmd - Configuration HD Audio PIN Command
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] BAR0 HD Audio BAR0 base address.
* @param[in] ChannelNum Channel Number.
*
*/
VOID
ConfigureAzaliaPinCmd (
IN FCH_DATA_BLOCK *FchDataPtr,
IN UINT32 BAR0,
IN UINT8 ChannelNum
)
{
UINT32 AzaliaTempVariable;
UINT32 ChannelNumDword;
CODEC_TBL_LIST *TempAzaliaOemCodecTablePtr;
CODEC_ENTRY *TempAzaliaCodecEntryPtr;
if ( (FchDataPtr->Azalia.AzaliaPinCfg) != 1 ) {
return;
}
ChannelNumDword = ChannelNum << 28;
AzaliaTempVariable = 0xF0000;
AzaliaTempVariable |= ChannelNumDword;
WriteMem (BAR0 + FCH_AZ_BAR_REG60, AccessWidth32, &AzaliaTempVariable);
FchStall (600, FchDataPtr->StdHeader);
ReadMem (BAR0 + FCH_AZ_BAR_REG64, AccessWidth32, &AzaliaTempVariable);
if ( ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == ((CODEC_TBL_LIST*) (UINTN)0xFFFFFFFF))) {
TempAzaliaOemCodecTablePtr = (CODEC_TBL_LIST*) (&AzaliaCodecTableList[0]);
} else {
TempAzaliaOemCodecTablePtr = (CODEC_TBL_LIST*) FchDataPtr->Azalia.AzaliaOemCodecTablePtr;
}
while ( TempAzaliaOemCodecTablePtr->CodecId != 0xFFFFFFFF ) {
if ( TempAzaliaOemCodecTablePtr->CodecId == AzaliaTempVariable ) {
break;
} else {
++TempAzaliaOemCodecTablePtr;
}
}
if ( TempAzaliaOemCodecTablePtr->CodecId != 0xFFFFFFFF ) {
TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) TempAzaliaOemCodecTablePtr->CodecTablePtr;
if ( ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemCodecTablePtr) == ((CODEC_TBL_LIST*) (UINTN)0xFFFFFFFF)) ) {
TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) (TempAzaliaCodecEntryPtr);
}
ConfigureAzaliaSetConfigD4Dword (TempAzaliaCodecEntryPtr, ChannelNumDword, BAR0, FchDataPtr->StdHeader);
if ( FchDataPtr->Azalia.AzaliaFrontPanel != 1 ) {
if ( (FchDataPtr->Azalia.AzaliaFrontPanel == 2) || (FchDataPtr->Azalia.FrontPanelDetected == 1) ) {
if ( ((FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr) == NULL) || ((FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {
TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) (&FrontPanelAzaliaCodecTableList[0]);
} else {
TempAzaliaCodecEntryPtr = (CODEC_ENTRY*) FchDataPtr->Azalia.AzaliaOemFpCodecTablePtr;
}
ConfigureAzaliaSetConfigD4Dword (TempAzaliaCodecEntryPtr, ChannelNumDword, BAR0, FchDataPtr->StdHeader);
}
}
}
}
/**
* ConfigureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table
*
*
* @param[in] TempAzaliaCodecEntryPtr HD Audio Codec table structure pointer.
* @param[in] ChannelNumDword HD Audio Channel Number.
* @param[in] BAR0 HD Audio BAR0 base address.
* @param[in] StdHeader
*
*/
VOID
ConfigureAzaliaSetConfigD4Dword (
IN CODEC_ENTRY *TempAzaliaCodecEntryPtr,
IN UINT32 ChannelNumDword,
IN UINT32 BAR0,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 TempByte1;
UINT8 TempByte2;
UINT8 Index;
UINT32 TempDword1;
UINT32 TempDword2;
TempDword1 = 0;
TempDword2 = 0;
while ( (TempAzaliaCodecEntryPtr->Nid) != 0xFF ) {
TempByte1 = 0x20;
if ( (TempAzaliaCodecEntryPtr->Nid) == 0x1 ) {
TempByte1 = 0x24;
}
TempDword1 = TempAzaliaCodecEntryPtr->Nid;
TempDword1 &= 0xff;
TempDword1 <<= 20;
TempDword1 |= ChannelNumDword;
TempDword1 |= (0x700 << 8);
for ( Index = 4; Index > 0; Index-- ) {
do {
ReadMem (BAR0 + FCH_AZ_BAR_REG68, AccessWidth32, &TempDword2);
} while ( (TempDword2 & BIT0) != 0 );
TempByte2 = (UINT8) (( (TempAzaliaCodecEntryPtr->Byte40) >> ((4 - Index) * 8 ) ) & 0xff);
TempDword1 = (TempDword1 & 0xFFFF0000) + ((TempByte1 - Index) << 8) + TempByte2;
WriteMem (BAR0 + FCH_AZ_BAR_REG60, AccessWidth32, &TempDword1);
FchStall (60, StdHeader);
}
++TempAzaliaCodecEntryPtr;
}
}

77
src/vendorcode/amd/agesa/f12/Proc/Fch/Azalia/AzaliaReset.c
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH HD Audio Controller
*
* Init Azalia Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_AZALIA_AZALIARESET_FILECODE
/**
* FchInitResetAzalia - Config Azalia controller during Power-On
*
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchInitResetAzalia (
IN VOID *FchDataPtr
)
{
}
/**
* FchInitRecoveryAzalia - Config Azalia controller during
* Crisis Recovery
*
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchInitRecoveryAzalia (
IN VOID *FchDataPtr
)
{
}

231
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@ -1,231 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH ACPI lib
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_ACPILIB_FILECODE
//
//
// Routine Description:
//
// Locate ACPI table
//
// Arguments:
//
// Signature - table signature
//
//Returns:
//
// pointer to ACPI table
//
//
VOID*
AcpiLocateTable (
IN UINT32 Signature
)
{
UINT32 Index;
UINT32 *RsdPtr;
UINT32 *Rsdt;
UINTN TableOffset;
DESCRIPTION_HEADER *CurrentTable;
RsdPtr = (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_LOW;
Rsdt = NULL;
do {
if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) {
Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress;
break;
}
RsdPtr += 4;
} while ( RsdPtr <= (UINT32*) (UINTN) FCHOEM_ACPI_TABLE_RANGE_HIGH );
if ( Rsdt != NULL && AcpiGetTableCheckSum (Rsdt) == 0 ) {
for ( Index = 0; Index < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; Index++ ) {
TableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + Index * 4);
CurrentTable = (DESCRIPTION_HEADER*)TableOffset;
if ( CurrentTable->Signature == Signature ) {
return CurrentTable;
}
}
}
return NULL;
}
//
//
// Routine Description:
//
// Update table CheckSum
//
// Arguments:
//
// TablePtr - table pointer
//
// Returns:
//
// none
//
//
VOID
AcpiSetTableCheckSum (
IN VOID *TablePtr
)
{
UINT8 CheckSum;
CheckSum = 0;
((DESCRIPTION_HEADER*)TablePtr)->CheckSum = 0;
CheckSum = AcpiGetTableCheckSum (TablePtr);
((DESCRIPTION_HEADER*)TablePtr)->CheckSum = (UINT8) (FCHOEM_ACPI_BYTE_CHECHSUM - CheckSum);
}
//
//
// Routine Description:
//
// Get table CheckSum - Get ACPI table checksum
//
// Arguments:
//
// TablePtr - table pointer
//
// Returns:
//
// none
//
//
UINT8
AcpiGetTableCheckSum (
IN VOID *TablePtr
)
{
return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);
}
//
//
// Routine Description:
//
// GetByteSum - Get BYTE checksum value
//
// Arguments:
//
// DataPtr - table pointer
// Length - table length
//
// Returns:
//
// CheckSum - CheckSum value
//
//
UINT8
GetByteSum (
IN VOID *DataPtr,
IN UINT32 Length
)
{
UINT32 Index;
UINT8 CheckSum;
CheckSum = 0;
for ( Index = 0; Index < Length; Index++ ) {
CheckSum = CheckSum + (*((UINT8*)DataPtr + Index));
}
return CheckSum;
}
//
//
// Routine Description:
//
// GetFchAcpiMmioBase - Get FCH HwAcpi MMIO Base Address
//
// Arguments:
//
// AcpiMmioBase - HwAcpi MMIO Base Address
// StdHeader - Amd Stand Header
//
// Returns:
//
// AcpiMmioBase - HwAcpi MMIO Base Address
//
//
VOID
GetFchAcpiMmioBase (
OUT UINT32 *AcpiMmioBase,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 AcpiMmioBaseAddressDword;
ReadPmio (FCH_PMIOA_REG24 + 2, AccessWidth16, &AcpiMmioBaseAddressDword, StdHeader);
*AcpiMmioBase = AcpiMmioBaseAddressDword << 16;
}
//
//
// Routine Description:
//
// GetFchAcpiPmBase - Get FCH HwAcpi PM Base Address
//
// Arguments:
//
// AcpiPmBase - HwAcpi PM Base Address
// StdHeader - Amd Stand Header
//
// Returns:
//
// AcpiPmBase - HwAcpi PM Base Address
//
//
VOID
GetFchAcpiPmBase (
OUT UINT16 *AcpiPmBase,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
ReadPmio (FCH_PMIOA_REG60, AccessWidth16, AcpiPmBase, StdHeader);
}

87
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@ -1,87 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH ACPI lib
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
///
/// RSDP - ACPI 2.0 table RSDP
///
typedef struct _RSDP_HEADER {
UINT64 Signature; ///< RSDP signature "RSD PTR"
UINT8 CheckSum; ///< checksum of the first 20 bytes
UINT8 OEMID[6]; ///< OEM ID
UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
UINT32 RsdtAddress; ///< physical address of RSDT
UINT32 Length; ///< total length of RSDP (including extended part)
UINT64 XsdtAddress; ///< physical address of XSDT
UINT8 ExtendedCheckSum; ///< chechsum of whole table
UINT8 Reserved[3]; ///< Reserved
} RSDP_HEADER;
///
/// DESCRIPTION_HEADER - ACPI common table header
///
typedef struct _DESCRIPTION_HEADER {
UINT32 Signature; ///< ACPI signature (4 ASCII characters)
UINT32 Length; ///< Length of table, in bytes, including header
UINT8 Revision; ///< ACPI Specification minor version #
UINT8 CheckSum; ///< To make sum of entire table == 0
UINT8 OemId[6]; ///< OEM identification
UINT8 OemTableId[8]; ///< OEM table identification
UINT32 OemRevision; ///< OEM revision number
UINT32 CreatorId; ///< ASL compiler vendor ID
UINT32 CreatorRevision; ///< ASL compiler revision number
} DESCRIPTION_HEADER;
///
/// _AcpiRegWrite - ACPI MMIO register R/W structure
///
typedef struct _ACPI_REG_WRITE {
UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
UINT8 MmioReg; /// MmioReg : Register index
UINT8 DataAndMask; /// DataANDMask : AND Register Data
UINT8 DataOrMask; /// DataOrMask : Or Register Data
} ACPI_REG_WRITE;
VOID* AcpiLocateTable (IN UINT32 Signature);
VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);

67
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchBiosRamUsage.h
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@ -1,67 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH BIOS Ram usage
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#ifndef _FCH_BIOS_RAM_USAGE_H_
#define _FCH_BIOS_RAM_USAGE_H_
#define RESTORE_MEMORY_CONTROLLER_START 0
#define XHCI_REGISTER_BAR00 0xD0
#define XHCI_REGISTER_BAR01 0xD1
#define XHCI_REGISTER_BAR02 0xD2
#define XHCI_REGISTER_BAR03 0xD3
#define XHCI_REGISTER_04H 0xD4
#define XHCI_REGISTER_0CH 0xD5
#define XHCI_REGISTER_3CH 0xD6
#define XHCI1_REGISTER_BAR00 0xE0
#define XHCI1_REGISTER_BAR01 0xE1
#define XHCI1_REGISTER_BAR02 0xE2
#define XHCI1_REGISTER_BAR03 0xE3
#define XHCI1_REGISTER_04H 0xE4
#define XHCI1_REGISTER_0CH 0xE5
#define XHCI1_REGISTER_3CH 0xE6
#define RTC_WORKAROUND_DATA_START 0xF0
#define BOOT_TIME_FLAG_SEC 0xF8
#define BOOT_TIME_FLAG_INT19 0xFC
#endif

47
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommon.c
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@ -1,47 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH common
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "heapManager.h"
#define FILECODE PROC_FCH_COMMON_FCHCOMMON_FILECODE

1092
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonCfg.h
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71
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchCommonSmm.c
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@ -1,71 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH common SMM
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE
/*----------------------------------------------------------------------------------------*/
/**
* FchSmmAcpiOn - Config Fch during ACPI_ON
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchSmmAcpiOn (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
//
// Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest
// recommendation. This is required to fix the keyboard stuck issue when playing games under Windows
//
//
// Disable Power Button SMI
//
RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGAC, AccessWidth8, ~(BIT6), 0);
}

444
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@ -1,444 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH routine definition
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 45638 $ @e \$Date: 2011-01-20 03:17:37 +0800 (Thu, 20 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#ifndef _FCH_DEF_H_
#define _FCH_DEF_H_
UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
///
/// Fch Ab Routines
///
/// Pei Phase
///
VOID FchInitResetAb (IN VOID* FchDataPtr);
VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvAb (IN VOID* FchDataPtr);
VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
VOID FchInitMidAb (IN VOID* FchDataPtr);
VOID FchInitLateAb (IN VOID* FchDataPtr);
///
/// Other Public Routines
///
VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
///
/// Fch Pcie Routines
///
/// Pei Phase
///
VOID FchInitResetPcie (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvPcie (IN VOID* FchDataPtr);
VOID FchInitMidPcie (IN VOID* FchDataPtr);
VOID FchInitLatePcie (IN VOID* FchDataPtr);
VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
///
/// Fch Gpp Routines
///
/// Pei Phase
///
VOID FchInitResetGpp (IN VOID* FchDataPtr);
VOID ProgramFchGppInitReset (IN VOID *FchDataPtr);
VOID FchResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader);
///
/// Dxe Phase
///
VOID FchInitEnvGpp (IN VOID* FchDataPtr);
VOID FchInitMidGpp (IN VOID* FchDataPtr);
VOID FchInitLateGpp (IN VOID* FchDataPtr);
///
/// Other Public Routines
///
VOID ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppForceGen1 (IN VOID* FchDataPtr, IN CONST UINT8 ActivePorts);
VOID FchGppForceGen2 (IN VOID* FchDataPtr, IN CONST UINT8 ActivePorts);
VOID FchGppDynamicPowerSaving (IN VOID* FchDataPtr );
UINT8 GppPortPollingLtssm (IN VOID* FchDataPtr, IN UINT8 ActivePorts, IN BOOLEAN IsGen2);
///
/// Fch Azalia Routines
///
/// Pei Phase
///
VOID FchInitResetAzalia (IN VOID *FchDataPtr);
VOID FchInitRecoveryAzalia (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
VOID FchInitMidAzalia (IN VOID *FchDataPtr);
VOID FchInitLateAzalia (IN VOID *FchDataPtr);
///
/// Fch GEC Routines
///
/// Pei Phase
///
VOID FchInitResetGec (IN VOID* FchDataPtr);
VOID FchInitRecoveryGec (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvGec (IN VOID* FchDataPtr);
VOID FchInitMidGec (IN VOID* FchDataPtr);
VOID FchInitLateGec (IN VOID* FchDataPtr);
///
/// Other Public Routines
///
VOID FchInitGecController (IN VOID* FchDataPtr);
VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
///
/// Fch HwAcpi Routines
///
/// Pei Phase
///
VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
VOID FchInitRecoveryHwAcpi (IN VOID *FchDataPtr);
VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
///
/// Other Public Routines
///
VOID HpetInit (IN VOID *FchDataPtr);
VOID C3PopupSetting (IN VOID *FchDataPtr);
VOID MtC1eEnable (IN VOID *FchDataPtr);
VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
VOID StressResetModeLate (IN VOID *FchDataPtr);
///
/// Fch Hwm Routines
///
/// Pei Phase
///
VOID FchInitResetHwm (IN VOID* FchDataPtr);
VOID FchInitRecoveryHwm (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvHwm (IN VOID* FchDataPtr);
VOID FchInitMidHwm (IN VOID* FchDataPtr);
VOID FchInitLateHwm (IN VOID* FchDataPtr);
///
/// Other Public Routines
///
VOID HwmInitRegister (IN VOID* FchDataPtr);
VOID HwmProcessParameter (IN VOID* FchDataPtr);
VOID HwmSetRegister (IN VOID* FchDataPtr);
VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr);
VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
VOID HwmGetRawData (IN VOID* FchDataPtr);
VOID HwmCaculate (IN VOID* FchDataPtr);
VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr);
VOID FchECfancontrolservice (IN VOID* FchDataPtr);
///
/// Fch Ide Routines
///
VOID FchInitEnvIde (IN VOID* FchDataPtr);
VOID FchInitMidIde (IN VOID* FchDataPtr);
VOID FchInitLateIde (IN VOID* FchDataPtr);
///
/// Fch Imc Routines
///
/// Pei Phase
///
VOID FchInitResetImc (IN VOID *FchDataPtr);
VOID FchInitRecoveryImc (IN VOID *FchDataPtr);
VOID FchInitResetEc (IN VOID *FchDataPtr);
VOID FchInitRecoveryEc (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvImc (IN VOID *FchDataPtr);
VOID FchInitMidImc (IN VOID *FchDataPtr);
VOID FchInitLateImc (IN VOID *FchDataPtr);
VOID FchInitEnvEc (IN VOID *FchDataPtr);
VOID FchInitMidEc (IN VOID *FchDataPtr);
VOID FchInitLateEc (IN VOID *FchDataPtr);
///
/// Other Public Routines
///
VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
VOID ImcSleep (IN VOID *FchDataPtr);
VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr);
VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
VOID ImcWakeup (IN VOID *FchDataPtr);
VOID ImcIdle (IN VOID *FchDataPtr);
BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
///
/// Fch Ir Routines
///
/// Dxe Phase
///
VOID FchInitEnvIr (IN VOID* FchDataPtr);
VOID FchInitMidIr (IN VOID* FchDataPtr);
VOID FchInitLateIr (IN VOID* FchDataPtr);
///
/// Fch Pcib Routines
///
/// Pei Phase
///
VOID FchInitResetPcib (IN VOID* FchDataPtr);
VOID FchInitRecoveryPcib (IN VOID* FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvPcib (IN VOID* FchDataPtr);
VOID FchInitMidPcib (IN VOID* FchDataPtr);
VOID FchInitLatePcib (IN VOID* FchDataPtr);
///
/// Fch SATA Routines
///
/// Pei Phase
///
VOID FchInitResetSata (IN VOID *FchDataPtr);
VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitMidSata (IN VOID *FchDataPtr);
VOID FchInitEnvSata (IN VOID *FchDataPtr);
VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
VOID FchInitLateSata (IN VOID *FchDataPtr);
VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
VOID FchInitMidSataIde (IN VOID *FchDataPtr);
VOID FchInitLateSataIde (IN VOID *FchDataPtr);
VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
VOID FchSataGpioInitial (IN VOID *FchDataPtr);
VOID SataBar5RegSet (IN VOID *FchDataPtr);
VOID SataSetPortGenMode (IN VOID *FchDataPtr);
VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchSataDriveFpga (IN VOID *FchDataPtr);
///
/// FCH USB Controller Public Function
///
/// Pei Phase
///
VOID FchInitResetUsb (IN VOID *FchDataPtr);
VOID FchInitRecoveryUsb (IN VOID *FchDataPtr);
VOID FchInitResetOhci (IN VOID *FchDataPtr);
VOID FchInitRecoveryOhci (IN VOID *FchDataPtr);
VOID FchInitResetEhci (IN VOID *FchDataPtr);
VOID FchInitRecoveryEhci (IN VOID *FchDataPtr);
VOID FchInitResetXhci (IN VOID *FchDataPtr);
VOID FchInitRecoveryXhci (IN VOID *FchDataPtr);
VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvUsb (IN VOID *FchDataPtr);
VOID FchInitMidUsb (IN VOID *FchDataPtr);
VOID FchInitLateUsb (IN VOID *FchDataPtr);
VOID FchInitEnvUsbOhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci (IN VOID *FchDataPtr);
VOID FchInitLateUsbOhci (IN VOID *FchDataPtr);
VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci1 (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci2 (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci3 (IN VOID *FchDataPtr);
VOID FchInitMidUsbOhci4 (IN VOID *FchDataPtr);
VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr);
///
/// Other Public Routines
///
VOID SetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchXhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
///
/// Fch Sd Routines
///
VOID FchInitEnvSd (IN VOID *FchDataPtr);
VOID FchInitMidSd (IN VOID *FchDataPtr);
VOID FchInitLateSd (IN VOID *FchDataPtr);
///
/// Fch Spi Routines
///
/// Pei Phase
///
VOID FchInitResetSpi (IN VOID *FchDataPtr);
VOID FchInitRecoverySpi (IN VOID *FchDataPtr);
VOID FchInitResetLpc (IN VOID *FchDataPtr);
VOID FchInitRecoveryLpc (IN VOID *FchDataPtr);
///
/// Dxe Phase
///
VOID FchInitEnvSpi (IN VOID *FchDataPtr);
VOID FchInitMidSpi (IN VOID *FchDataPtr);
VOID FchInitLateSpi (IN VOID *FchDataPtr);
VOID FchInitEnvLpc (IN VOID *FchDataPtr);
VOID FchInitMidLpc (IN VOID *FchDataPtr);
VOID FchInitLateLpc (IN VOID *FchDataPtr);
///
/// Other Public Routines
///
VOID FchSpiUnlock (IN VOID *FchDataPtr);
VOID FchSpiLock (IN VOID *FchDataPtr);
/*--------------------------- Documentation Pages ---------------------------*/
VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchReset (IN AMD_CONFIG_PARAMS *StdHeader);
VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
VOID TurnOffCG2 (OUT VOID);
VOID BackUpCG2 (OUT VOID);
VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
VOID AcLossControl (IN UINT8 AcLossControlValue);
VOID FchVgaInit (OUT VOID);
VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
VOID ValidateFchVariant (IN VOID *FchDataPtr);
VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
BOOLEAN IsGCPU (IN VOID *FchDataPtr);
BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
BOOLEAN IsLpcRom (OUT VOID);
#endif

564
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchLib.c
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@ -1,564 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH IO access common routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 45638 $ @e \$Date: 2011-01-20 03:17:37 +0800 (Thu, 20 Jan 2011) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE
/**< FchStall - Reserved */
VOID
FchStall (
IN UINT32 uSec,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 timerAddr;
UINT32 startTime;
UINT32 elapsedTime;
LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
if ( timerAddr == 0 ) {
uSec = uSec / 2;
while ( uSec != 0 ) {
LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader);
uSec--;
}
} else {
LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
for ( ;; ) {
LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
if ( elapsedTime < startTime ) {
elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
} else {
elapsedTime = elapsedTime - startTime;
}
if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
break;
}
}
}
}
/**< cimFchStall - Reserved */
VOID
CimFchStall (
IN UINT32 uSec,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 timerAddr;
UINT32 startTime;
UINT32 elapsedTime;
LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
if ( timerAddr == 0 ) {
uSec = uSec / 2;
while ( uSec != 0 ) {
LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader);
uSec--;
}
} else {
LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
for ( ;; ) {
LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
if ( elapsedTime < startTime ) {
elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
} else {
elapsedTime = elapsedTime - startTime;
}
if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
break;
}
}
}
}
/**< FchReset - Reserved */
VOID
FchReset (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PciRstValue;
PciRstValue = 0x06;
LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader);
}
/**< outPort80 - Reserved */
VOID
OutPort80 (
IN UINT32 pcode,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader);
return;
}
/**< outPort1080 - Reserved */
VOID
OutPort1080 (
IN UINT32 pcode,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader);
return;
}
/**< FchCopyMem - Reserved */
VOID
FchCopyMem (
IN VOID* pDest,
IN VOID* pSource,
IN UINTN Length
)
{
UINTN i;
UINT8 *Ptr;
UINT8 *Source;
Ptr = (UINT8*)pDest;
Source = (UINT8*)pSource;
for (i = 0; i < Length; i++) {
*Ptr = *Source;
Source++;
Ptr++;
}
}
/** GetRomSigPtr - Reserved **/
VOID*
GetRomSigPtr (
IN UINTN *RomSigPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 RomPtr;
UINT32 RomSig;
UINT16 MswAddr;
*RomSigPtr = 0;
MswAddr = 0xFFF0;
do {
RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO;
LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader);
if (RomSig == FCH_ROMSIG_SIGNATURE) {
*RomSigPtr = RomPtr;
break;
}
MswAddr <<= 1;
} while (MswAddr != 0xFE00);
return RomSigPtr;
}
/** RwXhciIndReg - Reserved **/
VOID
RwXhciIndReg (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 RevReg;
PCI_ADDR PciAddress;
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
RevReg = ~AndMask;
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
RevReg = ~AndMask;
LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
}
/** AcLossControl - Reserved **/
VOID
AcLossControl (
IN UINT8 AcLossControlValue
)
{
AcLossControlValue &= 0x03;
AcLossControlValue |= BIT2;
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue);
}
/** RecordFchConfigPtr - Reserved **/
VOID
RecordFchConfigPtr (
IN UINT32 FchConfigPtr
)
{
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) );
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) );
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) );
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) );
}
/** ReadAlink - Reserved **/
UINT32
ReadAlink (
IN UINT32 Index,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Data;
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
//Clear Index
Index = 0;
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
return Data;
}
/** WriteAlink - Reserved **/
VOID
WriteAlink (
IN UINT32 Index,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
//Clear Index
Index = 0;
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
}
/** RwAlink - Reserved **/
VOID
RwAlink (
IN UINT32 Index,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 AccessType;
AccessType = Index & 0xE0000000;
if (AccessType == (AXINDC << 29)) {
WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader);
Index = FCH_AX_DATAC_REG34 | AccessType;
} else if (AccessType == (AXINDP << 29)) {
WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader);
Index = FCH_AX_DATAP_REG3C | AccessType;
}
WriteAlink (Index, ReadAlink (Index, StdHeader) & AndMask | OrMask, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadPmio (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
Address++;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WritePmio (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
Address++;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RwPmio - Read/Write PMIO
*
*
*
* @param[in] Address - PMIO Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
* @param[in] StdHeader
*
*/
VOID
RwPmio (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Result;
ReadPmio (Address, OpFlag, &Result, StdHeader);
Result = (Result & AndMask) | OrMask;
WritePmio (Address, OpFlag, &Result, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadPmio2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for ( i = 0; i < OpFlag; i++ ) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
Address++;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write PMIO 2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WritePmio2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for ( i = 0; i < OpFlag; i++ ) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
Address++;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* RwPmio2 - Read/Write PMIO2
*
*
*
* @param[in] Address - PMIO2 Offset value
* @param[in] OpFlag - Access sizes
* @param[in] AndMask - Data And Mask 32 bits
* @param[in] OrMask - Data OR Mask 32 bits
* @param[in] StdHeader
*
*/
VOID
RwPmio2 (
IN UINT8 Address,
IN UINT8 OpFlag,
IN UINT32 AndMask,
IN UINT32 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 Result;
ReadPmio2 (Address, OpFlag, &Result, StdHeader);
Result = (Result & AndMask) | OrMask;
WritePmio2 (Address, OpFlag, &Result, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read BIOSRAM
*
*
*
* @param[in] Address - BIOSRAM Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadBiosram (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
Address++;
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Write BIOSRAM
*
*
*
* @param[in] Address - BIOSRAM Offset value
* @param[in] OpFlag - Access sizes
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WriteBiosram (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
OpFlag = OpFlag & 0x7f;
OpFlag = 1 << (OpFlag - 1);
for (i = 0; i < OpFlag; i++) {
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
Address++;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Record SMI Status
*
*
* @param[in] StdHeader
*
*/
VOID
RecordSmiStatus (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINTN Index;
UINT8 SwSmiValue;
ACPIMMIO8 (0xfed80320) |= 0x01;
for ( Index = 0; Index < 20; Index++ ) {
ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index);
}
LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader);
ACPIMMIO8 (0xfed10040) = SwSmiValue;
}

196
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/FchPeLib.c
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@ -1,196 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH IO access common routine
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
/*----------------------------------------------------------------------------------------*/
/**
* ProgramPciByteTable - Program PCI register by table (8 bits data)
*
*
*
* @param[in] pPciByteTable - Table data pointer
* @param[in] dwTableSize - Table length
* @param[in] StdHeader
*
*/
VOID
ProgramPciByteTable (
IN REG8_MASK *pPciByteTable,
IN UINT16 dwTableSize,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 dbBusNo;
UINT8 dbDevFnNo;
UINT8 Or8;
UINT8 Mask8;
PCI_ADDR PciAddress;
dbBusNo = pPciByteTable->RegIndex;
dbDevFnNo = pPciByteTable->AndMask;
pPciByteTable++;
for ( i = 1; i < dwTableSize; i++ ) {
if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) {
pPciByteTable++;
dbBusNo = pPciByteTable->RegIndex;
dbDevFnNo = pPciByteTable->AndMask;
pPciByteTable++;
i++;
} else {
PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex;
Or8 = pPciByteTable->OrMask;
Mask8 = ~pPciByteTable->AndMask;
LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader);
pPciByteTable++;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
*
*
*
* @param[in] pAcpiTbl - Table data pointer
* @param[in] StdHeader
*
*/
VOID
ProgramFchAcpiMmioTbl (
IN ACPI_REG_WRITE *pAcpiTbl,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 i;
UINT8 Or8;
UINT8 Mask8;
UINT32 ddtempVar;
if (pAcpiTbl != NULL) {
if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
// Signature Checking
pAcpiTbl++;
for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
Or8 = pAcpiTbl->DataOrMask;
Mask8 = ~pAcpiTbl->DataAndMask;
LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader);
pAcpiTbl++;
}
}
}
}
/**
* GetChipSysMode - Get Chip status
*
*
* @param[in] Value - Return Chip strap status
* StrapStatus [15.0] - Hudson-2 chip Strap Status
* @li <b>0001</b> - Not USED FWH
* @li <b>0002</b> - Not USED LPC ROM
* @li <b>0004</b> - EC enabled
* @li <b>0008</b> - Reserved
* @li <b>0010</b> - Internal Clock mode
* @param[in] StdHeader
*
*/
VOID
GetChipSysMode (
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader);
}
/**
* IsImcEnabled - Is IMC Enabled
* @retval TRUE for IMC Enabled; FALSE for IMC Disabled
*/
BOOLEAN
IsImcEnabled (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 dbSysConfig;
GetChipSysMode (&dbSysConfig, StdHeader);
if (dbSysConfig & ChipSysEcEnable) {
return TRUE;
} else {
return FALSE;
}
}
/**
* GetEfuseStatue - Get Efuse status
*
*
* @param[in] Value - Return Chip strap status
* @param[in] StdHeader
*
*/
VOID
GetEfuseStatus (
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Or8;
UINT8 Mask8;
Or8 = BIT5;
Mask8 = BIT5;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8), Value, StdHeader);
LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1), Value, StdHeader);
Or8 = 0;
Mask8 = BIT5;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
}

144
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/MemLib.c
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@ -1,144 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH memory access lib
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 46093 $ @e \$Date: 2011-01-28 11:39:58 +0800 (Fri, 28 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Ids.h"
#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE
/**
* ReadMem - Read FCH BAR Memory
*
* @param[in] Address - Memory BAR address
* @param[in] OpFlag - Access width
* @param[in] *ValuePtr - In/Out value pointer
*
*/
VOID
ReadMem (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID *ValuePtr
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccessWidth8:
*((UINT8*)ValuePtr) = *((UINT8*) ((UINTN)Address));
break;
case AccessWidth16:
*((UINT16*)ValuePtr) = *((UINT16*) ((UINTN)Address));
break;
case AccessWidth32:
*((UINT32*)ValuePtr) = *((UINT32*) ((UINTN)Address));
break;
default:
ASSERT (FALSE);
break;
}
}
/**
* WriteMem - Write FCH BAR Memory
*
* @param[in] Address - Memory BAR address
* @param[in] OpFlag - Access width
* @param[in] *ValuePtr - In/Out Value pointer
*
*/
VOID
WriteMem (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID *ValuePtr
)
{
OpFlag = OpFlag & 0x7f;
switch ( OpFlag ) {
case AccessWidth8 :
*((UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr);
break;
case AccessWidth16:
*((UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr);
break;
case AccessWidth32:
*((UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr);
break;
default:
ASSERT (FALSE);
break;
}
}
/**
* RwMem - Read & Write FCH BAR Memory
*
* @param[in] Address - Memory BAR address
* @param[in] OpFlag - Access width
* @param[in] Mask - Mask Value of data
* @param[in] Data - Write data
*
*/
VOID
RwMem (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data
)
{
UINT32 Result;
ReadMem (Address, OpFlag, &Result);
Result = (Result & Mask) | Data;
WriteMem (Address, OpFlag, &Result);
}

94
src/vendorcode/amd/agesa/f12/Proc/Fch/Common/PciLib.c
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@ -1,94 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH PCI access lib
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE
VOID
ReadPci (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID* Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
}
VOID
WritePci (
IN UINT32 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
}
VOID
RwPci (
IN UINT32 Address,
IN UINT8 OpFlag,
IN UINT32 Mask,
IN UINT32 Data,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCI_ADDR PciAddress;
UINT32 rMask;
PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
rMask = ~Mask;
LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
}

1949
src/vendorcode/amd/agesa/f12/Proc/Fch/Fch.h
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File diff suppressed because it is too large Load Diff

117
src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h
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@ -1,117 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH platform definition
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 48055 $ @e \$Date: 2011-03-03 10:33:13 +0800 (Thu, 03 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#ifndef _FCH_PLATFORM_H_
#define _FCH_PLATFORM_H_
#define MAX_SATA_PORTS 8
#include "AGESA.h"
#ifndef FCHOEM_ACPI_RESTORE_SWSMI
#define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
#define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
#define FCHOEM_ENABLE_ACPI_SWSMI 0xA0
#define FCHOEM_DISABLE_ACPI_SWSMI 0xA1
#endif
#ifndef FCHOEM_SPI_UNLOCK_SWSMI
#define FCHOEM_SPI_UNLOCK_SWSMI 0xAA
#endif
#ifndef FCHOEM_SPI_LOCK_SWSMI
#define FCHOEM_SPI_LOCK_SWSMI 0xAB
#endif
#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
#define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000
#endif
#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
#define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0
#endif
#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
#define FCHOEM_ACPI_BYTE_CHECHSUM 0x100
#endif
#ifndef FCHOEM_IO_DELAY_PORT
#define FCHOEM_IO_DELAY_PORT 0x80
#endif
#ifndef FCHOEM_OUTPUT_DEBUG_PORT
#define FCHOEM_OUTPUT_DEBUG_PORT 0x80
#endif
#define FCH_PCIRST_BASE_IO 0xCF9
#define FCH_PCI_RESET_COMMAND06 0x06
#define FCH_PCI_RESET_COMMAND0E 0x0E
#define FCH_KBDRST_BASE_IO 0x64
#define FCH_KBC_RESET_COMMAND 0xFE
#define FCH_ROMSIG_BASE_IO 0x20000
#define FCH_ROMSIG_SIGNATURE 0x55AA55AA
#define FCH_MAX_TIMER 0xFFFFFFFF
#define FCH_GEC_INTERNAL_REG 0x6804
#define FCH_HPET_REG_MASK 0xFFFFF800
#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000
#ifndef FCHOEM_ELAPSED_TIME_UNIT
#define FCHOEM_ELAPSED_TIME_UNIT 28
#endif
#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
#define FCHOEM_ELAPSED_TIME_DIVIDER 100
#endif
#include "Fch.h"
#include "amdlib.h"
#include "FchCommonCfg.h"
#include "AcpiLib.h"
#include "FchDef.h"
#include "OEM.h"
#include "FchBiosRamUsage.h"
#include "AmdFch.h"
extern BUILD_OPT_CFG UserOptions;
#endif // _FCH_PLATFORM_H_

104
src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecEnvService.c
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@ -1,104 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH GEC controller
*
* Init GEC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE
/**
* FchInitGecController - Config GEC controller
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitGecController (
IN VOID *FchDataPtr
)
{
UINT8 FchSBGecDebugBus;
UINT8 FchSBGecPwr;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
FchSBGecDebugBus = (UINT8) LocalCfgPtr->Gec.GecDebugBus;
FchSBGecPwr = (UINT8) LocalCfgPtr->Gec.GecPowerPolicy;
if ( LocalCfgPtr->Misc.Cg2Pll == 1 ) {
LocalCfgPtr->Gec.GecEnable = 1;
}
if ( LocalCfgPtr->Gec.GecEnable == 0) {
//
// GEC Enabled
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT0, 0x00);
} else {
//
// GEC Disabled
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT0, BIT0);
//return; ///return if GEC controller is disabled.
}
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG11, AccessWidth8, 0, 0x00);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG21, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG166, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG181, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF8, AccessWidth8, ~(BIT5 + BIT6), (UINT8) ((FchSBGecPwr) << 5));
if ( FchSBGecDebugBus == 1) {
//
// GEC Debug Bus Enabled
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT3, BIT3);
} else {
//
// GEC Debug Bus Disabled
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGF6, AccessWidth8, ~BIT3, 0x00);
}
}

78
src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/Family/Hudson2/Hudson2GecService.c
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@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH GEC controller
*
* Init GEC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE
/**
* FchSwInitGecBootRom - Config GEC Boot ROM by Platform define
* ROM address
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchSwInitGecBootRom (
IN VOID *FchDataPtr
)
{
VOID* GecRomAddress;
VOID* GecShadowRomAddress;
UINT32 Temp;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( !LocalCfgPtr->Gec.PtrDynamicGecRomAddress == NULL ) {
GecRomAddress = LocalCfgPtr->Gec.PtrDynamicGecRomAddress;
GecShadowRomAddress = (VOID*) (UINTN) LocalCfgPtr->Gec.GecShadowRomBase;
FchCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
ReadPci ((GEC_BUS_DEV_FUN << 16) + FCH_GEC_REG10, AccessWidth32, &Temp, StdHeader);
Temp = Temp & 0xFFFFFFF0;
RwMem (Temp + FCH_GEC_INTERNAL_REG, AccessWidth32, 0, BIT0 + BIT29);
}
}

65
src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecEnv.c
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@ -1,65 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH GEC controller
*
* Init GEC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_GEC_GECENV_FILECODE
extern VOID FchInitGecController (IN VOID* FchDataPtr);
/**
* FchInitEnvGec - Config GEC controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvGec (
IN VOID *FchDataPtr
)
{
FchInitGecController (FchDataPtr);
}

61
src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecLate.c
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@ -1,61 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH GEC controller
*
* Init GEC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_GEC_GECLATE_FILECODE
/**
* FchInitLateGec - Prepare GEC controller to boot to OS.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateGec (
IN VOID *FchDataPtr
)
{
}

63
src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecMid.c
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@ -1,63 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH GEC controller
*
* Init GEC features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_GEC_GECMID_FILECODE
extern VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
/**
* FchInitMidGec - Config GEC controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidGec (
IN VOID *FchDataPtr
)
{
FchSwInitGecBootRom (FchDataPtr);
}

83
src/vendorcode/amd/agesa/f12/Proc/Fch/Gec/GecReset.c
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@ -1,83 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH GEC controller
*
* Init Gec Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_GEC_GECRESET_FILECODE
/**
* FchInitResetGec - Config Gec controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetGec (
IN VOID *FchDataPtr
)
{
//
// Init Gec SHADOW Rom Base Address
//
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG9C, AccessWidth32, 0, \
UserOptions.CfgGecShadowRomBase + 1, ((FCH_RESET_DATA_BLOCK *) FchDataPtr)->StdHeader);
}
/**
* FchInitRecoveryGec - Config Gec controller during Crisis
* Recovery
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitRecoveryGec (
IN VOID *FchDataPtr
)
{
}

505
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
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@ -1,505 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init HwAcpi Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "amdlib.h"
#include "cpuServices.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE
#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID
/**
* FchInitEnvHwAcpiMmioTable - Fch ACPI MMIO initial
* during POST.
*
*/
ACPI_REG_WRITE FchHudson2InitEnvHwAcpiMmioTable[] =
{
{00, 00, 0xB0, 0xAC}, /// Signature
//
// HPET workaround
//
{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},
{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
//
// Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3]
// ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.
// UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.
// ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.
// MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event.
// IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.
// GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.
// PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state.
// UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.
// Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support.
//
{PMIO_BASE >> 8, FCH_PMIOA_REGC4, ~BIT2, BIT2},
{PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0xF9},
{PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x04, 0x07},
//
// RtcSts 19-17 RTC_STS set only in Sleep State.
// GppPme 20 Set to 1 to enable PME request from SB GPP.
// Pcireset 22 Set to 1 to allow SW to reset PCIe.
//
{PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58},
{PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40},
{PMIO_BASE >> 8, FCH_PMIOA_REGC2, ~(BIT4), BIT4},
{PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x01},
{PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
{PMIO_BASE >> 8, FCH_PMIOA_REG74 + 3, ~BIT5, 0},
{PMIO_BASE >> 8, FCH_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},
{PMIO_BASE >> 8, FCH_PMIOA_REGDE, ~BIT4, BIT4},
{PMIO_BASE >> 8, FCH_PMIOA_REGBA, ~BIT3, BIT3},
{PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, ~BIT6, BIT6},
{PMIO_BASE >> 8, FCH_PMIOA_REGBC, ~BIT1, BIT1},
{PMIO_BASE >> 8, FCH_PMIOA_REGED, ~(BIT0 + BIT1), 0},
{PMIO_BASE >> 8, FCH_PMIOA_REGDC, 0x7C, BIT0}, /// Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01
{PMIO_BASE >> 8, FCH_PMIOA_REGBF, ~BIT0, 0},
{PMIO_BASE >> 8, FCH_PMIOA_REGBE, ~BIT0, BIT0},
{SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1},
{SMI_BASE >> 8, FCH_SMI_Gevent3, 0, 3},
{SMI_BASE >> 8, FCH_SMI_Gevent4, 0, 4},
{SMI_BASE >> 8, FCH_SMI_Gevent5, 0, 5},
{SMI_BASE >> 8, FCH_SMI_Gevent6, 0, 6},
{SMI_BASE >> 8, FCH_SMI_Gevent23, 0, 23},
{SMI_BASE >> 8, FCH_SMI_xHC0Pme, 0, 11},
{SMI_BASE >> 8, FCH_SMI_xHC1Pme, 0, 11},
{SMI_BASE >> 8, FCH_SMI_Usbwakup0, 0, 11},
{SMI_BASE >> 8, FCH_SMI_Usbwakup1, 0, 11},
{SMI_BASE >> 8, FCH_SMI_Usbwakup2, 0, 11},
{SMI_BASE >> 8, FCH_SMI_Usbwakup3, 0, 11},
{SMI_BASE >> 8, FCH_SMI_IMCGevent0, 0, 12},
{SMI_BASE >> 8, FCH_SMI_FanThGevent, 0, 13},
{SMI_BASE >> 8, FCH_SMI_SBGppPme0, 0, 15},
{SMI_BASE >> 8, FCH_SMI_SBGppPme1, 0, 16},
{SMI_BASE >> 8, FCH_SMI_SBGppPme2, 0, 17},
{SMI_BASE >> 8, FCH_SMI_SBGppPme3, 0, 18},
{SMI_BASE >> 8, FCH_SMI_GecPme, 0, 19},
{SMI_BASE >> 8, FCH_SMI_CIRPme, 0, 28},
{SMI_BASE >> 8, FCH_SMI_Gevent8, 0, 24},
{SMI_BASE >> 8, FCH_SMI_AzaliaPme, 0, 27},
{SMI_BASE >> 8, FCH_SMI_SataGevent0, 0, 30},
{SMI_BASE >> 8, FCH_SMI_SataGevent1, 0, 31},
{SMI_BASE >> 8, FCH_SMI_REG08, 0xE7, 0},
{SMI_BASE >> 8, FCH_SMI_REG0C + 2, ~BIT3, BIT3},
{SMI_BASE >> 8, FCH_SMI_TWARN, 0, 9},
{SMI_BASE >> 8, FCH_SMI_REG3C, 0, BIT6},
{SMI_BASE >> 8, FCH_SMI_REG84 + 2, 0, BIT7},
//
// CG PLL CMOX Clock Driver Setting for power saving
//
{MISC_BASE >> 8, FCH_MISC_REG18 + 0x06, 0, 0xE0},
{MISC_BASE >> 8, FCH_MISC_REG18 + 0x07, 0, 0x1F},
{MISC_BASE >> 8, FCH_MISC_REG50 + 3, ~BIT5, BIT5},
{MISC_BASE >> 8, FCH_MISC_REG50 + 2, ~BIT3, BIT3},
//{SERIAL_DEBUG_BASE >> 8, FCH_SDB_REG74, 0, 0},
{0xFF, 0xFF, 0xFF, 0xFF},
};
/**
* FchHudson2InitEnvHwAcpiPciTable - PCI device registers initial
* during early POST.
*
*/
REG8_MASK FchHudson2InitEnvHwAcpiPciTable[] =
{
//
// SMBUS Device (Bus 0, Dev 20, Func 0)
//
{0x00, SMBUS_BUS_DEV_FUN, 0},
{FCH_CFG_REG10, 0X00, (FCH_VERSION & 0xFF)}, ///Program the version information
{FCH_CFG_REG11, 0X00, (FCH_VERSION >> 8)},
{0xFF, 0xFF, 0xFF},
};
/**
* ProgramPFchAcpiMmio - Config HwAcpi MMIO registers
* Acpi S3 resume won't execute this procedure (POST only)
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramEnvPFchAcpiMmio (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchHudson2InitEnvHwAcpiMmioTable[0]), StdHeader);
}
/**
* ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller
* before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramFchEnvHwAcpiPciReg (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// FCH CFG programming
//
// Make BAR registers of smbus visible.
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~BIT6, 0);
//
//Early post initialization of pci config space
//
ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), sizeof (FchHudson2InitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader);
if ( LocalCfgPtr->Smbus.SmbusSsid != NULL ) {
RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
}
//
//Make BAR registers of smbus invisible.
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, ~BIT6, BIT6);
}
/**
* FchVgaInit - Config VGA CODEC
*
* @param[in] VOID empty
*
*/
VOID
FchVgaInit (
OUT VOID
)
{
//
// Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xff, BIT5 );
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0x00, 0x17 );
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD9, AccessWidth8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3)));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8, AccessWidth8, 0x00, 0x16 );
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD9, AccessWidth8, 0x0f, ((DACADJ & 0x0f) << 4));
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff);
*((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff);
*((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08;
*((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01;
}
/**
* ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before
* PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramSpecificFchInitEnvAcpiMmio (
IN VOID *FchDataPtr
)
{
CPUID_DATA CpuId;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set ASF SMBUS master function enabled here (temporary)
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, ~(BIT0 + BIT2), BIT0 + BIT2);
#ifdef ACPI_SLEEP_TRAP
//
// Set SLP_TYPE as SMI event
//
RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, AccessWidth8, ~(BIT2 + BIT3), BIT2);
//
// Disabled SLP function for S1/S3/S4/S5
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE, AccessWidth8, ~BIT5, 0x00);
//
// Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG08 + 3, AccessWidth8, ~(BIT0 + BIT1), BIT1);
//
// Enabled Global Smi ( BIT7 clear as 0 to enable )
//
RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98 + 3 , AccessWidth8, ~BIT7, 0x00);
#endif
//
// Set Stutter timer settings
//
LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 1, AccessWidth8, ~(BIT3 + BIT4), BIT3 + BIT4);
//
// Set LDTSTP# duration to 10us for Specific CPU, or when HT link is 200MHz
//
if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x28);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x20);
}
if (!IsImcEnabled (StdHeader)) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD2, AccessWidth8, 0xFF, BIT3);
}
//
// SSC will provide better jitter margin
//
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccessWidth8, 0xFC, 0x01);
//
// Ac Loss Control
//
AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow);
//
//FCH VGA Init
//
FchVgaInit ();
//
// Set ACPIMMIO by OEM Input table
//
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader);
}
/**
* ValidateFchVariant - Validate FCH Variant
*
*
*
* @param[in] FchDataPtr
*
*/
VOID
ValidateFchVariant (
IN VOID *FchDataPtr
)
{
UINT8 XhciEfuse;
UINT8 PcieEfuse;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
switch ( LocalCfgPtr->Misc.FchVariant ) {
case FCH_M3T:
//Disable Devices for M3T
LocalCfgPtr->Gec.GecEnable = 1;
LocalCfgPtr->Hwm.HwMonitorEnable = 0;
LocalCfgPtr->Sd.SdConfig = 0;
LocalCfgPtr->Ir.IrConfig = 0;
break;
default:
break;
}
// add Efuse checking for Xhci enable/disable
XhciEfuse = XHCI_EFUSE_LOCATION;
GetEfuseStatus (&XhciEfuse, StdHeader);
if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) {
LocalCfgPtr->Usb.Xhci0Enable = 0;
LocalCfgPtr->Usb.Xhci1Enable = 0;
}
// add Efuse checking for PCIE Gen2 enable
PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION;
GetEfuseStatus (&PcieEfuse, StdHeader);
if ( PcieEfuse & BIT0 ) {
LocalCfgPtr->Gpp.GppGen2 = 0;
}
}
/**
* IsExternalClockMode - Is External Clock Mode?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsExternalClockMode (
IN VOID *FchDataPtr
)
{
UINT8 MISC80;
ReadMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80, AccessWidth8, &MISC80);
return ( (BOOLEAN) ((MISC80 & BIT4) == 0) );
}
/**
* ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before
* PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramFchEnvSpreadSpectrum (
IN VOID *FchDataPtr
)
{
UINT8 PortStatus;
UINT8 FchSpreadSpectrum;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum;
if ( FchSpreadSpectrum ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth32, (UINT32) (~(0x1 << 25)), (0x1 << 25));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 0)), (0x0 << 0));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0x7FF << 5)), (0x418 << 5));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0xF << 16)), (0x0 << 16));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFFFF << 8)), (0x828F << 8));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFF << 0)), (0xA8 << 0));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth32, (UINT32) (~(0x3F << 0)), (0x0 << 0));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0xF << 28)), (0x1 << 28));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 7)), (0x0 << 8));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 8)), (0x1 << 8));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0x3 << 24)), (0x1 << 24));
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x01);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00);
}
//
// PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5)
// OSC Clock setting for internal clock generator mode (BIT6)
//
GetChipSysMode (&PortStatus, StdHeader);
if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG04 + 1, AccessWidth8, ~(BIT5 + BIT6), BIT5 + BIT6);
}
}
/**
* TurnOffCG2
*
*
* @retval VOID
*
*/
VOID
TurnOffCG2 (
OUT VOID
)
{
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth8, ~BIT6, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0x0F, 0xA0);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccessWidth8, ~(BIT1 + BIT0), (BIT1 + BIT0));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~( BIT4), (BIT4));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~(BIT6), (BIT6));
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth8, ~BIT6, BIT6);
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, ~BIT6, BIT6);
}
/**
* BackUpCG2
*
*
* @retval VOID
*
*/
VOID
BackUpCG2 (
OUT VOID
)
{
UINT8 Byte;
ReadMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, &Byte);
if (Byte & BIT6) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, ~(BIT6), (0));
}
}

343
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiLateService.c
View File

@ -1,343 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init HwAcpi Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 46093 $ @e \$Date: 2011-01-28 11:39:58 +0800 (Fri, 28 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuServices.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE
#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID
/**
* HpetInit - Program Fch HPET function
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HpetInit (
IN VOID *FchDataPtr
)
{
DESCRIPTION_HEADER *HpetTable;
UINT8 FchHpetTimer;
UINT8 FchHpetMsiDis;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
FchHpetTimer = (UINT8) LocalCfgPtr->Hpet.HpetTimer;
FchHpetMsiDis = (UINT8) LocalCfgPtr->Hpet.HpetMsiDis;
HpetTable = NULL;
if ( FchHpetTimer == TRUE ) {
//
//Program the HPET BAR address
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, LocalCfgPtr->Hpet.HpetBase);
//
//Enabling decoding of HPET MMIO
//Enable HPET MSI support
//Enable High Precision Event Timer (also called Multimedia Timer) interrupt
//
if ( FchHpetMsiDis == FALSE ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);
#ifdef FCH_TIMER_TICK_INTERVAL_WA
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
#endif
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1);
}
} else {
if ( ! (LocalCfgPtr->Misc.S3Resume) ) {
HpetTable = (DESCRIPTION_HEADER*) AcpiLocateTable ('TEPH');
}
if ( HpetTable != NULL ) {
HpetTable->Signature = 'HPET';
}
}
}
/**
* C3PopupSetting - Program Fch C state function
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
C3PopupSetting (
IN VOID *FchDataPtr
)
{
UINT32 Value;
//
// C-State and VID/FID Change
//
GetActiveCoresInGivenSocket (0, &Value, ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader);
#define NON_SUPPORT_PREVIOUS_C3 TRUE
#ifndef NON_SUPPORT_PREVIOUS_C3
if (Value > 1) {
//
//PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
//PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
//PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the FCH will de-assert
//LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth8, ~(BIT1 + BIT2), (BIT1 + BIT2));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~BIT6, BIT6);
}
//
//PM 0x80 [8] = 0 for system with NB
//Note: North bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
//BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
//PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);
//
//LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
//the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
//serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
//link is disconnected.
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94 + 2, AccessWidth8, 0, 0x10);
//
//This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
//delay will allow USB DMA to go on in a continuous manner
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 1, AccessWidth8, 0, 0x10);
//
// ASIC info
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C, AccessWidth8, 0, 0x85);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7C + 1, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E + 1, AccessWidth8, ~(BIT7 + BIT5), BIT7 + BIT5);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88 + 1, AccessWidth8, ~BIT4, BIT4);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG98 + 3, AccessWidth8, 0, 0x10);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB4 + 1, AccessWidth8, 0, 0x0B);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(BIT4 + BIT5), BIT4 + BIT5);
#else
// C-State and VID/FID Change
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~(BIT5), BIT5);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT2), BIT2);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT1), BIT1);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7E, AccessWidth8, ~(BIT6), BIT6);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG89, AccessWidth8, ~BIT4, BIT4);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG88, AccessWidth8, ~BIT4, BIT4);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(BIT6 + BIT5 + BIT4), BIT4);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG9B, AccessWidth8, ~(BIT1 + BIT0), 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG96, AccessWidth8, 0, 0x10);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG99, AccessWidth8, 0, 0x10);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG8E, AccessWidth8, 0, 0x80);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG97, AccessWidth8, ~(BIT1 + BIT0), 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT4), BIT4);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT9), BIT9);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~(BIT7), 0);
#endif
}
/**
* GcpuRelatedSetting - Program Gcpu C related function
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
GcpuRelatedSetting (
IN VOID *FchDataPtr
)
{
UINT8 FchAcDcMsg;
UINT8 FchTimerTickTrack;
UINT8 FchClockInterruptTag;
UINT8 FchOhciTrafficHanding;
UINT8 FchEhciTrafficHanding;
UINT8 FchGcpuMsgCMultiCore;
UINT8 FchGcpuMsgCStage;
UINT32 Value;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
FchAcDcMsg = (UINT8) LocalCfgPtr->Gcpu.AcDcMsg;
FchTimerTickTrack = (UINT8) LocalCfgPtr->Gcpu.TimerTickTrack;
FchClockInterruptTag = (UINT8) LocalCfgPtr->Gcpu.ClockInterruptTag;
FchOhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.OhciTrafficHanding;
FchEhciTrafficHanding = (UINT8) LocalCfgPtr->Gcpu.EhciTrafficHanding;
FchGcpuMsgCMultiCore = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCMultiCore;
FchGcpuMsgCStage = (UINT8) LocalCfgPtr->Gcpu.GcpuMsgCStage;
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
Value = Value & 0xC07F00A0;
if ( FchAcDcMsg ) {
Value = Value | BIT0;
}
if ( FchTimerTickTrack ) {
Value = Value | BIT1;
}
if ( FchClockInterruptTag ) {
Value = Value | BIT10;
}
if ( FchOhciTrafficHanding ) {
Value = Value | BIT13;
}
if ( FchEhciTrafficHanding ) {
Value = Value | BIT15;
}
if ( FchGcpuMsgCMultiCore ) {
Value = Value | BIT23;
}
if ( FchGcpuMsgCMultiCore ) {
Value = (Value | (BIT6 + BIT4 + BIT3 + BIT2));
}
WriteMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGA0, AccessWidth32, &Value);
}
/**
* MtC1eEnable - Program Mt C1E Enable Function
*
*
*
* @param[in] FchDataPtr
*
*/
VOID
MtC1eEnable (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
if ( LocalCfgPtr->HwAcpi.MtC1eEnable ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, ~ BIT15, BIT15);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7A, AccessWidth16, ~ (BIT3 + BIT2 + BIT1 + BIT0), 0x01);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80, AccessWidth16, ~ BIT13, BIT13);
}
}
/**
* StressResetModeLate - Stress Reset Mode
*
*
*
* @param[in] FchDataPtr
*
*/
VOID
StressResetModeLate (
IN VOID *FchDataPtr
)
{
UINT8 ResetValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
switch ( LocalCfgPtr->HwAcpi.StressResetMode ) {
case 0:
return;
case 1:
ResetValue = FCH_KBC_RESET_COMMAND;
LibAmdIoWrite (AccessWidth8, FCH_KBDRST_BASE_IO, &ResetValue, StdHeader);
break;
case 2:
ResetValue = FCH_PCI_RESET_COMMAND06;
LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader);
break;
case 3:
ResetValue = FCH_PCI_RESET_COMMAND0E;
LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &ResetValue, StdHeader);
break;
case 4:
LocalCfgPtr->HwAcpi.StressResetMode = 3;
return;
default:
ASSERT (FALSE);
return;
}
while (LocalCfgPtr->HwAcpi.StressResetMode) {
}
}

48
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiMidService.c
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@ -1,48 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init HwAcpi Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "amdlib.h"
#include "cpuServices.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE

142
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c
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@ -1,142 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init Spread Spectrum features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "amdlib.h"
#include "cpuServices.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE
/**
* FchInitResetAcpiMmioTable - Fch ACPI MMIO initial
* during the power on stage.
*
*
*
*
*/
ACPI_REG_WRITE FchInitResetAcpiMmioTable[] =
{
{00, 00, 0xB0, 0xAC}, /// Signature
{MISC_BASE >> 8, FCH_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12]
//
// USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock.
//
{MISC_BASE >> 8, FCH_MISC_REG40, 0xEF, 0x00},
{PMIO_BASE >> 8, FCH_PMIOA_REG5D, 0x00, BIT0},
{PMIO_BASE >> 8, FCH_PMIOA_REGD2, 0xCF, BIT4 + BIT5},
{SMBUS_BASE >> 8, FCH_SMBUS_REG12, 0x00, BIT0},
{PMIO_BASE >> 8, FCH_PMIOA_REG28, 0xFF, BIT0},
{PMIO_BASE >> 8, FCH_PMIOA_REG44 + 3, 0x67, BIT7}, /// Disable Boot timer
{PMIO_BASE >> 8, FCH_PMIOA_REG48, 0xFF, BIT0},
{PMIO_BASE >> 8, FCH_PMIOA_REG00, 0xFF, 0x0E},
{PMIO_BASE >> 8, FCH_PMIOA_REG00 + 2, 0xFF, 0x40},
{PMIO_BASE >> 8, FCH_PMIOA_REG00 + 3, 0xFF, 0x08},
{PMIO_BASE >> 8, FCH_PMIOA_REG34, 0xEF, BIT0 + BIT1},
{PMIO_BASE >> 8, FCH_PMIOA_REGEC, 0xFD, BIT1},
{PMIO_BASE >> 8, FCH_PMIOA_REG08, 0xFE, BIT2 + BIT4},
{PMIO_BASE >> 8, FCH_PMIOA_REG08 + 1, 0xFF, BIT0},
{PMIO_BASE >> 8, FCH_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7},
{PMIO_BASE >> 8, FCH_PMIOA_REG04 + 3, 0xFD, BIT1},
{PMIO_BASE >> 8, FCH_PMIOA_REG74, 0xF6, BIT0 + BIT3},
{PMIO_BASE >> 8, FCH_PMIOA_REGF0, ~BIT2, 0x00},
//
// GEC I/O Termination Setting
// PM_Reg 0xF6 = Power-on default setting
// PM_Reg 0xF7 = Power-on default setting
// PM_Reg 0xF8 = 0x6C
// PM_Reg 0xF9 = 0x21
// PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS
//
{PMIO_BASE >> 8, FCH_PMIOA_REGF8, 0x00, 0x6C},
{PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 1, 0x00, 0x07},
{PMIO_BASE >> 8, FCH_PMIOA_REGF8 + 2, 0x00, 0x00},
//
// GEC -end
//
{PMIO_BASE >> 8, FCH_PMIOA_REGC4, 0xee, 0x04}, /// Release NB_PCIE_RST
{PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 2, 0xBF, 0x40},
{PMIO_BASE >> 8, FCH_PMIOA_REGBE, 0xDF, BIT5},
//
// Enabling ClkRun Function
//
{PMIO_BASE >> 8, FCH_PMIOA_REGBB, 0xFF, BIT2},
{PMIO_BASE >> 8, FCH_PMIOA_REGD0, ~BIT2, 0},
{0xFF, 0xFF, 0xFF, 0xFF},
};
/**
* ProgramFchHwAcpiResetP - Config SpreadSpectrum before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramFchHwAcpiResetP (
IN VOID *FchDataPtr
)
{
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
//Reset USB, BSOD 9F on Cobia Hudson 2 A12 during S4/S5 loop tests
RwPmio (0xD3, AccessWidth8, ~BIT4, 0, StdHeader);
RwPmio (0xD3, AccessWidth8, ~BIT4, BIT4, StdHeader);
if ( LocalCfgPtr->Cg2Pll == 1 ) {
TurnOffCG2 ();
LocalCfgPtr->SataClkMode = 0x0a;
}
}

106
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiEnv.c
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@ -1,106 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init HwAcpi Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "amdlib.h"
#include "cpuServices.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_HWACPIENV_FILECODE
extern VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
extern VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
extern VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
extern VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
extern VOID ValidateFchVariant (IN VOID *FchDataPtr);
/**
* FchInitEnvHwAcpiP - Config HwAcpi controller preliminary
* (Special)
* Acpi S3 resume won't execute this procedure (POST only)
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvHwAcpiP (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
RecordFchConfigPtr ( (UINT32) ((UINTN) (LocalCfgPtr)));
ValidateFchVariant (LocalCfgPtr);
ProgramEnvPFchAcpiMmio (FchDataPtr);
ProgramFchEnvSpreadSpectrum (FchDataPtr);
}
/**
* FchInitEnvHwAcpi - Config HwAcpi controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvHwAcpi (
IN VOID *FchDataPtr
)
{
ProgramFchEnvHwAcpiPciReg (FchDataPtr);
//
// FCH Specific Function programming
//
ProgramSpecificFchInitEnvAcpiMmio (FchDataPtr);
}

135
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiLate.c
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@ -1,135 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init HwAcpi Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "amdlib.h"
#include "cpuServices.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_HWACPILATE_FILECODE
#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID
extern VOID HpetInit (IN VOID *FchDataPtr);
extern VOID C3PopupSetting (IN VOID *FchDataPtr);
extern VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
extern VOID StressResetModeLate (IN VOID *FchDataPtr);
/**
* FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateHwAcpi (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
HpetInit (LocalCfgPtr);
if ( IsGCPU (LocalCfgPtr) ) {
GcpuRelatedSetting (LocalCfgPtr);
} else {
C3PopupSetting (LocalCfgPtr);
}
// Mt C1E Enable
MtC1eEnable (LocalCfgPtr);
if (LocalCfgPtr->SerialDb.SerialDebugBusEnable == 1 ) {
RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05);
}
StressResetModeLate (LocalCfgPtr);
}
/**
* IsGCPU - Is Gcpu Cpu?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsGCPU (
IN VOID *FchDataPtr
)
{
UINT8 ExtendedFamily;
UINT8 ExtendedModel;
UINT8 BaseFamily;
UINT8 BaseModel;
UINT8 Stepping;
UINT8 Family;
UINT8 Model;
CPUID_DATA CpuId;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff);
ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf);
BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf);
BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf);
Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf);
Family = BaseFamily + ExtendedFamily;
Model = (ExtendedModel << 4) + BaseModel;
if ( (Family == 0x12) || \
(Family == 0x14) || \
(Family == 0x16) || \
((Family == 0x15) && ((Model == 0x10) || (Model == 0x30))) ) {
return TRUE;
} else {
return FALSE;
}
}

64
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiMid.c
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@ -1,64 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init HwAcpi Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "amdlib.h"
#include "cpuServices.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_HWACPIMID_FILECODE
/**
* FchInitMidHwAcpi - Config HwAcpi controller after PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidHwAcpi (
IN VOID *FchDataPtr
)
{
}

200
src/vendorcode/amd/agesa/f12/Proc/Fch/HwAcpi/HwAcpiReset.c
View File

@ -1,200 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch HwAcpi controller
*
* Init HwAcpi Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWACPI_HWACPIRESET_FILECODE
extern ACPI_REG_WRITE FchInitResetAcpiMmioTable[];
extern VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
/**
* FchInitResetHwAcpiP - Config HwAcpi controller ( Preliminary
* ) during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetHwAcpiP (
IN VOID *FchDataPtr
)
{
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
//
// Enabled (Mmio_mem_enable)
//
RwPmio (FCH_PMIOA_REG24, AccessWidth8, 0xFF, BIT0, StdHeader);
ProgramFchHwAcpiResetP (FchDataPtr);
//
// enable CF9
//
RwPmio (0xD2, AccessWidth8, ~BIT6, 0, StdHeader);
}
/**
* FchInitResetHwAcpi - Config HwAcpi controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetHwAcpi (
IN VOID *FchDataPtr
)
{
UINT16 SmbusBase;
UINT8 Value;
UINT16 AsfPort;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set Build option into SB
//
WritePci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG64, AccessWidth16, &(UserOptions.CfgSioPmeBaseAddress), StdHeader);
//
// Enabled SMBUS0/SMBUS1 (ASF) Base Address
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2C, AccessWidth16, 06, (UserOptions.CfgSmbus0BaseAddress) + BIT0); ///protect BIT[2:1]
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG28, AccessWidth16, 06, (UserOptions.CfgSmbus1BaseAddress) + BIT0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, 00, (UserOptions.CfgAcpiPm1EvtBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG62, AccessWidth16, 00, (UserOptions.CfgAcpiPm1CntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64, AccessWidth16, 00, (UserOptions.CfgAcpiPmTmrBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG66, AccessWidth16, 00, (UserOptions.CfgCpuControlBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG68, AccessWidth16, 00, (UserOptions.CfgAcpiGpe0BlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6A, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, 00, (UserOptions.CfgAcpiPmaCntBlkAddr));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6E, AccessWidth16, 00, (UserOptions.CfgSmiCmdPortAddr) + 8);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG48, AccessWidth32, 00, (UserOptions.CfgWatchDogTimerBase));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0); ///clear BIT[2:1]
SmbusBase = (UINT16) (UserOptions.CfgSmbus0BaseAddress);
Value = 0x00;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &Value, StdHeader);
ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchInitResetAcpiMmioTable[0]), StdHeader);
//
// Prevent RTC error
//
Value = 0x0A;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xEF;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value | 0x0A;
}
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
Value = 0x09;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
//
Value = Value & 0xF9;
}
if ( LocalCfgPtr->LegacyFree ) {
//
// Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.
//
Value = Value & 0x9F;
}
//
// Enabled IRQ input
//
Value = Value | BIT4;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
AsfPort = ((UINT16) UserOptions.CfgSmbus1BaseAddress & 0xFFF0);
if ( AsfPort != 0 ) {
UINT8 dbValue;
dbValue = 0x70;
LibAmdIoWrite (AccessWidth8, AsfPort + 0x0E, &dbValue, StdHeader);
}
}
/**
* FchInitRecoveryHwAcpi - Config HwAcpi controller during
* Crisis Recovery
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitRecoveryHwAcpi (
IN VOID *FchDataPtr
)
{
}

265
src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmEnvService.c
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@ -1,265 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE
FCH_HWM_TEMP_PAR TempParDefault[] = {
{ 5220, 27365 , 0 },
{ 5225, 27435 , 0 },
{ 5220, 27516 , BIT0 }, ///High Ratio
{ 5212, 27580 , BIT1 }, ///High Current
{ 5123, 27866 , 0 }
};
/**
* HwmInitRegister - Init Hardware Monitor Register.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmInitRegister (
IN VOID *FchDataPtr
)
{
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccessWidth8, 0, 0x55);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccessWidth8, 0, 0x55);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccessWidth8, 0, 0x55);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccessWidth8, 0, 0x55);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccessWidth8, 0, 0x06);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccessWidth8, 0, 0x06);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccessWidth8, 0, 0x06);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccessWidth8, 0, 0x06);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccessWidth8, 0, 0x06);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE6, AccessWidth8, 0xff, 0x02);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccessWidth8, 0, 0x05);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccessWidth8, 0, 0x06);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccessWidth8, 0, 0x42);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccessWidth8, 0, 0xFF);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccessWidth8, 0, 0x1F);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccessWidth8, 0, 0x04);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccessWidth8, 0, 0x00);
//2.9 Enhancement of FanOut0 Control
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG50, AccessWidth32, ~ (BIT11 + BIT20), (BIT11 + BIT20));
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGB6, AccessWidth8, 0x0F, 0x10);
}
/**
* HwmProcessParameter - Hardware Monitor process Parameter
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmProcessParameter (
IN VOID *FchDataPtr
)
{
UINT8 Index;
UINT8 TempChannel;
UINT8 ValueByte;
UINT16 ValueWord;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
HwmGetCalibrationFactor (LocalCfgPtr);
//
//temperatue parameter
//
for ( Index = 0; Index < 5 ; Index++ ) {
if ( LocalCfgPtr->Hwm.HwmTempPar[Index].At == 0 ) {
LocalCfgPtr->Hwm.HwmTempPar[Index] = TempParDefault[Index];
}
}
for ( Index = 0; Index < 5 ; Index++ ) {
if ( LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 == 100 ) {
LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 = 255;
} else {
LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 = (LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03 << 8) / 100;
}
if ( LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 == 100 ) {
LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 = 255;
} else {
LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 = (LocalCfgPtr->Hwm.HwmFanControl[Index].MedDutyReg04 << 8) / 100;
}
ValueByte = (UINT8) ((256 - LocalCfgPtr->Hwm.HwmFanControl[Index].LowDutyReg03) / (LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A - LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08));
ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].LowTempReg06;
if (LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00 > 4) {
TempChannel = 0;
} else {
TempChannel = LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00;
}
if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
ValueWord = ValueWord << 8;
} else {
ValueByte = (UINT8) (ValueByte * 10000 / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At);
ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
}
LocalCfgPtr->Hwm.HwmFanControl[Index].LowTempReg06 = ValueWord;
LocalCfgPtr->Hwm.HwmFanControl[Index].MultiplierReg05 = ValueByte & 0x3f;
ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08;
if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
ValueWord = ValueWord << 8;
} else {
ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
}
LocalCfgPtr->Hwm.HwmFanControl[Index].MedTempReg08 = ValueWord;
ValueWord = LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A;
if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 0)) {
ValueWord = ValueWord << 8;
} else {
ValueWord = ((ValueWord * 100 + LocalCfgPtr->Hwm.HwmTempPar[TempChannel].Ct ) * 100 * LocalCfgPtr->Hwm.HwmCalibrationFactor / LocalCfgPtr->Hwm.HwmTempPar[TempChannel].At) >> 3;
}
LocalCfgPtr->Hwm.HwmFanControl[Index].HighTempReg0A = ValueWord;
}
}
/**
* hwmSetRegister - Hardware Monitor Set Parameter
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmSetRegister (
IN VOID *FchDataPtr
)
{
UINT8 *DbValuePtr;
UINT8 Index;
UINT8 RegisterN;
UINT8 RegisterPM2RegF8;
UINT8 RegisterPM2RegF9;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Configure Fans
//
for ( Index = 0; Index < 5 ; Index++ ) {
DbValuePtr = &(LocalCfgPtr->Hwm.HwmFanControl[Index].InputControlReg00);
for ( RegisterN = 0; RegisterN < 0x0E ; RegisterN++ ) {
WritePmio2 (Index * 0x10 + RegisterN, AccessWidth8, DbValuePtr, StdHeader);
DbValuePtr ++;
}
}
//
//Configure Sample Frequency Divider
//
WritePmio2 (FCH_PMIO2_REG63, AccessWidth8, &(LocalCfgPtr->Hwm.FanSampleFreqDiv), StdHeader);
//
//Configure Mode
//
ReadPmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader);
ReadPmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader);
for ( Index = 0; Index < 5 ; Index++ ) {
if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT0) {
RegisterPM2RegF8 |= 1 << (Index + 3);
} else if (LocalCfgPtr->Hwm.HwmTempPar[Index].Mode == BIT1) {
RegisterPM2RegF9 |= 1 << (Index + 3);
}
}
WritePmio2 (0xF8, AccessWidth8, &RegisterPM2RegF8, StdHeader);
WritePmio2 (0xF9, AccessWidth8, &RegisterPM2RegF9, StdHeader);
}
/**
* hwmGetCalibrationFactor - Hardware Monitor Get Calibration
* Factor
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmGetCalibrationFactor (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//temperatue parameter
//
ReadPmio2 (FCH_PMIO2_REGEA, AccessWidth8, &ValueByte, StdHeader);
if ( ValueByte & BIT7 ) {
if ( ValueByte & BIT6 ) {
LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x100 + ValueByte;
} else {
LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200 + (ValueByte & 0x3f );
}
} else {
LocalCfgPtr->Hwm.HwmCalibrationFactor = 0x200;
}
}

170
src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c
View File

@ -1,170 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE
FCH_EC EcDefaultMassege = {
0x00, 0x00, 0x35, 0x0E, 0x00, 0x54, 0x9B, 0x02, 0x01, 0x00,
0x00, 0x01, 0x35, 0x0A, 0x00, 0x04, 0x00, 0x00, 0x01, 0x00,
0x00, 0x02, 0x05, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x03, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x46, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00,
0x00, 0x01, 0x5F, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x00,
0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x01, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x3E, 0x87, 0x00, 0x00, 0xA8, 0x11, 0x01, 0x00, 0x00,
0x00, 0x01, 0x86, 0x87, 0x00, 0x00, 0x14, 0x12, 0x01, 0x00, 0x01,
0x00, 0x02, 0x31, 0x86, 0x00, 0x00, 0x33, 0x15, 0x01, 0x00, 0x02,
0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x04, 0x86, 0x87, 0x00, 0x00, 0xA6, 0x11, 0x01, 0x00, 0x00
};
/**
* Table for Function Number
*
*
*
*
*/
UINT8 FunctionNumber[] =
{
Fun_81,
Fun_83,
Fun_85,
Fun_89,
};
/**
* Table for Max Thermal Zone
*
*
*
*
*/
UINT8 MaxZone[] =
{
4,
2,
2,
5,
};
/**
* Table for Max Register
*
*
*
*
*/
UINT8 MaxRegister[] =
{
MSG_REG9,
MSG_REGB,
MSG_REG9,
MSG_REGA,
};
/*-------------------------------------------------------------------------------
;Procedure: FchECfancontrolservice
;
;Description: This routine service EC fan policy
;
;
;Exit: None
;
;Modified: None
;
;-----------------------------------------------------------------------------
*/
VOID
FchECfancontrolservice (
IN VOID *FchDataPtr
)
{
UINT8 ZoneNum;
UINT8 FunNum;
UINT8 RegNum;
UINT8 *CurPoint;
UINT8 FunIndex;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if (!IsImcEnabled (StdHeader)) {
return; //IMC is not enabled
}
CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);
for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
CurPoint += 1;
}
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
}
CurPoint = &LocalCfgPtr->Imc.EcStruct.MsgFun81Zone0MsgReg0;
for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {
FunNum = FunctionNumber[FunIndex];
for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {
for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {
WriteECmsg (RegNum, AccessWidth8, CurPoint, StdHeader);
CurPoint += 1;
}
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &FunNum, StdHeader); // function number
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
}
}

248
src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmMidService.c
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@ -1,248 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE
/**
* hwmFchtsiAutoPolling - Hardware Monitor Auto Poll SB-TSI.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmFchtsiAutoPolling (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT16 SmbusBase;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress);
if (LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), BIT2);
ValueByte = 0xff;
LibAmdIoWrite (AccessWidth8, SmbusBase, &ValueByte, StdHeader);
ValueByte = 0x08;
LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
ValueByte = 0x09;
LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader);
ValueByte = 0x98;
LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader);
ValueByte = 0x20;
LibAmdIoWrite (AccessWidth8, SmbusBase + 5, &ValueByte, StdHeader);
ValueByte = 0x48;
LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader);
while ( ValueByte & BIT0 ) {
LibAmdIoRead (AccessWidth8, SmbusBase + 0, &ValueByte, StdHeader);
}
ValueByte = 0x08;
LibAmdIoWrite (AccessWidth8, SmbusBase + 2, &ValueByte, StdHeader);
ValueByte = 0x10;
LibAmdIoWrite (AccessWidth8, SmbusBase + 3, &ValueByte, StdHeader);
ValueByte = 0x99;
LibAmdIoWrite (AccessWidth8, SmbusBase + 4, &ValueByte, StdHeader);
ValueByte = 0x80;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
ValueByte = 0x01;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x17, &ValueByte, StdHeader);
ValueByte = 0x81;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
//
//map SB-TSI to tempin0
//
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, ~BIT3, BIT3);
} else {
HwmFchtsiAutoPollingOff (LocalCfgPtr);
}
}
/**
* HwmFchtsiAutoPollingOff - Hardware Monitor Auto Poll SB-TSI
* Off.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmFchtsiAutoPollingOff (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT16 SmbusBase;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Hwm.HwMonitorEnable ) {
SmbusBase = (UINT16) (LocalCfgPtr->HwAcpi.Smbus0BaseAddress);
ValueByte = 0x00;
LibAmdIoWrite (AccessWidth8, SmbusBase + 0x14, &ValueByte, StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG2E, AccessWidth8, ~(BIT1 + BIT2), 0);
RwMem (ACPI_MMIO_BASE + PMIO2_BASE + FCH_PMIO2_REG92, AccessWidth8, ~BIT3, 0x00);
}
}
/**
* HwmGetRawData - Hardware Monitor Get Raw Data.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmGetRawData (
IN VOID *FchDataPtr
)
{
UINT8 Index;
UINT16 ValueWord;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//fan speed
//
for ( Index = 0; Index < 5 ; Index++ ) {
ReadPmio2 (FCH_PMIO2_REG69 + Index * 5, AccessWidth16, &ValueWord, StdHeader);
if ( (ValueWord & 0xFFC0) != 0xFFC0 ) {
LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index] = ValueWord;
}
}
//
//temperatue
//
for ( Index = 0; Index < 5 ; Index++ ) {
ReadPmio2 (FCH_PMIO2_REG95 + Index * 4, AccessWidth16, &ValueWord, StdHeader);
if ( ( Index == 1 ) || (ValueWord > 0x4000) ) {
LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index] = ValueWord;
}
}
//
//voltage
//
for ( Index = 0; Index < 8 ; Index++ ) {
ReadPmio2 (FCH_PMIO2_REGB8 + Index * 4, AccessWidth16, &ValueWord, StdHeader);
if ( (ValueWord & 0xFFC0) != 0xFFC0 ) {
LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index] = ValueWord;
}
}
}
/**
* HwmCaculate - Hardware Monitor Caculate Raw Data to Display Data.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
HwmCaculate (
IN VOID *FchDataPtr
)
{
UINT8 Index;
UINT16 ValueWord;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
//
//fan speed
//
for ( Index = 0; Index < 5 ; Index++ ) {
ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.FanSpeed[Index];
if ((ValueWord == 0xffff) || (ValueWord == 0x0000)) {
LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = 0;
} else {
LocalCfgPtr->Hwm.HwmCurrent.FanSpeed[Index] = ( 22720 >> LocalCfgPtr->Hwm.FanSampleFreqDiv ) * 60 / ValueWord / 2;
}
}
//
//temperatue
//
for ( Index = 0; Index < 5 ; Index++ ) {
ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Temperature[Index];
if ((LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == 1) && (Index == 1)) {
ValueWord = ((ValueWord & 0xff00) >> 8) * 10 + (((ValueWord & 0x00ff) * 10 ) >> 8);
} else {
ValueWord = ((ValueWord << 3) * LocalCfgPtr->Hwm.HwmTempPar[Index].At / LocalCfgPtr->Hwm.HwmCalibrationFactor / 100 - LocalCfgPtr->Hwm.HwmTempPar[Index].Ct) / 100 ;
}
if ( LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] == 0 ) {
ValueWord = 0;
}
if ( ValueWord < 10000 ) {
LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = ValueWord;
} else {
LocalCfgPtr->Hwm.HwmCurrent.Temperature[Index] = 0;
}
}
//
//voltage
//
for ( Index = 0; Index < 8 ; Index++ ) {
ValueWord = LocalCfgPtr->Hwm.HwmCurrentRaw.Voltage[Index];
LocalCfgPtr->Hwm.HwmCurrent.Voltage[Index] = (ValueWord >> 6) * 512 / LocalCfgPtr->Hwm.HwmCalibrationFactor;
}
}

75
src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmEnv.c
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@ -1,75 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_HWMENV_FILECODE
extern VOID HwmInitRegister (IN VOID* FchDataPtr);
extern VOID HwmProcessParameter (IN VOID* FchDataPtr);
extern VOID HwmSetRegister (IN VOID* FchDataPtr);
/**
* FchInitEnvHwm - Config Hwm controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvHwm (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
if ( LocalCfgPtr->Hwm.HwMonitorEnable ) {
HwmInitRegister (LocalCfgPtr);
HwmProcessParameter (LocalCfgPtr);
HwmSetRegister (LocalCfgPtr);
}
}

84
src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmLate.c
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@ -1,84 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_HWMLATE_FILECODE
extern FCH_HWM_TEMP_PAR TempParDefault[];
extern FCH_EC EcDefaultMassege;
extern VOID FchECfancontrolservice (IN VOID* FchDataPtr);
/**
* FchInitLateHwm - Prepare Hwm controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateHwm (
IN VOID *FchDataPtr
)
{
UINT8 RegisterPM2Reg01;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
ImcWakeup (LocalCfgPtr);
if (( LocalCfgPtr->Hwm.HwmFchtsiAutoPoll == FALSE ) && ( LocalCfgPtr->Hwm.HwMonitorEnable )) {
//
// Overwrite Fan0Control to 0x04
//
RegisterPM2Reg01 = 0x04;
WritePmio2 (FCH_PMIO2_REG01, AccessWidth8, &RegisterPM2Reg01, StdHeader);
LocalCfgPtr->Imc.EcStruct = EcDefaultMassege;
FchECfancontrolservice (LocalCfgPtr);
}
}

74
src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmMid.c
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@ -1,74 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_HWMMID_FILECODE
extern VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
extern VOID HwmGetRawData (IN VOID* FchDataPtr);
extern VOID HwmCaculate (IN VOID* FchDataPtr);
/**
* FchInitMidHwm - Config Hwm controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidHwm (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
if ( LocalCfgPtr->Hwm.HwMonitorEnable ) {
HwmFchtsiAutoPolling (LocalCfgPtr);
HwmGetRawData (LocalCfgPtr);
HwmCaculate (LocalCfgPtr);
}
}

77
src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/HwmReset.c
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config FCH Hwm controller
*
* Init Hwm Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_HWM_HWMRESET_FILECODE
/**
* FchInitResetHwm - Config Hwm controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetHwm (
IN VOID *FchDataPtr
)
{
}
/**
* FchInitRecoveryLpc - Config Hwm controller during Crisis
* Recovery
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitRecoveryHwm (
IN VOID *FchDataPtr
)
{
}

120
src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeEnv.c
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@ -1,120 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch IDE controller
*
* Init IDE Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IDE_IDEENV_FILECODE
/**
* FchInitEnvIde - Config Ide controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvIde (
IN VOID *FchDataPtr
)
{
UINT8 Channel;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, 0xff, BIT0, StdHeader);
//
// Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0
//
RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG62 + 1), AccessWidth8, ~BIT0, BIT5, StdHeader);
//
// Disable SATA MSI
//
RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG34), AccessWidth8, 0x00, 0x00, StdHeader);
RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG06), AccessWidth8, 0xEF, 0x00, StdHeader);
//
// Set Ide Channel enable/disable by parameter
//
ReadPci (((IDE_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 11), AccessWidth8, &Channel, StdHeader);
Channel &= 0xCF;
if ( LocalCfgPtr->Sata.IdeDisUnusedIdePChannel ) {
Channel |= 0x10;
}
if ( LocalCfgPtr->Sata.IdeDisUnusedIdeSChannel ) {
Channel |= 0x20;
}
WritePci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40 + 11), AccessWidth8, &Channel, StdHeader);
//
// IDE Controller Class ID & SSID
// ** Get Sata Configuration ** for sync Sata & Ide with only one Legacy Ide device
//
if ( (LocalCfgPtr->Sata.SataIdeMode == 1) && (LocalCfgPtr->Sata.SataClass != SataLegacyIde) ) {
//
// Write the class code to IDE PCI register 08h-0Bh
//
RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
}
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
//
//Set SATA controller to native mode
//
RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG09), AccessWidth8, 0x00, 0x08F, StdHeader);
}
if (LocalCfgPtr->Ide.IdeSsid != NULL ) {
RwPci ((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Ide.IdeSsid, StdHeader);
}
//
// Disable write access to PCI header
//
RwPci (((IDE_BUS_DEV_FUN << 16) + FCH_IDE_REG40), AccessWidth8, ~BIT0, 0, StdHeader);
}

59
src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeLate.c
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@ -1,59 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch IDE controller
*
* Init IDE Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IDE_IDELATE_FILECODE
/**
* FchInitLateIde - Prepare IDE controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateIde (
IN VOID *FchDataPtr
)
{
}

61
src/vendorcode/amd/agesa/f12/Proc/Fch/Ide/IdeMid.c
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@ -1,61 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch IDE controller
*
* Init IDE Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IDE_IDEMID_FILECODE
/**
* FchInitMidIde - Config IDE controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidIde (
IN VOID *FchDataPtr
)
{
}

126
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/Family/Hudson2/Hudson2ImcService.c
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@ -1,126 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Imc controller
*
* Init Imc Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE
//
// Declaration of local functions
//
/**
* SoftwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SoftwareToggleImcStrapping (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT8 PortStatusByte;
UINT32 AbValue;
UINT32 ABStrapOverrideReg;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
ReadPmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
//
//if ( (ValueByte & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1
//The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.
//
//StrapStatus StrapOverride
// bit4 bit17
// bit6 bit12
// bit12 bit15
// bit15 bit16
// bit16 bit18
//
ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
ABStrapOverrideReg = AbValue;
if (AbValue & BIT4) {
ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT4) | BIT17;
}
if (AbValue & BIT6) {
ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT6) | BIT12;
}
if (AbValue & BIT12) {
ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT12) | BIT15;
}
if (AbValue & BIT15) {
ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT15) | BIT16;
}
if (AbValue & BIT16) {
ABStrapOverrideReg = (ABStrapOverrideReg & ~BIT16) | BIT18;
}
ABStrapOverrideReg |= BIT31; /// Overwrite enable
if ((PortStatusByte & ChipSysEcEnable) == 0) {
ABStrapOverrideReg |= BIT2; /// bit2- EcEnableStrap
} else {
ABStrapOverrideReg &= ~BIT2; /// bit2=0 EcEnableStrap
}
WriteMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG84), AccessWidth32, &ABStrapOverrideReg);
ValueByte |= (BIT6 + BIT7); /// PwrGoodOut =1, PwrGoodEnB=1
WritePmio (FCH_PMIOA_REGBF, AccessWidth8, &ValueByte, StdHeader);
ValueByte = 06;
LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
FchStall (0xffffffff, StdHeader);
}

185
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@ -1,185 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Embedded Controller
*
* Init Ec Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_FCHECENV_FILECODE
/**
* FchInitEnvEc - Config Ec controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvEc (
IN VOID *FchDataPtr
)
{
}
/*----------------------------------------------------------------------------------------*/
/**
* EnterEcConfig - Force EC into Config mode
*
*
*
*
*/
VOID
EnterEcConfig (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 EcIndexPortDword;
UINT8 FchEcData8;
ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
EcIndexPortDword &= ~(BIT0);
FchEcData8 = 0x5A;
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* ExitEcConfig - Force EC exit Config mode
*
*
*
*
*/
VOID
ExitEcConfig (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 EcIndexPortDword;
UINT8 FchEcData8;
ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
EcIndexPortDword &= ~(BIT0);
FchEcData8 = 0xA5;
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &FchEcData8, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* ReadEc8 - Read EC register data
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Read Data Buffer
* @param[in] StdHeader
*
*/
VOID
ReadEc8 (
IN UINT8 Address,
IN UINT8 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 EcIndexPortDword;
ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
EcIndexPortDword &= ~(BIT0);
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
LibAmdIoRead (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* RwEc8 - Read/Write EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] AndMask - Data And Mask 8 bits
* @param[in] OrMask - Data OR Mask 8 bits
* @param[in] StdHeader
*
*/
VOID
RwEc8 (
IN UINT8 Address,
IN UINT8 AndMask,
IN UINT8 OrMask,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Result;
ReadEc8 (Address, &Result, StdHeader);
Result = (Result & AndMask) | OrMask;
WriteEc8 (Address, &Result, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* WriteEc8 - Write date into EC register
*
*
*
* @param[in] Address - EC Register Offset Value
* @param[in] Value - Write Data Buffer
* @param[in] StdHeader
*
*/
VOID
WriteEc8 (
IN UINT8 Address,
IN UINT8 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT16 EcIndexPortDword;
ReadPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4, AccessWidth16, &EcIndexPortDword, StdHeader);
EcIndexPortDword &= ~(BIT0);
LibAmdIoWrite (AccessWidth8, EcIndexPortDword, &Address, StdHeader);
LibAmdIoWrite (AccessWidth8, EcIndexPortDword + 1, Value, StdHeader);
}

61
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcLate.c
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@ -1,61 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Embedded Controller
*
* Init Ec Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_FCHECLATE_FILECODE
/**
* FchInitLateEc - Prepare Ec controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateEc (
IN VOID *FchDataPtr
)
{
}

61
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcMid.c
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@ -1,61 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Embedded Controller
*
* Init Ec Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_FCHECMID_FILECODE
/**
* FchInitMidIde - Config Ec controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidEc (
IN VOID *FchDataPtr
)
{
}

132
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/FchEcReset.c
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@ -1,132 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ec controller
*
* Init Ec Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_FCHECRESET_FILECODE
/**
* FchInitResetEc - Config Ec controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetEc (
IN VOID *FchDataPtr
)
{
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Enable config mode
//
EnterEcConfig (StdHeader);
//
//Do settings for mailbox - logical device 0x09
//
RwEc8 (0x07, 0x00, 0x09, StdHeader); ///switch to device 9 (Mailbox)
RwEc8 (0x60, 0x00, (MailBoxPort >> 8), StdHeader); ///set MSB of Mailbox port
RwEc8 (0x61, 0x00, (MailBoxPort & 0xFF), StdHeader); ///set LSB of Mailbox port
RwEc8 (0x30, 0x00, 0x01, StdHeader); ///;Enable Mailbox Registers Interface, bit0=1
if ( LocalCfgPtr->EcKbd == ENABLED) {
//
//Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD6, AccessWidth8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);
//
//Disable LPC Decoding of port 60/64
//
RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG47), AccessWidth8, ~BIT5, 0, StdHeader);
//
//Enable logical device 0x07 (Keyboard controller)
//
RwEc8 (0x07, 0x00, 0x07, StdHeader);
RwEc8 (0x30, 0x00, 0x01, StdHeader);
}
if (IsImcEnabled (StdHeader) && ( LocalCfgPtr->EcChannel0 == ENABLED)) {
//
//Logical device 0x03
//
RwEc8 (0x07, 0x00, 0x03, StdHeader);
RwEc8 (0x60, 0x00, 0x00, StdHeader);
RwEc8 (0x61, 0x00, 0x62, StdHeader);
RwEc8 (0x30, 0x00, 0x01, StdHeader); ///;Enable Device 3
}
//
//Enable EC (IMC) to generate SMI to BIOS
//
RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB3, AccessWidth8, ~BIT6, BIT6);
ExitEcConfig (StdHeader);
}
/**
* FchInitRecoveryLpc - Config Ec controller during Crisis
* Recovery
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitRecoveryEc (
IN VOID *FchDataPtr
)
{
}

153
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcEnv.c
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@ -1,153 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Imc controller
*
* Init Imc Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_IMCENV_FILECODE
extern VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
//
// Declaration of local functions
//
/**
* FchInitEnvImc - Config Imc controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvImc (
IN VOID *FchDataPtr
)
{
UINT8 PortStatusByte;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
GetChipSysMode (&PortStatusByte, LocalCfgPtr->StdHeader);
ImcEnableSurebootTimer (LocalCfgPtr);
//
// Software IMC enable
//
if (((LocalCfgPtr->Imc.ImcEnableOverWrite == 1) && ((PortStatusByte & ChipSysEcEnable) == 0)) || ((LocalCfgPtr->Imc.ImcEnableOverWrite == 2) && ((PortStatusByte & ChipSysEcEnable) == ChipSysEcEnable))) {
if (ValidateImcFirmware (LocalCfgPtr)) {
SoftwareToggleImcStrapping (LocalCfgPtr);
}
}
FchInitEnvEc (LocalCfgPtr);
}
/**
* ValidateImcFirmware - Validate IMC Firmware.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
* @retval TRUE Pass
* @retval FALSE Failed
*/
BOOLEAN
ValidateImcFirmware (
IN VOID *FchDataPtr
)
{
UINT32 ImcSig;
UINT32 ImcSigAddr;
UINT32 ImcAddr;
UINT32 CurAddr;
UINT32 ImcBinSig0;
UINT32 ImcBinSig1;
UINT16 ImcBinSig2;
UINT8 IMCChecksumeByte;
UINT8 IMCByte;
ImcAddr = 0;
//
// Software IMC enable
//
ImcSigAddr = 0x80000; /// start from 512k to 64M
ImcSig = 0x0;
while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {
CurAddr = 0xffffffff - ImcSigAddr + 0x20001;
ReadMem (CurAddr, AccessWidth32, &ImcSig);
ReadMem ((CurAddr + 4), AccessWidth32, &ImcAddr);
ImcSigAddr <<= 1;
}
IMCChecksumeByte = 0xff;
if ( ImcSig == 0x55aa55aa ) {
//
// "_AMD_IMC_C" at offset 0x2000 of the binary
//
ReadMem ((ImcAddr + 0x2000), AccessWidth32, &ImcBinSig0);
ReadMem ((ImcAddr + 0x2004), AccessWidth32, &ImcBinSig1);
ReadMem ((ImcAddr + 0x2008), AccessWidth16, &ImcBinSig2);
if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {
IMCChecksumeByte = 0;
for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {
ReadMem (CurAddr, AccessWidth8, &IMCByte);
IMCChecksumeByte = IMCChecksumeByte + IMCByte;
}
}
}
if ( IMCChecksumeByte ) {
return FALSE;
} else {
return TRUE;
}
}

82
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLate.c
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@ -1,82 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Imc controller
*
* Init Imc Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_IMCLATE_FILECODE
/**
* FchInitLateImc - Prepare Imc controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateImc (
IN VOID *FchDataPtr
)
{
ImcDisarmSurebootTimer (FchDataPtr);
FchInitLateEc (FchDataPtr);
}
/**
* ImcDisarmSurebootTimer - IMC Disarm Sureboot Timer.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcDisarmSurebootTimer (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
ImcDisableSurebootTimer (LocalCfgPtr);
LocalCfgPtr->Imc.ImcSureBootTimer = 0;
}

279
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcLib.c
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@ -1,279 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH IMC lib
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_IMCLIB_FILECODE
VOID
WriteECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
IN VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Index;
ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
OpFlag = (OpFlag & 0x7f) - 1;
if (OpFlag == 0x02) OpFlag = 0x03;
for (Index = 0; Index <= OpFlag; Index++) {
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader);
Address++;
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoWrite (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader);
}
}
VOID
ReadECmsg (
IN UINT8 Address,
IN UINT8 OpFlag,
OUT VOID *Value,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Index;
ASSERT (OpFlag < AccessWidth64); /* TODO: Add the assertion to make it not crash for now. */
OpFlag = (OpFlag & 0x7f) - 1;
if (OpFlag == 0x02) OpFlag = 0x03;
for (Index = 0; Index <= OpFlag; Index++) {
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoWrite (AccessWidth8, 0x3E, &Address, StdHeader);
Address++;
/// EC_LDN9_MAILBOX_BASE_ADDRESS
LibAmdIoRead (AccessWidth8, 0x3F, (UINT8 *)Value + Index, StdHeader);
}
}
VOID
WaitForEcLDN9MailboxCmdAck (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Msgdata;
UINT16 Delaytime;
Msgdata = 0;
for (Delaytime = 0; Delaytime <= 500; Delaytime++) {
ReadECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
if ( Msgdata == 0xfa) {
break;
}
FchStall (1000, StdHeader); /// Wait for 1ms
}
}
/**
* ImcSleep - IMC Sleep.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcSleep (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0xB4;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x96;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
/**
* ImcEnableSurebootTimer - IMC Enable Sureboot Timer.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcEnableSurebootTimer (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
ImcDisableSurebootTimer (LocalCfgPtr);
Msgdata = 0x00;
if (!(IsImcEnabled (StdHeader)) || (LocalCfgPtr->Imc.ImcSureBootTimer == 0)) {
return; ///IMC is not enabled
}
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = ( (LocalCfgPtr->Imc.ImcSureBootTimer) << 6) -1;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x94;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
/**
* ImcDisableSurebootTimer - IMC Disable Sureboot Timer.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcDisableSurebootTimer (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x94;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
/**
* ImcWakeup - IMC Wakeup.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcWakeup (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0xB5;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x96;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
/**
* ImcIdle - IMC Idle.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ImcIdle (
IN VOID *FchDataPtr
)
{
UINT8 Msgdata;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
if (!(IsImcEnabled (StdHeader)) ) {
return; ///IMC is not enabled
}
Msgdata = 0x00;
WriteECmsg (MSG_REG0, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x01;
WriteECmsg (MSG_REG1, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x00;
WriteECmsg (MSG_REG2, AccessWidth8, &Msgdata, StdHeader);
Msgdata = 0x98;
WriteECmsg (MSG_SYS_TO_IMC, AccessWidth8, &Msgdata, StdHeader);
WaitForEcLDN9MailboxCmdAck (StdHeader);
}

63
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcMid.c
View File

@ -1,63 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Imc controller
*
* Init Imc Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_IMC_IMCMID_FILECODE
/**
* FchInitMidImc - Config Imc controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidImc (
IN VOID *FchDataPtr
)
{
ImcEnableSurebootTimer (FchDataPtr);
FchInitMidEc (FchDataPtr);
}

94
src/vendorcode/amd/agesa/f12/Proc/Fch/Imc/ImcReset.c
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@ -1,94 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Imc controller
*
* Init Imc Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IMC_IMCRESET_FILECODE
/**
* FchInitResetImc - Config Imc controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetImc (
IN VOID *FchDataPtr
)
{
UINT8 PortStatusByte;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
if ( ((PortStatusByte & ChipSysEcEnable) == 0x00) ) {
//
// EC is disabled by jumper setting or board config
//
RwPci (((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGA4), AccessWidth16, 0xFFFE, BIT0, StdHeader);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xF7, 0x08);
FchInitResetEc (FchDataPtr);
// ecPowerOnInit ( FchDataPtr);
ImcSleep (FchDataPtr);
}
}
/**
* FchInitRecoveryLpc - Config Imc controller during Crisis
* Recovery
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitRecoveryImc (
IN VOID *FchDataPtr
)
{
}

355
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/EnvDefHudson2.c
View File

@ -1,355 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Graphics Controller family specific service procedure
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "FchPlatform.h"
#include "Filecode.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------
* InitEnv Phase Data Block Default (Failsafe)
*----------------------------------------------------------------
*/
FCH_DATA_BLOCK InitEnvCfgDefault = {
NULL, // StdHeader
{ // FCH_ACPI
0xB00, // Smbus0BaseAddress
0xB20, // Smbus1BaseAddress
0xE00, // SioPmeBaseAddress
0xFEC00000, // WatchDogTimerBase
0x400, // AcpiPm1EvtBlkAddr
0x404, // AcpiPm1CntBlkAddr
0x408, // AcpiPmTmrBlkAddr
0x410, // CpuControlBlkAddr
0x420, // AcpiGpe0BlkAddr
0x00B0, // SmiCmdPortAddr
0xFE00, // AcpiPmaCntBlkAddr
TRUE, // AnyHt200MhzLink
TRUE, // SpreadSpectrum
UsePrevious, // PwrFailShadow
0, // StressResetMode
FALSE, // MtC1eEnable
NULL // OemProgrammingTablePtr
},
{ // FCH_AB
FALSE, // AbMsiEnable
0, // AlinkPhyPllPowerDown
0, // ALinkClkGateOff
0, // BLinkClkGateOff
0, // AbClockGating
0, // GppClockGating
0, // UmiL1TimerOverride
0, // UmiLinkWidth
0, // UmiDynamicSpeedChange
0, // PcieRefClockOverClocking
0, // UmiGppTxDriverStrength
FALSE, // NbSbGen2
0, // FchPcieOrderRule
0, // SlowSpeedAbLinkClock
0 // ResetCpuOnSyncFlood
},
{ // FCH_GPP
{ // Array of FCH_GPP_PORT_CONFIG PortCfg[4]
{
FALSE, // PortPresent
FALSE, // PortDetected
FALSE, // PortIsGen2
FALSE, // PortHotPlug
0, // PortMisc
},
{
FALSE, // PortPresent
FALSE, // PortDetected
FALSE, // PortIsGen2
FALSE, // PortHotPlug
0, // PortMisc
},
{
FALSE, // PortPresent
FALSE, // PortDetected
FALSE, // PortIsGen2
FALSE, // PortHotPlug
0, // PortMisc
},
{
FALSE, // PortPresent
FALSE, // PortDetected
FALSE, // PortIsGen2
FALSE, // PortHotPlug
0, // PortMisc
},
},
PortA4, // GppLinkConfig
0, // GppFoundGfxDev
0, // GppGen2
0, // GppGen2Strap
0, // GppMemWrImprove
FALSE, // GppFunctionEnable
0, // GppUnhidePorts
0, // GppPortAspm
0, // GppLaneReversal
0, // GppPhyPllPowerDown
0, // GppDynamicPowerSaving
0, // PcieAer
0, // PcieRas
0, // PcieCompliance
0, // PcieSoftwareDownGrade
0, // GppHardwareDownGrade
FALSE, // GppToggleReset
},
{ // FCH_USB
TRUE, // Ohci1Enable
TRUE, // Ohci2Enable
TRUE, // Ohci3Enable
TRUE, // Ohci4Enable
TRUE, // Ehci1Enable
TRUE, // Ehci2Enable
TRUE, // Ehci3Enable
FALSE, // Xhci0Enable
FALSE, // Xhci1Enable
FALSE, // UsbMsiEnable
0, // OhciSsid
0, // Ohci4Ssid
0, // EhciSsid
0, // XhciSsid
FALSE // UsbPhyPowerDown
},
{ // FCH_SATA
FALSE, // SataMsiEnable
0x00000000, // SataIdeSsid
0x00000000, // SataRaidSsid
0x00000000, // SataRaid5Ssid
0x00000000, // SataAhciSsid
{ // SATA_ST
0, // SataModeReg
TRUE, // SataEnable
0, // Sata6AhciCap
TRUE, // SataSetMaxGen2
TRUE, // IdeEnable
0, // SataClkMode
},
0, // SataClass
0, // SataIdeMode
0, // SataDisUnusedIdePChannel
0, // SataDisUnusedIdeSChannel
0, // IdeDisUnusedIdePChannel
0, // IdeDisUnusedIdeSChannel
0, // SataOptionReserved
{ // SATA_PORT_ST
0, // SataPortReg
TRUE, // Port0
TRUE, // Port1
TRUE, // Port2
TRUE, // Port3
TRUE, // Port4
TRUE, // Port5
TRUE, // Port6
TRUE, // Port7
},
{ // SATA_PORT_ST
0, // SataPortReg
FALSE, // Port0
FALSE, // Port1
FALSE, // Port2
FALSE, // Port3
FALSE, // Port4
FALSE, // Port5
FALSE, // Port6
FALSE, // Port7
},
{ // SATA_PORT_MD
0, // SataPortMode
0, // Port0
0, // Port1
0, // Port2
0, // Port3
0, // Port4
0, // Port5
0, // Port6
0, // Port7
},
0, // SataAggrLinkPmCap
0, // SataPortMultCap
0, // SataClkAutoOff
0, // SataPscCap
0, // BiosOsHandOff
0, // SataFisBasedSwitching
0, // SataCccSupport
0, // SataSscCap
0, // SataMsiCapability
0, // SataForceRaid
0, // SataInternal100Spread
0, // SataDebugDummy
0, // SataTargetSupport8Device
0, // SataDisableGenericMode
0, // SataAhciEnclosureManagement:1
0, // SataSgpio0
0, // SataSgpio1
0, // SataPhyPllShutDown
TRUE, // SataHotRemovalEnh
{ // SATA_PORT_ST
0, // SataPortReg
FALSE, // Port0
FALSE, // Port1
FALSE, // Port2
FALSE, // Port3
FALSE, // Port4
FALSE, // Port5
FALSE, // Port6
FALSE, // Port7
},
0 // TempMmio
},
{ // FCH_SMBUS
0x00000000 // SmbusSsid
},
{ // FCH_IDE
TRUE, // IdeEnable
FALSE, // IdeMsiEnable
0x00000000 // IdeSsid
},
{ // FCH_AZALIA
AzDisable, // AzaliaEnable
FALSE, // AzaliaMsiEnable
0x00000000, // AzaliaSsid
0, // AzaliaPinCfg
0, // AzaliaFrontPanel
0, // FrontPanelDetected
0, // AzaliaSnoop
0, // AzaliaDummy
{ // AZALIA_PIN
0, // AzaliaSdin0
0, // AzaliaSdin1
0, // AzaliaSdin2
0, // AzaliaSdin3
},
NULL, // *AzaliaOemCodecTablePtr
NULL, // *AzaliaOemFpCodecTablePtr
},
{ // FCH_SPI
FALSE, // LpcMsiEnable
0x00000000, // LpcSsid
0, // RomBaseAddress
0, // Speed
0, // FastSpeed
0, // WriteSpeed
0, // Mode
0, // AutoMode
0, // BurstWrite
},
{ // FCH_PCIB
FALSE, // PcibMsiEnable
0x00000000, // PcibSsid
0x0F, // PciClks
0, // PcibClkStopOverride
FALSE, // PcibClockRun
},
{ // FCH_GEC
FALSE, // GecEnable
0, // GecPhyStatus
0, // GecPowerPolicy
0, // GecDebugBus
0xFED61000, // GecShadowRomBase
NULL, // *PtrDynamicGecRomAddress
},
{ // FCH_SD
SdDisable, // SdConfig
0, // Speed
0, // BitWidth
},
{0}, // FCH_HWM
{0}, // FCH_IR
{ // FCH_HPET
FALSE, // HpetEnable
0, // HpetTimer
TRUE, // HpetMsiDis
0xFED00000 // HpetBase
},
{ // FCH_GCPU
0, // AcDcMsg
0, // TimerTickTrack
0, // ClockInterruptTag
0, // OhciTrafficHanding
0, // EhciTrafficHanding
0, // GcpuMsgCMultiCore
0, // GcpuMsgCStage
},
{0}, // FCH_IMC
{FALSE}, // FCH_SERIALDB
{ // FCH_MISC
FALSE, // NativePcieSupport
FALSE, // S3Resume
FALSE, // RebootRequired
0, // FchVariant
0, // CG2PLL
}
};

87
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c
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@ -1,87 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Graphics Controller family specific service procedure
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44909 $ @e \$Date: 2011-01-10 18:45:45 +0800 (Mon, 10 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "FchPlatform.h"
#include "Filecode.h"
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------
* InitReset Phase Data Block Default (Failsafe)
*----------------------------------------------------------------
*/
FCH_RESET_DATA_BLOCK InitResetCfgDefault = {
NULL, // StdHeader
NULL, // FchReset
FALSE, // NbSbGen2
0, // FastSpeed
0, // WriteSpeed
0, // Mode
0, // AutoMode
0, // BurstWrite
FALSE, // SataIdeCombMdPriSecOpt
0, // Cg2Pll
FALSE, // EcKbd
FALSE, // LegacyFree
FALSE, // SataSetMaxGen2
9, // SataClkMode
0, // SataModeReg
FALSE, // SataInternal100Spread
2, // SpiSpeed
TRUE, // EcChannel0
FALSE, // SerialDebugBusEnable
FALSE // GppToggleReset
};

113
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitEnv.c
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@ -1,113 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Initialization.
*
* Init IOAPIC/IOMMU/Misc NB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49837 $ @e \$Date: 2011-03-30 04:31:05 +0800 (Wed, 30 Mar 2011) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "FchTaskLauncher.h"
#include "heapManager.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_INTERFACE_FCHINITENV_FILECODE
extern FCH_TASK_ENTRY *FchInitEnvTaskTable[];
extern FCH_INTERFACE FchInterfaceDefault;
/*----------------------------------------------------------------------------------------*/
/**
* FchInitEnv - Config Fch before PCI emulation
*
*
*
* @param[in] EnvParams
*
*/
AGESA_STATUS
FchInitEnv (
IN AMD_ENV_PARAMS *EnvParams
)
{
UINT8 i;
UINT8 Data;
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Enter... \n");
FchParams = FchInitEnvCreatePrivateData (EnvParams);
// Override internal data with IDS (Optional, internal build only)
IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_ENV, FchParams, FchParams->StdHeader);
//
//to_do-Initialize PCI IRQ routing registers for INTA#-INTH#
//
for (i = 0; i < 8; i++) {
Data = i | BIT7; // Select IRQ routing to APIC
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, &EnvParams->StdHeader);
Data = i | BIT4;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, &EnvParams->StdHeader);
}
AgesaFchOemCallout (FchParams);
Status = FchTaskLauncher (&FchInitEnvTaskTable[0], FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitEnv Exit... Status = [0x%x]\n", Status);
return Status;
}
/**
* A constructor for FCH build parameter structure at InitEnv stage
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in,out] EnvParams InitEnv configuration data block
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
FchEnvConstructor (
IN AMD_ENV_PARAMS *EnvParams
)
{
EnvParams->FchInterface = FchInterfaceDefault;
return AGESA_SUCCESS;
}

93
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitLate.c
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@ -1,93 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Initialization.
*
* Init IOAPIC/IOMMU/Misc NB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "FchTaskLauncher.h"
#include "heapManager.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_INTERFACE_FCHINITLATE_FILECODE
extern FCH_TASK_ENTRY *FchInitLateTaskTable[];
/*----------------------------------------------------------------------------------------*/
/**
* FchInitLate - Prepare Fch to boot to OS.
*
*
*
* @param[in] LateParams
*
*/
AGESA_STATUS
FchInitLate (
IN AMD_S3SAVE_PARAMS *LateParams
)
{
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Enter... \n");
FchParams = FchInitLoadDataBlock (&LateParams->FchInterface, &LateParams->StdHeader);
Status = FchTaskLauncher (&FchInitLateTaskTable[0], FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitLate Exit... Status = [0x%x]\n", Status);
return Status;
}
/**
* A constructor for FCH build parameter structure at InitLate stage
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in,out] LateParams
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
FchLateConstructor (
IN AMD_LATE_PARAMS *LateParams
)
{
return AGESA_SUCCESS;
}

91
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitMid.c
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@ -1,91 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Initialization.
*
* Init IOAPIC/IOMMU/Misc NB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "FchTaskLauncher.h"
#include "heapManager.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_INTERFACE_FCHINITMID_FILECODE
extern FCH_TASK_ENTRY *FchInitMidTaskTable[];
/**
* FchInitMid - Config Fch after PCI emulation
*
*
*
* @param[in] MidParams Fch configuration structure pointer.
*
*/
AGESA_STATUS
FchInitMid (
IN AMD_MID_PARAMS *MidParams
)
{
FCH_DATA_BLOCK *FchParams;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Enter... \n");
FchParams = FchInitLoadDataBlock (&MidParams->FchInterface, &MidParams->StdHeader);
Status = FchTaskLauncher (&FchInitMidTaskTable[0], FchParams);
IDS_HDT_CONSOLE (FCH_TRACE, " FchInitMid Exit... Status = [0x%x]\n", Status);
return Status;
}
/**
* A constructor for FCH build parameter structure at InitEnv stage
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] MidParams
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
FchMidConstructor (
IN AMD_MID_PARAMS *MidParams
)
{
return AGESA_SUCCESS;
}

100
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitReset.c
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@ -1,100 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Init during Power-On Reset
*
* Prepare FCH environment during power on stage
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "FchTaskLauncher.h"
#include "heapManager.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_INTERFACE_FCHINITRESET_FILECODE
extern FCH_TASK_ENTRY *FchInitResetTaskTable[];
extern FCH_RESET_INTERFACE FchResetInterfaceDefault;
/**
* FchInitReset - Config Fch during power on stage.
*
*
*
* @param[in] ResetParams
*
*/
AGESA_STATUS
FchInitReset (
IN AMD_RESET_PARAMS *ResetParams
)
{
FCH_RESET_DATA_BLOCK FchParams;
// Load private data block with default
FchInitResetLoadPrivateDefault (&FchParams, &ResetParams->StdHeader);
// Override external data with input parameters
FchParams.StdHeader = &ResetParams->StdHeader;
FchParams.FchReset = &ResetParams->FchInterface;
// Override internal data with IDS (Optional, internal build only)
IDS_OPTION_CALLOUT (IDS_CALLOUT_FCH_INIT_RESET, &FchParams, &ResetParams->StdHeader);
AgesaFchOemCallout (&FchParams);
return FchTaskLauncher (&FchInitResetTaskTable[0], &FchParams);
}
/**
* A constructor for FCH build parameter structure at InitReset stage
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] ResetParams
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
FchResetConstructor (
IN AMD_RESET_PARAMS *ResetParams
)
{
ResetParams->FchInterface = FchResetInterfaceDefault;
return AGESA_SUCCESS;
}

94
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchInitS3.c
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@ -1,94 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH Initialization.
*
* Init IOAPIC/IOMMU/Misc NB features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "FchTaskLauncher.h"
#define FILECODE PROC_FCH_INTERFACE_FCHINITS3_FILECODE
extern FCH_TASK_ENTRY *FchInitS3EarlyTaskTable[];
extern FCH_TASK_ENTRY *FchInitS3LateTaskTable[];
/*----------------------------------------------------------------------------------------*/
/**
* FchInitS3EarlyRestore - Config Fch before ACPI S3 resume PCI config device restore
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitS3EarlyRestore (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
AGESA_STATUS AgesaStatus;
FchDataPtr->Misc.S3Resume = 1;
AgesaStatus = FchTaskLauncher (&FchInitS3EarlyTaskTable[0], FchDataPtr);
FchDataPtr->Misc.S3Resume = 0;
}
/*----------------------------------------------------------------------------------------*/
/**
* FchInitS3LateRestore - Config Fch after ACPI S3 resume PCI config device restore
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitS3LateRestore (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
AGESA_STATUS AgesaStatus;
FchDataPtr->Misc.S3Resume = 1;
AgesaStatus = FchTaskLauncher (&FchInitS3LateTaskTable[0], FchDataPtr);
FchDataPtr->Misc.S3Resume = 0;
}

62
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.c
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@ -1,62 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH task launcher
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE
AGESA_STATUS
FchTaskLauncher (
IN FCH_TASK_ENTRY **TaskPtr,
IN VOID *FchCfg
)
{
// AGESA_STATUS AgesaStatus;
while (*TaskPtr != NULL) {
(*TaskPtr) (FchCfg);
TaskPtr++;
}
return AGESA_SUCCESS;
}

80
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/FchTaskLauncher.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH task launcher
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#ifndef _FCH_TASK_LAUNCHER_H_
#define _FCH_TASK_LAUNCHER_H_
VOID
FchInitResetLoadPrivateDefault (
IN FCH_RESET_DATA_BLOCK *FchParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
FCH_DATA_BLOCK*
FchInitEnvCreatePrivateData (
IN AMD_ENV_PARAMS *EnvParams
);
FCH_DATA_BLOCK*
FchInitLoadDataBlock (
IN FCH_INTERFACE *FchInterface,
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
FchTaskLauncher (
IN FCH_TASK_ENTRY **TaskPtr,
IN VOID *FchCfg
);
VOID
FchInitS3EarlyRestore (
IN FCH_DATA_BLOCK *FchDataPtr
);
VOID
FchInitS3LateRestore (
IN FCH_DATA_BLOCK *FchDataPtr
);
#endif

170
src/vendorcode/amd/agesa/f12/Proc/Fch/Interface/InitEnvDef.c
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@ -1,170 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Fch Init during POWER-ON
*
* Prepare Fch environment during power on stage.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49753 $ @e \$Date: 2011-03-29 04:51:46 +0800 (Tue, 29 Mar 2011) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Ids.h"
#include "heapManager.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_INTERFACE_INITENVDEF_FILECODE
extern FCH_DATA_BLOCK InitEnvCfgDefault;
FCH_DATA_BLOCK*
FchInitLoadDataBlock (
IN FCH_INTERFACE *FchInterface,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
FCH_DATA_BLOCK *FchParams;
LOCATE_HEAP_PTR LocHeapPtr;
AMD_CONFIG_PARAMS TempStdHeader;
AGESA_STATUS AgesaStatus;
TempStdHeader = *StdHeader;
TempStdHeader.HeapStatus = HEAP_SYSTEM_MEM;
// Locate the internal data block via heap manager
LocHeapPtr.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE;
AgesaStatus = HeapLocateBuffer (&LocHeapPtr, &TempStdHeader);
ASSERT (!AgesaStatus);
FchParams = (FCH_DATA_BLOCK *) LocHeapPtr.BufferPtr;
ASSERT (FchParams != NULL);
FchParams->StdHeader = StdHeader;
return FchParams;
}
FCH_DATA_BLOCK*
FchInitEnvCreatePrivateData (
IN AMD_ENV_PARAMS *EnvParams
)
{
FCH_DATA_BLOCK *FchParams;
ALLOCATE_HEAP_PARAMS AllocHeapParams;
AMD_CONFIG_PARAMS TempStdHeader;
AGESA_STATUS AgesaStatus;
TempStdHeader = EnvParams->StdHeader;
TempStdHeader.HeapStatus = HEAP_SYSTEM_MEM;
// First allocate internal data block via heap manager
AllocHeapParams.RequestedBufferSize = sizeof (FCH_DATA_BLOCK);
AllocHeapParams.Persist = HEAP_SYSTEM_MEM;
AllocHeapParams.BufferHandle = AMD_FCH_DATA_BLOCK_HANDLE;
AgesaStatus = HeapAllocateBuffer (&AllocHeapParams, &TempStdHeader);
ASSERT (!AgesaStatus);
FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr;
ASSERT (FchParams != NULL);
IDS_HDT_CONSOLE (FCH_TRACE, " FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
// Load private data block with default
LibAmdMemCopy (
(UINT8 *) FchParams,
(UINT8 *) &InitEnvCfgDefault,
sizeof (FCH_DATA_BLOCK),
&EnvParams->StdHeader
);
// Update with external parameters
FchParams->StdHeader = &EnvParams->StdHeader;
FchParams->Sd.SdConfig = EnvParams->FchInterface.SdConfig;
FchParams->Azalia.AzaliaEnable = EnvParams->FchInterface.AzaliaController;
FchParams->Ir.IrConfig = EnvParams->FchInterface.IrConfig;
FchParams->Ab.NbSbGen2 = EnvParams->FchInterface.UmiGen2;
FchParams->Sata.SataClass = EnvParams->FchInterface.SataClass;
FchParams->Sata.SataMode.SataEnable = EnvParams->FchInterface.SataEnable;
FchParams->Sata.SataMode.IdeEnable = EnvParams->FchInterface.IdeEnable;
FchParams->Sata.SataIdeMode = EnvParams->FchInterface.SataIdeMode;
FchParams->Usb.Ohci1Enable = EnvParams->FchInterface.Ohci1Enable;
FchParams->Usb.Ehci1Enable = EnvParams->FchInterface.Ohci1Enable;
FchParams->Usb.Ohci2Enable = EnvParams->FchInterface.Ohci2Enable;
FchParams->Usb.Ehci2Enable = EnvParams->FchInterface.Ohci2Enable;
FchParams->Usb.Ohci3Enable = EnvParams->FchInterface.Ohci3Enable;
FchParams->Usb.Ehci3Enable = EnvParams->FchInterface.Ohci3Enable;
FchParams->Usb.Ohci4Enable = EnvParams->FchInterface.Ohci4Enable;
FchParams->Usb.Xhci0Enable = EnvParams->FchInterface.XhciSwitch;
FchParams->Usb.Xhci1Enable = EnvParams->FchInterface.XhciSwitch;
FchParams->Gpp.GppFunctionEnable = EnvParams->FchInterface.GppEnable;
FchParams->HwAcpi.PwrFailShadow = EnvParams->FchInterface.FchPowerFail;
FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.CfgSmbus0BaseAddress;
FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.CfgSmbus1BaseAddress;
FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.CfgSioPmeBaseAddress;
FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.CfgAcpiPm1EvtBlkAddr;
FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.CfgAcpiPm1CntBlkAddr;
FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.CfgAcpiPmTmrBlkAddr;
FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.CfgCpuControlBlkAddr;
FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.CfgAcpiGpe0BlkAddr;
FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.CfgSmiCmdPortAddr;
FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.CfgAcpiPmaCntBlkAddr;
FchParams->HwAcpi.WatchDogTimerBase = UserOptions.CfgWatchDogTimerBase;
FchParams->Sata.SataRaid5Ssid = UserOptions.CfgSataRaid5Ssid;
FchParams->Sata.SataRaidSsid = UserOptions.CfgSataRaidSsid;
FchParams->Sata.SataAhciSsid = UserOptions.CfgSataAhciSsid;
FchParams->Sata.SataIdeSsid = UserOptions.CfgSataIdeSsid;
FchParams->Gec.GecShadowRomBase = UserOptions.CfgGecShadowRomBase;
FchParams->Spi.RomBaseAddress = UserOptions.CfgSpiRomBaseAddress;
FchParams->Spi.LpcSsid = UserOptions.CfgLpcSsid;
FchParams->Hpet.HpetBase = UserOptions.CfgHpetBaseAddress;
FchParams->Azalia.AzaliaSsid = UserOptions.CfgAzaliaSsid;
FchParams->Smbus.SmbusSsid = UserOptions.CfgSmbusSsid;
FchParams->Ide.IdeSsid = UserOptions.CfgIdeSsid;
FchParams->Usb.EhciSsid = UserOptions.CfgEhciSsid;
FchParams->Usb.OhciSsid = UserOptions.CfgOhciSsid;
FchParams->Gpp.GppLinkConfig = UserOptions.CfgFchGppLinkConfig;
FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.CfgFchGppPort0Present;
FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.CfgFchGppPort1Present;
FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.CfgFchGppPort2Present;
FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.CfgFchGppPort3Present;
FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.CfgFchGppPort0HotPlug;
FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.CfgFchGppPort1HotPlug;
FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.CfgFchGppPort2HotPlug;
FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.CfgFchGppPort3HotPlug;
return FchParams;
}

63
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@ -1,63 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Fch Init during POWER-ON
*
* Prepare Fch environment during power on stage.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*;********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#include "FchPlatform.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_INTERFACE_INITRESETDEF_FILECODE
extern FCH_RESET_DATA_BLOCK InitResetCfgDefault;
VOID
FchInitResetLoadPrivateDefault (
IN FCH_RESET_DATA_BLOCK *FchParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
LibAmdMemCopy (
(UINT8 *) FchParams,
(UINT8 *) &InitResetCfgDefault,
sizeof (FCH_RESET_DATA_BLOCK),
StdHeader
);
}

101
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@ -1,101 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ir controller
*
* Init Ir Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IR_IRENV_FILECODE
/**
* FchInitEnvIr - Config Ir controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvIr (
IN VOID *FchDataPtr
)
{
IR_CONFIG FchIrConfig;
UINT8 Data;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchIrConfig = LocalCfgPtr->Ir.IrConfig;
//
//IR init Logical device 0x05
//
if (FchIrConfig != IrDisable) {
EnterEcConfig (StdHeader);
RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller
RwEc8 (0x60, 0x00, 0x05, StdHeader); ///Set Base Address to 550h
RwEc8 (0x61, 0x00, 0x50, StdHeader);
RwEc8 (0x70, 0xF0, 0x05, StdHeader); ///Set IRQ to 05h
RwEc8 (0x30, 0x00, 0x01, StdHeader); ///Enable logical device 5, IR controller
Data = 0xAB;
LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader);
LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader);
Data = (((Data & 0xFC ) | 0x20) | (UINT8) FchIrConfig);
LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader);
ExitEcConfig (StdHeader);
Data = 0xA0; /// EC APIC index
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader);
Data = 0x05; /// IRQ5
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader);
} else {
EnterEcConfig (StdHeader);
RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller
RwEc8 (0x30, 0x00, 0x00, StdHeader); ///Disable logical device 5, IR controller
ExitEcConfig (StdHeader);
}
}

60
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@ -1,60 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ir controller
*
* Init Ir Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IR_IRLATE_FILECODE
/**
* FchInitLateIr - Prepare Ir controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateIr (
IN VOID *FchDataPtr
)
{
}

60
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@ -1,60 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ir controller
*
* Init Ir Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_IR_IRMID_FILECODE
/**
* FchInitMidIr - Config Ir controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidIr (
IN VOID *FchDataPtr
)
{
}

141
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@ -1,141 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* FCH oem definition
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44854 $ @e \$Date: 2011-01-07 16:48:51 +0800 (Fri, 07 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#define ACPI_SLEEP_TRAP 0x01
/**
* Module Specific Defines for platform BIOS
*
*/
/**
* PCIEX_BASE_ADDRESS - Define PCIE base address
*
* Option MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
*/
#ifdef MOVE_PCIEBAR_TO_F0000000
#define PCIEX_BASE_ADDRESS 0xF7000000
#else
#define PCIEX_BASE_ADDRESS 0xE0000000
#endif
#define SATA_IDE_MODE_SSID 0x78001022
/**
* SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
* Define value for SSID while SATA controller set to RAID mode.
*/
#define SATA_RAID_MODE_SSID 0x78021022
/**
* SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
* Define value for SSID while SATA controller set to RAID5 mode.
*/
#define SATA_RAID5_MODE_SSID 0x78031022
/**
* SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
* Define value for SSID while SATA controller set to AHCI mode.
*/
#define SATA_AHCI_SSID 0x78011022
/**
* OHCI_SSID - All FCH OHCI controllers SSID value.
*
*/
#define OHCI_SSID 0x78071022
/**
* EHCI_SSID - All FCH EHCI controllers SSID value.
*
*/
#define EHCI_SSID 0x78081022
/**
* OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
*
*/
#define OHCI4_SSID 0x78091022
/**
* SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
*
*/
#define SMBUS_SSID 0x780B1022
/**
* IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
*
*/
#define IDE_SSID 0x780C1022
/**
* AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
*
*/
#define AZALIA_SSID 0x780D1022
/**
* LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
*
*/
#define LPC_SSID 0x780E1022
/**
* PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
*
*/
#define PCIB_SSID 0x780F1022
#ifndef XHCI_SUPPORT
#define FCH_NO_XHCI_SUPPORT TRUE
#endif
#ifdef NO_EC_SUPPORT
#define FCH_NO_IMC_SUPPORT TRUE
#endif
#ifdef NO_EC_SUPPORT
#define FCH_NO_HWM_SUPPORT TRUE
#endif

107
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibEnv.c
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@ -1,107 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcib controller
*
* Init Pcib Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_PCIB_PCIBENV_FILECODE
/**
* FchInitEnvPcibPciTable - PCI device registers initial during
* early POST.
*
*/
REG8_MASK FchInitEnvPcibPciTable[] =
{
//
// PCIB Bridge (Bus 0, Dev 20, Func 4)
//
{0x00, PCIB_BUS_DEV_FUN, 0},
{FCH_PCIB_REG40, 0xFF, BIT5}, /// PCI-bridge Subtractive Decode
{FCH_PCIB_REG4B, 0xFF, BIT7}, ///
{FCH_PCIB_REG66, 0xFF, BIT4}, /// Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
{FCH_PCIB_REG65, 0xFF, BIT7}, /// proper operation of CLKRUN#.
{FCH_PCIB_REG0D, 0x00, 0x40}, /// Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
{FCH_PCIB_REG1B, 0x00, 0x40}, /// of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
{FCH_PCIB_REG66 + 1, 0xFF, BIT1}, /// Enable PCI bus GNT3#..
{0xFF, 0xFF, 0xFF},
};
/**
* FchInitEnvPcib - Config Pcib controller before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvPcib (
IN VOID *FchDataPtr
)
{
UINT8 VerbPciClks;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//Early post initialization of pci config space
//
ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader);
//
//Disable or Enable PCI Clks based on input
//
VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2);
RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, ~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader);
//
// PCIB MSI
//
if (LocalCfgPtr->Pcib.PcibMsiEnable) {
RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG40, AccessWidth8, ~BIT3, BIT3, StdHeader);
}
}

94
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@ -1,94 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcib controller
*
* Init Pcib Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_PCIB_PCIBLATE_FILECODE
/**
* FchInitLatePcib - Prepare Pcib controller to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLatePcib (
IN VOID *FchDataPtr
)
{
UINT8 Value;
UINT8 NStBit;
UINT8 NSBit;
UINT32 VarDd;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// We need to do the following setting in late post also because some bios core pci enumeration changes these values
// programmed during early post.
// Master Latency Timer
//
Value = 0x40;
WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG0D, AccessWidth8, &Value, StdHeader);
WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG1B, AccessWidth8, &Value, StdHeader);
//
// CLKRUN#
// FCH P2P AutoClock control settings.
// VarDd = (FchDataPtr->PcibAutoClkCtrlLow) | (FchDataPtr->PcibAutoClkCtrlLow);
//
if ( LocalCfgPtr->Pcib.PcibClockRun ) {
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG54, AccessWidth8, &Value);
NStBit = Value & 0x03;
NSBit = (Value & 0x3F ) >> 2;
VarDd = (4 + (NStBit * 2) + (( 17 + NSBit) * 3) + 4) | 0x01;
VarDd = 9; // for A12
WritePci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG4C, AccessWidth32, &VarDd, StdHeader);
}
VarDd = (LocalCfgPtr->Pcib.PcibClkStopOverride);
RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG50, AccessWidth16, 0x3F, (UINT16) (VarDd << 6), StdHeader);
}

60
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibMid.c
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@ -1,60 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcib controller
*
* Init Pcib Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_PCIB_PCIBMID_FILECODE
/**
* FchInitMidPcib - Config Pcib controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidPcib (
IN VOID *FchDataPtr
)
{
}

112
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcib/PcibReset.c
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@ -1,112 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcib controller
*
* Init Pcib Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 48244 $ @e \$Date: 2011-03-05 12:39:46 +0800 (Sat, 05 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE
/**
* FchInitResetPcibPciTable - Pcib device registers initial
* during the power on stage.
*
*
*
*
*/
REG8_MASK FchInitResetPcibPciTable[] =
{
//
// P2P Bridge (Bus 0, Dev 20, Func 4)
//
{0x00, PCIB_BUS_DEV_FUN, 0},
{FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},
// ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in Reset
// ENH261115: Add PCI port 80 support in Hudson-2/3. Platform bios define SB_PCIB_PORT_80_SUPPORT to support it
#ifdef SB_PCIB_PORT_80_SUPPORT
{FCH_PCIB_REG1C, 0x00, 0xF0},
{FCH_PCIB_REG1D, 0x00, 0x00},
{FCH_PCIB_REG04, 0x00, 0x21},
#endif
{FCH_PCIB_REG40, 0xDF, 0x20},
{FCH_PCIB_REG50, 0x02, 0x01},
{0xFF, 0xFF, 0xFF},
};
/**
* FchInitResetPcib - Config Pcib controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetPcib (
IN VOID *FchDataPtr
)
{
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
ProgramPciByteTable (
(REG8_MASK*) (&FchInitResetPcibPciTable[0]),
sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK),
StdHeader
);
}
/**
* FchInitRecoveryPcib - Config Pcib controller during Crisis
* Recovery
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitRecoveryPcib (
IN VOID *FchDataPtr
)
{
}

79
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbEnv.c
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@ -1,79 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ab Bridge
*
* Init Ab Bridge features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_ABENV_FILECODE
/**
* FchInitEnvAb - Config Ab Bridge before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAb (
IN VOID *FchDataPtr
)
{
FchInitEnvAbLinkInit (FchDataPtr);
}
/**
* FchInitEnvAbSpecial - Config Ab Bridge special timing
*
* This routine must separate with FchInitEnvAb and give Ab
* bridge little time to get ready
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAbSpecial (
IN VOID *FchDataPtr
)
{
}

75
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbLate.c
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@ -1,75 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ab Bridge
*
* Init Ab Bridge features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_ABLATE_FILECODE
/**
* FchInitLateAb - Prepare Ab Bridge to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateAb (
IN VOID *FchDataPtr
)
{
UINT32 AbValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
AbValue &= 0xf0;
if ( LocalCfgPtr->Ab.PcieOrderRule && AbValue ) {
AbValue = ReadAlink (FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), StdHeader);
AbValue = AbValue | BIT9;
WriteAlink (FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), AbValue, StdHeader);
}
}

62
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbMid.c
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@ -1,62 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ab Bridge
*
* Init Ab Bridge features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_ABMID_FILECODE
/**
* FchInitMidAb - Config Ab Bridge after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidAb (
IN VOID *FchDataPtr
)
{
}

64
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/AbReset.c
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@ -1,64 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Ab Bridge
*
* Init Ab Bridge features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#include "FchDef.h"
#define FILECODE PROC_FCH_PCIE_ABRESET_FILECODE
/**
* FchInitResetAb - Config Ab Bridge during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetAb (
IN VOID *FchDataPtr
)
{
FchProgramAbPowerOnReset (FchDataPtr);
}

360
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbEnvService.c
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@ -1,360 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Hudson2 AB
*
* Init AB bridge.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 48048 $ @e \$Date: 2011-03-03 10:13:06 +0800 (Thu, 03 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE
//
// Declaration of local functions
//
VOID AbCfgTbl (IN AB_TBL_ENTRY *ABTbl, IN AMD_CONFIG_PARAMS *StdHeader);
/**
* Hudson2PcieOrderRule - AB-Link Configuration Table for ablink
* Post Pass Np Downstream/Upstream Feature
*
*/
AB_TBL_ENTRY Hudson2PcieOrderRule[] =
{
//
// abPostPassNpDownStreamTbl
//
{ABCFG, FCH_ABCFG_REG10060, BIT31, BIT31},
{ABCFG, FCH_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},
{ABCFG, FCH_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},
{ABCFG, FCH_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},
{ABCFG, FCH_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},
{AXINDC, FCH_AX_INDXC_REG02, BIT9, BIT9},
{ABCFG, FCH_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},
//
// abPostPassNpUpStreamTbl
//
{ABCFG, FCH_ABCFG_REG58, BIT10, BIT10},
{ABCFG, FCH_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},
{ABCFG, FCH_ABCFG_REG54, BIT1, BIT1},
{ (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
};
/**
* Hudson2InitEnvAbTable - AB-Link Configuration Table for Hudson2
*
*/
AB_TBL_ENTRY Hudson2InitEnvAbTable[] =
{
//
// Enable downstream posted transactions to pass non-posted transactions.
//
{ABCFG, FCH_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},
//
// Enable Hudson-2 to issue memory read/write requests in the upstream direction.
//
{AXCFG, FCH_AB_REG04, BIT2, BIT2},
//
// Enabling IDE/PCIB Prefetch for Performance Enhancement
// PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1
//
{ABCFG, FCH_ABCFG_REG10060, BIT20, BIT20}, /// PCIB prefetch enable
{ABCFG, FCH_ABCFG_REG10064, BIT20, BIT20}, /// PCIB prefetch enable
//
// Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.
// Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)
//
{ABCFG, FCH_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},
//
// Enabled SMI ordering enhancement. ABCFG 0x90[21]
// USB Delay A-Link Express L1 State. ABCFG 0x90[17]
//
{ABCFG, FCH_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17},
//
// Disable the credit variable in the downstream arbitration equation
// Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)
//
{ABCFG, FCH_ABCFG_REG9C, BIT0, BIT0},
//
// Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
// ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
//
{ABCFG, FCH_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},
//
// Programming cycle delay for AB and BIF clock gating
// Enable the AB and BIF clock-gating logic.
// Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently
// Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP
//
{ABCFG, FCH_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF},
{ABCFG, FCH_ABCFG_REG98, 0xFFFC00FF, 0x00034700},
{ABCFG, FCH_ABCFG_REG54, 0x00FF0000, 0x00040000},
//
// Non-Posted Memory Write Support
//
{AXINDC, FCH_AX_INDXC_REG10, BIT9, BIT9},
//
// UMI L1 Configuration
//Step 1: AXINDC_Reg 0x02[0] = 0x1 Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs during L1 so that txclk can be turned off.
//Step 2: AXINDP_Reg 0x02[15] = 0x1 Sets REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to prevent LC from going to L1 when there are outstanding completions.
//
{AXINDC, FCH_AX_INDXC_REG02, BIT0, BIT0},
{AXINDP, FCH_AX_INDXP_REG02, BIT15, BIT15},
{ABCFG, 0, 0, (UINT8) 0xFF}, /// This dummy entry is to clear ab index
{ (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},
};
/**
* FchInitEnvAbLinkInit - Set ABCFG registers before PCI
* emulation.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvAbLinkInit (
IN VOID *FchDataPtr
)
{
UINT32 AbValue;
UINT16 AbTempVar;
UINT8 AbValue8;
UINT8 FchALinkClkGateOff;
UINT8 FchBLinkClkGateOff;
UINT32 FchResetCpuOnSyncFlood;
AB_TBL_ENTRY *AbTblPtr;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchALinkClkGateOff = (UINT8) LocalCfgPtr->Ab.ALinkClkGateOff;
FchBLinkClkGateOff = (UINT8) LocalCfgPtr->Ab.BLinkClkGateOff;
//
// AB CFG programming
//
if ( LocalCfgPtr->Ab.SlowSpeedAbLinkClock ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~BIT1, BIT1);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40, AccessWidth8, ~BIT1, 0);
}
//
// Read Arbiter address, Arbiter address is in PMIO 6Ch
//
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG6C, AccessWidth16, &AbTempVar);
/// Write 0 to enable the arbiter
AbValue8 = 0;
LibAmdIoWrite (AccessWidth8, AbTempVar, &AbValue8, StdHeader);
FchResetCpuOnSyncFlood = LocalCfgPtr->Ab.ResetCpuOnSyncFlood;
if ( LocalCfgPtr->Ab.PcieOrderRule == 1 ) {
AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2PcieOrderRule[0]);
AbCfgTbl (AbTblPtr, StdHeader);
}
if ( LocalCfgPtr->Ab.PcieOrderRule == 2 ) {
RwAlink (FCH_ABCFG_REG10090 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 10), (UINT32) (0x7 << 10), StdHeader);
RwAlink (FCH_ABCFG_REG58 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1F << 11), (UINT32) (0x1C << 11), StdHeader);
RwAlink (FCH_ABCFG_REGB4 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 0), (UINT32) (0x3 << 0), StdHeader);
}
AbTblPtr = (AB_TBL_ENTRY *) (&Hudson2InitEnvAbTable[0]);
AbCfgTbl (AbTblPtr, StdHeader);
if ( FchResetCpuOnSyncFlood ) {
RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2, StdHeader);
}
if ( LocalCfgPtr->Ab.AbClockGating ) {
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16), StdHeader);
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x1 << 24), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG10054 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 24), (UINT32) (0x0 << 24), StdHeader);
}
if ( LocalCfgPtr->Ab.GppClockGating ) {
RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 12), (UINT32) (0x4 << 12), StdHeader);
RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x7 << 8), StdHeader);
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
} else {
RwAlink (FCH_ABCFG_REG98 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xF << 8), (UINT32) (0x0 << 8), StdHeader);
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 0), (UINT32) (0x0 << 0), StdHeader);
}
if ( LocalCfgPtr->Ab.UmiL1TimerOverride ) {
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x7 << 12), (UINT32) (LocalCfgPtr->Ab.UmiL1TimerOverride << 12), StdHeader);
RwAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 15), (UINT32) (0x1 << 15), StdHeader);
}
if ( LocalCfgPtr->Ab.UmiLinkWidth ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
if ( LocalCfgPtr->Ab.UmiDynamicSpeedChange ) {
RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 0), (UINT32) (0x1 << 0), StdHeader);
RwAlink ((UINT32) FCH_AX_CFG_REG88, ~ (UINT32) (0xF << 0), (UINT32) (0x2 << 0), StdHeader);
RwAlink ((UINT32) FCH_AX_INDXP_REGA4, ~ (UINT32) (0x1 << 18), (UINT32) (0x1 << 18), StdHeader);
}
if ( LocalCfgPtr->Ab.PcieRefClockOverClocking ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
if ( LocalCfgPtr->Ab.UmiGppTxDriverStrength ) {
RwAlink (FCH_ABCFG_REGA8 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x3 << 18), (UINT32) ((LocalCfgPtr->Ab.UmiGppTxDriverStrength - 1) << 18), StdHeader);
RwAlink (FCH_ABCFG_REGA0 | (UINT32) (ABCFG << 29), ~ (UINT32) (0x1 << 8), (UINT32) (0x1 << 8), StdHeader);
}
if ( LocalCfgPtr->Gpp.PcieAer ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
if ( LocalCfgPtr->Gpp.PcieRas ) {
// RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~ (UINT32) (0xFF << 16), (UINT32) (0x4 << 16));
}
//
// Ab Bridge MSI
//
if ( LocalCfgPtr->Ab.AbMsiEnable) {
AbValue = ReadAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), StdHeader);
AbValue = AbValue | BIT20;
WriteAlink (FCH_ABCFG_REG94 | (UINT32) (ABCFG << 29), AbValue, StdHeader);
}
//
// A/B Clock Gate-OFF
//
if ( FchALinkClkGateOff ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, BIT0);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFE, 0x00);
}
if ( FchBLinkClkGateOff ) {
//RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2D, AccessWidth8, 0xEF, 0x10); /// A11 Only
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, BIT1);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x2E, AccessWidth8, 0xFD, 0x00);
}
}
/**
* AbCfgTbl - Program ABCFG by input table.
*
*
* @param[in] ABTbl ABCFG config table.
* @param[in] StdHeader
*
*/
VOID
AbCfgTbl (
IN AB_TBL_ENTRY *ABTbl,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 AbValue;
while ( (ABTbl->RegType) != 0xFF ) {
if ( ABTbl->RegType == AXINDC ) {
AbValue = 0x30 | (ABTbl->RegType << 29);
WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader);
AbValue = 0x34 | (ABTbl->RegType << 29);
WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
} else if ( ABTbl->RegType == AXINDP ) {
AbValue = 0x38 | (ABTbl->RegType << 29);
WriteAlink (AbValue, (ABTbl->RegIndex & 0x00FFFFFF), StdHeader);
AbValue = 0x3C | (ABTbl->RegType << 29);
WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
} else {
AbValue = ABTbl->RegIndex | (ABTbl->RegType << 29);
WriteAlink (AbValue, ((ReadAlink (AbValue, StdHeader)) & (0xFFFFFFFF^ (ABTbl->RegMask))) | ABTbl->RegData, StdHeader);
}
++ABTbl;
}
//
//Clear ALink Access Index
//
AbValue = 0;
LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &AbValue, StdHeader);
}
/**
* Is UMI One Lane GEN1 Mode?
*
*
* @retval TRUE or FALSE
*
*/
BOOLEAN
IsUmiOneLaneGen1Mode (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 AbValue;
AbValue = ReadAlink ((UINT32) (FCH_AX_CFG_REG68), StdHeader);
AbValue >>= 16;
if (((AbValue & 0x0f) == 1) && ((AbValue & 0x03f0) == 0x0010)) {
return (TRUE);
} else {
return (FALSE);
}
}

126
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbResetService.c
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@ -1,126 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Hudson2 AB
*
* Init AB bridge.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 47163 $ @e \$Date: 2011-02-16 07:23:13 +0800 (Wed, 16 Feb 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE
/**
* FchProgramAbPowerOnReset - Config Ab Bridge during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchProgramAbPowerOnReset (
IN VOID *FchDataPtr
)
{
UINT32 AbValue;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 EfuseValue;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Set A-Link bridge access address.
// This is an I/O address. The I/O address must be on 16-byte boundary.
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE0, AccessWidth32, 00, ALINK_ACCESS_INDEX);
//
// Enable Hudson-2 to issue memory read/write requests in the upstream direction
//
WriteAlink (0x80000004, 0x04, StdHeader);
//
// Disable the credit variable in the downstream arbitration equation
//
AbValue = ReadAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), StdHeader);
AbValue = AbValue | BIT0;
WriteAlink (FCH_ABCFG_REG9C | (UINT32) (ABCFG << 29), AbValue, StdHeader);
//
// AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
//
WriteAlink (0x30, 0x10, StdHeader);
WriteAlink (0x34, ReadAlink (0x34, StdHeader) | BIT9, StdHeader);
RwAlink (FCH_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00, StdHeader);
//
// Configure UMI target link speed
//
EfuseValue = PCIE_FORCE_GEN1_EFUSE_LOCATION;
GetEfuseStatus (&EfuseValue, StdHeader);
if ( EfuseValue & BIT0 ) {
LocalCfgPtr->NbSbGen2 = 0;
}
EfuseValue = FCH_Variant_EFUSE_LOCATION;
GetEfuseStatus (&EfuseValue, StdHeader);
if ((EfuseValue == 0x07) || (EfuseValue == 0x08)) {
LocalCfgPtr->NbSbGen2 = 0;
}
if (LocalCfgPtr->NbSbGen2) {
AbValue = 2;
} else {
AbValue = 1;
}
RwAlink ((UINT32)FCH_AX_CFG_REG88, 0xFFFFFFF0, AbValue, StdHeader);
if (LocalCfgPtr->NbSbGen2) {
AbValue = BIT0;
} else {
AbValue = 0;
}
RwAlink (FCH_AX_INDXP_REGA4, 0xFFFFFFFE, AbValue, StdHeader);
}

47
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2AbService.c
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@ -1,47 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Hudson2 AB
*
* Init AB bridge.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE

123
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppResetService.c
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@ -1,123 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Hudson2 Pcie controller
*
* Init GPP (pcie Controller) features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44855 $ @e \$Date: 2011-01-07 16:51:55 +0800 (Fri, 07 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE
/**
* ProgramFchGppInitReset - Config Gpp at PowerOnReset
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramFchGppInitReset (
IN VOID *FchDataPtr
)
{
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
//
// Toggle GEVENT4 to reset all GPP devices
//
ProgramGppTogglePcieReset (LocalCfgPtr->GppToggleReset, LocalCfgPtr->StdHeader);
if (LocalCfgPtr->SerialDebugBusEnable) {
RwAlink (FCH_ABCFG_REGC0, (UINT32) (ABCFG << 29), ~BIT12, 0x00);
}
}
/**
* FchResetPcie - Toggle GEVENT4 to assert/deassert GPP device
* reset
*
*
* @param[in] ResetBlock - PCIE reset for FCH GPP or NB PCIE
* @param[in] ResetOp - Assert or deassert PCIE reset
* @param[in] StdHeader
*
*/
VOID
FchResetPcie (
IN RESET_BLOCK ResetBlock,
IN RESET_OP ResetOp,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 Or8;
UINT8 Mask8;
if (ResetBlock == NbBlock) {
if (ResetOp == AssertReset) {
Or8 = BIT4;
Mask8 = 0;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader);
} else if (ResetOp == DeassertReset) {
Or8 = 0;
Mask8 = BIT4;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader);
}
} else if (ResetBlock == FchBlock) {
Or8 = BIT1;
Mask8 = BIT1 + BIT0;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
if (ResetOp == AssertReset) {
Or8 = 0;
Mask8 = BIT5;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
Or8 = BIT4;
Mask8 = 0;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader);
} else if (ResetOp == DeassertReset) {
Or8 = 0;
Mask8 = BIT4;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader);
Or8 = BIT5;
Mask8 = 0;
LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader);
}
}
}

207
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2GppService.c
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@ -1,207 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Hudson2 Pcie controller
*
* Init GPP (pcie Controller) features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE
/**
* ProgramGppTogglePcieReset - Toggle PCIE_RST2#
*
*
* @param[in] DoToggling
* @param[in] StdHeader
*
*/
VOID
ProgramGppTogglePcieReset (
IN BOOLEAN DoToggling,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
if (DoToggling) {
FchResetPcie (FchBlock, AssertReset, StdHeader);
FchStall (500, StdHeader);
FchResetPcie (FchBlock, DeassertReset, StdHeader);
} else {
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, ~(BIT1 + BIT0), 0x02);
}
}
/**
* FchGppDynamicPowerSaving - GPP Dynamic Power Saving
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchGppDynamicPowerSaving (
IN VOID *FchDataPtr
)
{
FCH_GPP_PORT_CONFIG *PortCfg;
UINT8 FchGppLaneReversal;
UINT8 FchAlinkPhyPllPowerDown;
UINT8 FchGppPhyPllPowerDown;
UINT32 GppData32;
UINT32 HoldGppData32;
UINT32 AbValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if (!LocalCfgPtr->Gpp.GppDynamicPowerSaving || LocalCfgPtr->SerialDb.SerialDebugBusEnable) {
return;
}
FchAlinkPhyPllPowerDown = (UINT8) LocalCfgPtr->Ab.UmiPhyPllPowerDown;
FchGppLaneReversal = (UINT8) LocalCfgPtr->Gpp.GppLaneReversal;
FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown;
if (LocalCfgPtr->Gpp.GppHardwareDownGrade) {
PortCfg = &LocalCfgPtr->Gpp.PortCfg[LocalCfgPtr->Gpp.GppHardwareDownGrade - 1];
PortCfg->PortDetected = TRUE;
}
GppData32 = 0;
HoldGppData32 = 0;
switch ( LocalCfgPtr->Gpp.GppLinkConfig ) {
case PortA4:
PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= 0x0f0f;
HoldGppData32 |= 0x1000;
}
break;
case PortA2B2:
PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0c0c:0x0303;
HoldGppData32 |= 0x1000;
}
PortCfg = &LocalCfgPtr->Gpp.PortCfg[1];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0303:0x0c0c;
HoldGppData32 |= 0x2000;
}
break;
case PortA2B1C1:
PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0c0c:0x0303;
HoldGppData32 |= 0x1000;
}
PortCfg = &LocalCfgPtr->Gpp.PortCfg[1];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0202:0x0404;
HoldGppData32 |= 0x2000;
}
PortCfg = &LocalCfgPtr->Gpp.PortCfg[2];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0101:0x0808;
HoldGppData32 |= 0x4000;
}
break;
case PortA1B1C1D1:
PortCfg = &LocalCfgPtr->Gpp.PortCfg[0];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0808:0x0101;
HoldGppData32 |= 0x1000;
}
PortCfg = &LocalCfgPtr->Gpp.PortCfg[1];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0404:0x0202;
HoldGppData32 |= 0x2000;
}
PortCfg = &LocalCfgPtr->Gpp.PortCfg[2];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0202:0x0404;
HoldGppData32 |= 0x4000;
}
PortCfg = &LocalCfgPtr->Gpp.PortCfg[3];
if ( PortCfg->PortDetected == FALSE ) {
GppData32 |= ( FchGppLaneReversal )? 0x0101:0x0808;
HoldGppData32 |= 0x8000;
}
break;
default:
ASSERT (FALSE);
break;
}
//
// Power Saving With GPP Disable
// ABCFG 0xC0[8] = 0x0
// ABCFG 0xC0[15:12] = 0xF
// Enable "Power Saving Feature for A-Link Express Lanes"
// Enable "Power Saving Feature for GPP Lanes"
// ABCFG 0x90[19] = 1
// ABCFG 0x90[6] = 1
// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
// ABCFG 0xC0[7:4] = 0x0
//
if ( FchAlinkPhyPllPowerDown && FchGppPhyPllPowerDown ) {
AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( AbValue | HoldGppData32 ) & (~ BIT8 )), StdHeader);
RwAlink (FCH_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader);
RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19), StdHeader);
RwAlink (RC_INDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader);
RwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader);
}
}

77
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieEnvService.c
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Hudson2 Pcie controller
*
* Init Pcie Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 46088 $ @e \$Date: 2011-01-28 11:24:26 +0800 (Fri, 28 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE
/**
* ProgramPcieNativeMode - Config Pcie Native Mode
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
ProgramPcieNativeMode (
IN VOID *FchDataPtr
)
{
UINT8 FchNativepciesupport;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
FchNativepciesupport = (UINT8) LocalCfgPtr->Misc.NativePcieSupport;
//
// PCIE Native setting
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBA + 1, AccessWidth8, ~BIT14, 0);
if ( FchNativepciesupport == 1) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG74 + 3, AccessWidth8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2 + BIT0);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG74 + 3, AccessWidth8, ~(BIT3 + BIT1 + BIT0), BIT3 + BIT2);
}
}

46
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/Family/Hudson2/Hudson2PcieService.c
View File

@ -1,46 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Hudson2 Pcie controller
*
* Init Pcie Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE

562
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppEnv.c
View File

@ -1,562 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Gpp controller
*
* Init Gpp Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49753 $ @e \$Date: 2011-03-29 04:51:46 +0800 (Tue, 29 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_GPPENV_FILECODE
//
// Declaration of local functions
//
VOID FchGppRasInitialization (IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchGppAerInitialization (IN FCH_DATA_BLOCK* FchDataPtr);
VOID PreInitGppLink (IN FCH_DATA_BLOCK* FchDataPtr);
UINT8 CheckGppLinkStatus (IN FCH_DATA_BLOCK* FchDataPtr);
VOID AfterGppLinkInit (IN FCH_DATA_BLOCK* FchDataPtr);
//
//-----------------------------------------------------------------------------------
// Early GPP initialization sequence:
//
// 1) Set port enable bit fields by current GPP link configuration mode
// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
// 3) Loop polling for the link status of all ports
// 4) Misc operations after link training:
// - (optional) Detect GFX device
// - Hide empty GPP configuration spaces (Disable empty GPP ports)
// - (optional) Power down unused GPP ports
// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
// 5) GPP init completed
//
//
// *) Gen2 vs Gen1
// Gen2 mode Gen1 mode
// ---------------------------------------------------------------
// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19
// STRAP_BIF_GEN2_EN 1 0
//
// PCIE_PHY_PLL clock locks @ 5GHz
//
//
/**
* FchInitEnvGpp - Config Gpp controller before PCI emulation
*
* - GppEarlyInit
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvGpp (
IN VOID *FchDataPtr
)
{
//
// GppEarlyInit
//
UINT8 FchGppMemWrImprove;
UINT8 FchGppLaneReversal;
UINT8 FchAlinkPhyPllPowerDown;
UINT32 AbValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchGppMemWrImprove = LocalCfgPtr->Gpp.GppMemWrImprove;
FchGppLaneReversal = (UINT8) LocalCfgPtr->Gpp.GppLaneReversal;
FchAlinkPhyPllPowerDown = (UINT8) LocalCfgPtr->Ab.UmiPhyPllPowerDown;
OutPort80 (0x90, StdHeader);
//
// Configure NB-FCH link PCIE PHY PLL power down for L1
//
if ( FchAlinkPhyPllPowerDown == TRUE ) {
//
// Set PCIE_P_CNTL in Alink PCIEIND space
//
WriteAlink (FCH_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40, StdHeader);
AbValue = ReadAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), StdHeader);
AbValue |= BIT12 + BIT3 + BIT0;
AbValue &= ~(BIT9 + BIT4);
WriteAlink (FCH_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), AbValue, StdHeader);
RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT8), (BIT8), StdHeader);
RwAlink (FCH_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~(BIT3), (BIT3), StdHeader);
}
//
// AXINDC_Reg 0xA4[18] = 0x1
//
WriteAlink (FCH_AX_INDXP_REG38 | (UINT32) (AXINDP << 29), 0xA4, StdHeader);
AbValue = ReadAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), StdHeader);
AbValue |= BIT18;
WriteAlink (FCH_AX_DATAP_REG3C | (UINT32) (AXINDP << 29), AbValue, StdHeader);
//
// Set ABCFG 0x031C[0] = 1 to enable lane reversal
//
AbValue = ReadAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), StdHeader);
if ( FchGppLaneReversal ) {
WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | BIT0, StdHeader);
} else {
WriteAlink (FCH_ABCFG_REG31C | (UINT32) (ABCFG << 29), AbValue | 0x00, StdHeader);
}
//
// Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function
//
AbValue = ReadAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), StdHeader);
WriteAlink (FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29), AbValue | BIT20, StdHeader);
//
// Initialize and configure GPP
//
if (LocalCfgPtr->Gpp.GppFunctionEnable) {
ProgramGppTogglePcieReset (LocalCfgPtr->Gpp.GppToggleReset, StdHeader);
FchGppAerInitialization (LocalCfgPtr);
FchGppRasInitialization (LocalCfgPtr);
//
// PreInit - Enable GPP link training
//
PreInitGppLink (LocalCfgPtr);
//
// GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1
// GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4
//
if ( FchGppMemWrImprove == TRUE ) {
RwAlink (FCH_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26), StdHeader);
RwAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12), StdHeader);
}
if (CheckGppLinkStatus (LocalCfgPtr) && !LocalCfgPtr->Misc.S3Resume) {
//
// Toggle GPP reset (Note this affects all Hudson-2 GPP ports)
//
ProgramGppTogglePcieReset (LocalCfgPtr->Gpp.GppToggleReset, StdHeader);
}
//
// Misc operations after link training
//
AfterGppLinkInit (LocalCfgPtr);
}
FchGppDynamicPowerSaving (LocalCfgPtr);
OutPort80 (0x9F, StdHeader);
}
/**
* FchGppAerInitialization - Initializing AER
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchGppAerInitialization (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = FchDataPtr->StdHeader;
if (FchDataPtr->Gpp.PcieAer) {
//
// GPP strap configuration
//
RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), ~(BIT7 + BIT4), BIT28 + BIT27 + BIT26 + BIT1, StdHeader);
RwAlink (FCH_ABCFG_REG314 | (UINT32) (ABCFG << 29), ~(UINT32) (0xfff << 15), 0, StdHeader);
//
// AB strap configuration
//
RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT15 + BIT14, StdHeader);
RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT3, StdHeader);
} else {
//
// Hard System Hang running MeatGrinder Test on multiple blocks
// GPP Error Reporting Configuration
RwAlink (FCH_ABCFG_REGF0 | (UINT32) (ABCFG << 29), ~(BIT1), 0, StdHeader);
}
}
/**
* FchGppRasInitialization - Initializing RAS
*
*
* @param[in] FchDataPtr
*
*/
VOID
FchGppRasInitialization (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
if (FchDataPtr->Gpp.PcieRas) {
RwAlink (FCH_ABCFG_REGF4 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT0, FchDataPtr->StdHeader);
}
}
/**
* PreInitGppLink - Enable GPP link training.
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
PreInitGppLink (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
GPP_LINKMODE CfgMode;
UINT8 PortId;
UINT32 GppPortCfg;
UINT16 Tmp16Value;
FCH_GPP_PORT_CONFIG *PortCfg;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 PortMask[5] = {
0x01,
0x00,
0x03,
0x07,
0x0F
};
//
// PCIE_GPP_ENABLE (abcfg:0xC0):
//
// GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description
// ----------------------------------------------------------------------------------
// 0000 0-3 x4 Config
// 0001 N/A
// 0010 0-1 2-3 0 2:2 Config
// 0011 0-1 2 3 2:1:1 Config
// 0100 0 1 2 3 1:1:1:1 Config
//
// For A12 and above:
// ABCFG:0xC0[12] - Port A hold training (default 1)
// ABCFG:0xC0[13] - Port B hold training (default 1)
// ABCFG:0xC0[14] - Port C hold training (default 1)
// ABCFG:0xC0[15] - Port D hold training (default 1)
//
//
//
// Set port enable bit fields based on current GPP link configuration mode
//
CfgMode = FchDataPtr->Gpp.GppLinkConfig;
StdHeader = FchDataPtr->StdHeader;
ASSERT (CfgMode == PortA4 || CfgMode == PortA2B2 || CfgMode == PortA2B1C1 || CfgMode == PortA1B1C1D1);
GppPortCfg = (UINT32) PortMask[CfgMode];
//
// Mask out non-applicable ports according to the target link configuration mode
//
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
FchDataPtr->Gpp.PortCfg[PortId].PortPresent &= (UINT8 ) (GppPortCfg >> PortId) & BIT0;
}
//
// Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
//
Tmp16Value = (UINT16) (~GppPortCfg << 12);
GppPortCfg = (UINT32) (Tmp16Value + (GppPortCfg << 4) + CfgMode);
WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), GppPortCfg, StdHeader);
GppPortCfg = ReadAlink (0xC0 | (UINT32) (RCINDXC << 29), StdHeader);
WriteAlink (0xC0 | (UINT32) (RCINDXC << 29), GppPortCfg | 0x400, StdHeader); /// Set STRAP_F0_MSI_EN
//
// A-Link L1 Entry Delay Shortening
// AXINDP_Reg 0xA0[7:4] = 0x3
// KR Does not need this portion of code.
RwAlink (FCH_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30, StdHeader);
RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19, StdHeader);
RwAlink (FCH_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28, StdHeader);
//
// GPP L1 Entry Delay Shortening
// RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request.
// This is done to reduce number of NAK received with L1 enabled.
//
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
RwAlink (FCH_RCINDXP_REGA0 | PortId << 24, 0xFFFFFF0F, 0x10, StdHeader);
// Hard System Hang running MeatGrinder Test on multiple blocks
// GPP Error Reporting Configuration
RwAlink (FCH_RCINDXP_REG6A | PortId << 24, ~(BIT1), 0, StdHeader);
}
if (FchDataPtr->Misc.S3Resume) {
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
PortCfg = &FchDataPtr->Gpp.PortCfg[PortId];
if (PortCfg->PortHotPlug == TRUE) {
PortCfg->PortDetected = FALSE;
} else {
if (PortCfg->PortIsGen2 == 1) {
FchGppForceGen1 (FchDataPtr, (UINT8) (1 << PortId));
} else {
FchGppForceGen2 (FchDataPtr, (UINT8) (1 << PortId));
}
}
}
}
//
// Obtain original Gen2 strap value (LC_GEN2_EN_STRAP)
//
FchDataPtr->Gpp.GppGen2Strap = (UINT8) (ReadAlink (FCH_RCINDXP_REGA4 | 0 << 24, StdHeader) & BIT0);
}
/**
* CheckGppLinkStatus - loop polling the link status for each GPP port
*
*
* Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
UINT8
CheckGppLinkStatus (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT32 PortId;
UINT8 PortScanMap;
UINT8 GppHwDowngrade;
FCH_GPP_PORT_CONFIG *PortCfg;
UINT8 FailedPorts;
PortScanMap = 0;
FailedPorts = 0;
//
// Obtain a list of ports to be checked
//
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
PortCfg = &FchDataPtr->Gpp.PortCfg[PortId];
if ( PortCfg->PortPresent == TRUE && PortCfg->PortDetected == FALSE ) {
PortScanMap |= 1 << PortId;
}
}
GppHwDowngrade = (UINT8)FchDataPtr->Gpp.GppHardwareDownGrade;
if (GppHwDowngrade != 0) {
//
// Skip polling and always assume this port to be present
//
PortScanMap &= ~(1 << (GppHwDowngrade - 1));
}
//
//GPP Gen2 Speed Change
// if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) {
// PCIe_Cfg 0x88[3:0] = 0x2
// RCINDP_Reg 0xA2[13] = 0x0
// RCINDP_Reg 0xC0[15] = 0x0
// RCINDP_Reg 0xA4[29] = 0x1
// } else {
// PCIe_Cfg 0x88[3:0] = 0x1
// RCINDP_Reg 0xA4[0] = 0x0
// RCINDP_Reg 0xA2[13] = 0x1
// RCINDP_Reg 0xC0[15] = 0x0
// RCINDP_Reg 0xA4[29] = 0x1
// }
//
FchStall (5000, FchDataPtr->StdHeader);
if (FchDataPtr->Gpp.GppGen2 && FchDataPtr->Gpp.GppGen2Strap) {
FchGppForceGen2 (FchDataPtr, PortScanMap);
FailedPorts = GppPortPollingLtssm (FchDataPtr, PortScanMap, TRUE);
if (FailedPorts) {
FchGppForceGen1 (FchDataPtr, FailedPorts);
FailedPorts = GppPortPollingLtssm (FchDataPtr, FailedPorts, FALSE);
}
} else {
FchGppForceGen1 (FchDataPtr, PortScanMap);
FailedPorts = GppPortPollingLtssm (FchDataPtr, PortScanMap, FALSE);
}
return FailedPorts;
}
/**
* AfterGppLinkInit
* - Search for display device behind each GPP port
* - If the port is empty AND not hotplug-capable:
* * Turn off link training
* * (optional) Power down the port
* * Hide the configuration space (Turn off the port)
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
AfterGppLinkInit (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT32 PortId;
FCH_GPP_PORT_CONFIG *PortCfg;
UINT32 RegBusNumber;
UINT32 AbValue;
UINT32 AbIndex;
UINT8 Value;
UINT8 FchGppGen2;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = FchDataPtr->StdHeader;
FchGppGen2 = FchDataPtr->Gpp.GppGen2;
FchDataPtr->Gpp.GppFoundGfxDev = 0;
AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
//
// Link Bandwidth Notification Capability Enable
//RCINDC:0xC1[0] = 1
//
RwAlink (FCH_RCINDXC_REGC1, 0xFFFFFFFF, BIT0, StdHeader);
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
//
// Program requester ID for every port
//
AbIndex = FCH_RCINDXP_REG21 | (UINT32) (RCINDXP << 29) | (PortId << 24);
WriteAlink (AbIndex, (FCH_GPP_DEV << 3) + PortId, StdHeader);
//
// Link Bandwidth Notification Capability Enable
//PCIe Cfg 0x68[10] = 0
//PCIe Cfg 0x68[11] = 0
//
RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x68), AccessWidth16, ~(BIT10 + BIT11), 0, StdHeader);
PortCfg = &FchDataPtr->Gpp.PortCfg[PortId];
//
// Check if there is GFX device behind each GPP port
//
if ( PortCfg->PortDetected == TRUE ) {
RegBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8);
WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader);
ReadPci (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccessWidth8, &Value, StdHeader);
if ( Value == 3 ) {
FchDataPtr->Gpp.GppFoundGfxDev |= (1 << PortId);
}
RegBusNumber = 0;
WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x18), AccessWidth32, &RegBusNumber, StdHeader);
} else if ( PortCfg->PortPresent == FALSE || PortCfg->PortHotPlug == FALSE ) {
//
// Mask off non-applicable ports
//
AbValue &= ~(1 << (PortId + 4));
}
if ( PortCfg->PortHotPlug == TRUE ) {
//
// Hot Plug: PCIe Native Support
// RCINDP_Reg 0x10[3] = 0x1
// PCIe_Cfg 0x5A[8] = 0x1
// PCIe_Cfg 0x6C[6] = 0x1
// RCINDP_Reg 0x20[19] = 0x0
//
RwAlink ((FCH_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (PortId << 24)), 0xFFFFFFFF, BIT3, StdHeader);
RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x5b), AccessWidth8, 0xff, BIT0, StdHeader);
RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x6c), AccessWidth8, 0xff, BIT6, StdHeader);
RwAlink ((FCH_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (PortId << 24)), ~BIT19, 0, StdHeader);
}
}
if ( FchDataPtr->Gpp.GppUnhidePorts == FALSE ) {
if ((AbValue & 0xF0) == 0) {
AbValue = BIT8; /// if all ports are empty set GPP_RESET
} else if ((AbValue & 0xE0) != 0 && (AbValue & 0x10) == 0) {
AbValue |= BIT4; /// PortA should always be visible whenever other ports are exist
}
//
// Update GPP_Portx_Enable (abcfg:0xC0[7:5])
//
WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), AbValue, StdHeader);
}
//
// Common initialization for open GPP ports
//
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
ReadPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader);
if (Value != 0xff) {
//
// Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0])
//
Value &= 0xf0;
Value |= 0x06;
WritePci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x80), AccessWidth8, &Value, StdHeader);
//
// Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1
//
AbIndex = FCH_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (PortId << 24);
AbValue = ReadAlink (AbIndex, StdHeader) | BIT19;
WriteAlink (AbIndex, AbValue, StdHeader);
//
// Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0
//
AbIndex = FCH_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (PortId << 24);
AbValue = ReadAlink (AbIndex, StdHeader) & ~BIT19;
WriteAlink (AbIndex, AbValue, StdHeader);
}
}
}

159
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppHp.c
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@ -1,159 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch GPP controller
*
* Init GPP features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49456 $ @e \$Date: 2011-03-24 04:13:38 +0800 (Thu, 24 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_GPPHP_FILECODE
/**
* GPP hot plug handler
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] HpPort The hot plug port number.
*
*/
VOID
FchGppHotPlugSmiProcess (
IN AMD_FCH_CFG *FchDataPtr,
IN UINT32 HpPort
)
{
UINT8 FailedPort;
//
// First restore GPP pads if needed
//
if (FchDataPtr->Gpp->GppDynamicPowerSaving && FchDataPtr->Ab->AlinkPhyPllPowerDown && FchDataPtr->Gpp->GppPhyPllPowerDown) {
RwAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), 0, StdHeader);
RwAlink (RC_INDXC_REG65, ~(UINT32) (0x101 << HpPort), 0, StdHeader);
FchStall (1000);
}
FailedPort = (UINT8) (1 << HpPort);
if (FchDataPtr->Gpp->GppGen2 && FchDataPtr->Gpp->GppGen2Strap) {
if (GppPortPollingLtssm (FchDataPtr, FailedPort, TRUE)) {
FchGppForceGen1 (FchDataPtr, FailedPort);
FailedPort = GppPortPollingLtssm (FchDataPtr, FailedPort, FALSE);
}
} else {
FchGppForceGen1 (FchDataPtr, FailedPort);
FailedPort = GppPortPollingLtssm (FchDataPtr, FailedPort, FALSE);
}
}
/**
* GPP hot-unplug handler
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] HpPort The hot plug port number.
*
*/
VOID
FchGppHotUnplugSmiProcess (
IN AMD_FCH_CFG *FchDataPtr,
IN UINT32 HpPort
)
{
FchDataPtr->Gpp->PortCfg[HpPort].PortDetected = FALSE;
if (FchDataPtr->Gpp->GppGen2 && FchDataPtr->Gpp->GppGen2Strap) {
FchGppForceGen2 (FchDataPtr, (UINT8) (1 << HpPort));
}
if (FchDataPtr->Gpp->GppDynamicPowerSaving && FchDataPtr->Ab->AlinkPhyPllPowerDown && FchDataPtr->Gpp->GppPhyPllPowerDown) {
RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), BIT17, StdHeader);
RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT8), BIT8, StdHeader);
RwAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~(UINT32) (1 << (12 + HpPort)), (1 << (12 + HpPort)), StdHeader);
RwAlink (FCH_RCINDXP_REGA2 | HpPort << 24, ~(UINT32) (BIT17), 0, StdHeader);
}
//
// Finally re-configure GPP pads if needed
//
FchGppDynamicPowerSaving (FchDataPtr);
}
/**
* SMI handler for GPP hot-plug
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] IsPlugged Is a card currently plugged in the GPP port?
*
*/
VOID
FchGppHotplugSmiCallback (
IN AMD_FCH_CFG *FchDataPtr,
IN BOOLEAN IsPlugged
)
{
UINT32 PortNum;
UINT32 HpPort;
if (!FchDataPtr->Gpp->GppFunctionEnable) {
return;
}
HpPort = 0xff;
for (PortNum = 0; PortNum < MAX_GPP_PORTS; PortNum++) {
if (FchDataPtr->Gpp->PortCfg[PortNum].PortHotPlug == TRUE) {
HpPort = PortNum;
break;
}
}
if (HpPort == 0xff) {
return;
}
if (IsPlugged) {
OutPort80 (0x9C);
FchGppHotPlugSmiProcess (FchDataPtr, HpPort);
} else {
OutPort80 (0x9D);
FchGppHotUnplugSmiProcess (FchDataPtr, HpPort);
}
}

351
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLate.c
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@ -1,351 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Gpp controller
*
* Init Gpp Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49456 $ @e \$Date: 2011-03-24 04:13:38 +0800 (Thu, 24 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_GPPLATE_FILECODE
//
// Declaration of local functions
//
VOID FchGppSetAspm (IN UINT32 PciAddress, IN UINT8 LxState, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppSetEpAspm (IN UINT32 PciAddress, IN UINT8 LxState, IN AMD_CONFIG_PARAMS *StdHeader);
VOID FchGppValidateAspm (IN UINT32 PciAddress, IN UINT8 *LxState, IN AMD_CONFIG_PARAMS *StdHeader);
UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader);
//
//-----------------------------------------------------------------------------------
// GPP initialization sequence:
//
// 1) Set port enable bit fields by current GPP link configuration mode
// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)
// 3) Loop polling for the link status of all ports
// 4) Misc operations after link training:
// - (optional) Detect GFX device
// - Hide empty GPP configuration spaces (Disable empty GPP ports)
// - (optional) Power down unused GPP ports
// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])
// 5) GPP init completed
//
//
// *) Gen2 vs Gen1
// Gen2 mode Gen1 mode
// ---------------------------------------------------------------
// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19
// STRAP_BIF_GEN2_EN 1 0
//
// PCIE_PHY_PLL clock locks @ 5GHz
//
//
/**
* FchInitLateGpp - Prepare Gpp controller to boot to OS.
*
* PcieGppLateInit
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateGpp (
IN VOID *FchDataPtr
)
{
UINT8 PortId;
UINT8 BusNum;
UINT8 AspmValue;
UINT8 PortAspmValue;
UINT8 AllowStrapControlByAB;
UINT8 FchGppPhyPllPowerDown;
FCH_GPP_PORT_CONFIG *PortCfg;
UINT32 PciAspmValue;
UINT32 AbValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Disable hidden register decode and serial number capability
//
AbValue = ReadAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), StdHeader);
WriteAlink (FCH_ABCFG_REG330 | (UINT32) (ABCFG << 29), AbValue & ~(BIT26 + BIT10), StdHeader);
if (ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader) & BIT8) {
return;
}
//
// Configure ASPM
//
AspmValue = (UINT8)LocalCfgPtr->Gpp.GppPortAspm;
FchGppPhyPllPowerDown = (UINT8) LocalCfgPtr->Gpp.GppPhyPllPowerDown;
AllowStrapControlByAB = 0x01;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
//
// write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under some OS
// when native PCIE is enabled but MSI is not available
// BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg
//
PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId];
if (PortCfg->PortHotPlug) {
RwPci (PCI_ADDRESS (0, 21, PortId, 0x04), AccessWidth8, 0xFE, 0x00, StdHeader); ///clear IO enable to fix possible hotplug hang
}
WritePci (PCI_ADDRESS (0, 21, PortId, 0x3d), AccessWidth8, &AllowStrapControlByAB, StdHeader);
ReadPci (PCI_ADDRESS (0, 21, PortId, 0x19), AccessWidth8, &BusNum, StdHeader);
if (BusNum != 0xFF) {
ReadPci (PCI_ADDRESS (BusNum, 0, 0, 0x00), AccessWidth32, &PciAspmValue, StdHeader);
if (PciAspmValue != 0xffffffff) {
PortAspmValue = AspmValue;
//
// Validate ASPM support on EP side
//
FchGppValidateAspm (PCI_ADDRESS (BusNum, 0, 0, 0), &PortAspmValue, StdHeader);
//
// Set ASPM on EP side
//
FchGppSetEpAspm (PCI_ADDRESS (BusNum, 0, 0, 0), PortAspmValue, StdHeader);
//
// Set ASPM on port side
//
FchGppSetAspm (PCI_ADDRESS (0, 21, PortId, 0), PortAspmValue, StdHeader);
}
}
RwAlink ((FCH_RCINDXP_REG02 | (UINT32) (RCINDXP << 29) | (PortId << 24) ), ~(BIT15), (BIT15), StdHeader);
}
RwAlink ((FCH_RCINDXC_REG02 | (UINT32) (RCINDXC << 29)), ~(BIT0), (BIT0), StdHeader);
//
// Configure Lock HWInit registers
//
AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
if (AbValue & 0xF0) {
AbValue = ReadAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), StdHeader);
WriteAlink (FCH_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), AbValue | BIT0, StdHeader); /// Set HWINIT_WR_LOCK
if ( FchGppPhyPllPowerDown == TRUE ) {
//
// Power Saving Feature for GPP Lanes
//
// Set PCIE_P_CNTL in Alink PCIEIND space
//
AbValue = ReadAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), StdHeader);
AbValue |= BIT12 + BIT3 + BIT0;
AbValue &= ~(BIT9 + BIT4);
WriteAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), AbValue, StdHeader);
RwAlink (FCH_RCINDXC_REG02, ~(BIT8), (BIT8), StdHeader);
RwAlink (FCH_RCINDXC_REG02, ~(BIT3), (BIT3), StdHeader);
}
}
//
// Restore strap0 via override
//
if (LocalCfgPtr->Gpp.PcieAer) {
RwAlink (FCH_ABCFG_REG310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader);
RwAlink (RC_INDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader);
}
}
/**
* FchGppSetAspm - Set GPP ASPM
*
*
* @param[in] PciAddress PCI Address.
* @param[in] LxState Lane State.
* @param[in] StdHeader
*
*/
VOID
FchGppSetAspm (
IN UINT32 PciAddress,
IN UINT8 LxState,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapOffset;
UINT8 DeviceType;
PcieCapOffset = FchFindPciCap (PciAddress, PCIE_CAP_ID, StdHeader);
if (PcieCapOffset) {
//
// Read link capabilities register (0x0C[11:10] - ASPM support)
//
ReadPci (PciAddress + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
if (DeviceType & BIT2) {
DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
//
// Set ASPM state in link control register
//
RwPci (PciAddress + PcieCapOffset + 0x10, AccessWidth8, 0xffffffff, LxState & DeviceType, StdHeader);
}
}
}
/**
* FchGppSetEpAspm - Set EP ASPM
*
*
* @param[in] PciAddress PCI Address.
* @param[in] LxState Lane State.
* @param[in] StdHeader
*
*/
VOID
FchGppSetEpAspm (
IN UINT32 PciAddress,
IN UINT8 LxState,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 DeviceType;
UINT8 MaxFuncs;
UINT32 DevBDF;
MaxFuncs = 1;
ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader);
if (DeviceType & BIT7) {
MaxFuncs = 8; /// multi-function device
}
while (MaxFuncs != 0) {
DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16);
FchGppSetAspm (DevBDF, LxState, StdHeader);
MaxFuncs--;
}
}
/**
* FchGppValidateAspm - Validate EndPoint support for GPP ASPM
*
*
* @param[in] PciAddress PCI Address.
* @param[in] LxState Lane State.
* @param[in] StdHeader
*
*/
VOID
FchGppValidateAspm (
IN UINT32 PciAddress,
IN UINT8 *LxState,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 PcieCapOffset;
UINT8 DeviceType;
UINT8 MaxFuncs;
UINT32 DevBDF;
MaxFuncs = 1;
ReadPci (PciAddress + 0x0E, AccessWidth8, &DeviceType, StdHeader);
if (DeviceType & BIT7) {
MaxFuncs = 8; /// multi-function device
}
while (MaxFuncs != 0) {
DevBDF = PciAddress + (UINT32) ((MaxFuncs - 1) << 16);
PcieCapOffset = FchFindPciCap (DevBDF, PCIE_CAP_ID, StdHeader);
if (PcieCapOffset) {
//
// Read link capabilities register (0x0C[11:10] - ASPM support)
//
ReadPci (DevBDF + PcieCapOffset + 0x0D, AccessWidth8, &DeviceType, StdHeader);
if (DeviceType & BIT2) {
DeviceType = (DeviceType >> 2) & (BIT1 + BIT0);
//
// Update ASPM state as what endpoint support
//
*LxState &= DeviceType;
}
}
MaxFuncs--;
}
}
/**
* FchFindPciCap - Find PCI Cap
*
*
* @param[in] PciAddress PCI Address.
* @param[in] TargetCapId Target Cap ID.
* @param[in] StdHeader
*
*/
UINT8
FchFindPciCap (
IN UINT32 PciAddress,
IN UINT8 TargetCapId,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NextCapPtr;
UINT8 CapId;
NextCapPtr = 0x34;
while (NextCapPtr != 0) {
ReadPci (PciAddress + NextCapPtr, AccessWidth8, &NextCapPtr, StdHeader);
if (NextCapPtr == 0xff) {
return 0;
}
if (NextCapPtr != 0) {
ReadPci (PciAddress + NextCapPtr, AccessWidth8, &CapId, StdHeader);
if (CapId == TargetCapId) {
break;
} else {
NextCapPtr++;
}
}
}
return NextCapPtr;
}

193
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppLib.c
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@ -1,193 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Fch Gpp Library
*
* Gpp Library
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44909 $ @e \$Date: 2011-01-10 18:45:45 +0800 (Mon, 10 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#include "FchDef.h"
#define FILECODE PROC_FCH_PCIE_GPPLIB_FILECODE
/**
* FchGppForceGen2 - Set GPP to Gen2
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] ActivePorts Activate Ports.
*
*/
VOID
FchGppForceGen2 (
IN VOID *FchDataPtr,
IN CONST UINT8 ActivePorts
)
{
UINT32 PortId;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
if (ActivePorts & (1 << PortId)) {
RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, 0xFFFFFFFF, BIT29 + BIT0, StdHeader);
RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT21, StdHeader);
RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, ~BIT13, 0, StdHeader);
RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, ~BIT15, 0, StdHeader);
RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x02, StdHeader);
(&LocalCfgPtr->Gpp.PortCfg[PortId])->PortIsGen2 = 2;
}
}
}
/**
* FchGppForceGen1 - Set GPP to Gen1
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] ActivePorts Activate Ports.
*
*/
VOID
FchGppForceGen1 (
IN VOID *FchDataPtr,
IN CONST UINT8 ActivePorts
)
{
UINT32 PortId;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
if (ActivePorts & (1 << PortId) && LocalCfgPtr->Gpp.GppHardwareDownGrade != PortId + 1) {
RwAlink ((FCH_ABCFG_REG340 + PortId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0, StdHeader);
RwAlink (FCH_RCINDXP_REGA4 | PortId << 24, ~BIT0, BIT29, StdHeader);
RwAlink (FCH_RCINDXP_REGA2 | PortId << 24, 0xFFFFFFFF, BIT13, StdHeader);
RwAlink (FCH_RCINDXP_REGC0 | PortId << 24, ~BIT15, 0, StdHeader);
RwPci (PCI_ADDRESS (0, GPP_DEV_NUM, PortId, 0x88), AccessWidth8, 0xf0, 0x01, StdHeader);
(&LocalCfgPtr->Gpp.PortCfg[PortId])->PortIsGen2 = 1;
}
}
}
/**
* GppPortPollingLtssm - Loop polling the LTSSM for each GPP port marked in PortMap
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] ActivePorts A bitmap of ports which should be polled
* @param[in] IsGen2 TRUE if the polling is in Gen2 mode
*
* @retval FailedPorts A bitmap of ports which failed to train
*
*/
UINT8
GppPortPollingLtssm (
IN VOID *FchDataPtr,
IN UINT8 ActivePorts,
IN BOOLEAN IsGen2
)
{
UINT32 RetryCounter;
UINT8 PortId;
UINT8 FailedPorts;
FCH_GPP_PORT_CONFIG *PortCfg;
UINT32 AbIndex;
UINT32 GppData32;
UINT8 EmptyPorts;
UINT8 Index;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FailedPorts = 0;
RetryCounter = MAX_LT_POLLINGS;
EmptyPorts = ActivePorts;
while (RetryCounter-- && ActivePorts) {
for (PortId = 0; PortId < MAX_GPP_PORTS; PortId++) {
if (ActivePorts & (1 << PortId)) {
PortCfg = &LocalCfgPtr->Gpp.PortCfg[PortId];
AbIndex = FCH_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (PortId << 24);
GppData32 = ReadAlink (AbIndex, StdHeader) & 0x3F3F3F3F;
if ((UINT8) (GppData32) > 0x04) {
EmptyPorts &= ~(1 << PortId);
}
if ((UINT8) (GppData32) == 0x10) {
ActivePorts &= ~(1 << PortId);
PortCfg->PortDetected = TRUE;
break;
}
if (IsGen2) {
for (Index = 0; Index < 4; Index++) {
if ((UINT8) (GppData32) == 0x29 || (UINT8) (GppData32) == 0x2A ) {
ActivePorts &= ~(1 << PortId);
FailedPorts |= (1 << PortId);
break;
}
GppData32 >>= 8;
}
}
}
}
if (EmptyPorts && RetryCounter < (MAX_LT_POLLINGS - 200)) {
ActivePorts &= ~EmptyPorts;
}
FchStall (1000, StdHeader);
}
FailedPorts |= ActivePorts;
return FailedPorts;
}

64
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/GppMid.c
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@ -1,64 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Gpp controller
*
* Init Gpp Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_GPPMID_FILECODE
//
// Declaration of local functions
//
/**
* FchInitMidGpp - Config Gpp controller after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidGpp (
IN VOID *FchDataPtr
)
{
}

65
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@ -1,65 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Gpp controller
*
* Init Gpp features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#include "FchDef.h"
#define FILECODE PROC_FCH_PCIE_GPPRESET_FILECODE
/**
* FchInitResetGpp - Config Gpp during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetGpp (
IN VOID *FchDataPtr
)
{
ProgramFchGppInitReset (FchDataPtr);
}

67
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@ -1,67 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcie controller
*
* Init Pcie Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#include "FchDef.h"
#define FILECODE PROC_FCH_PCIE_PCIEENV_FILECODE
/**
* FchInitEnvPcie - Config Pcie before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvPcie (
IN VOID *FchDataPtr
)
{
//
// PCIE Native setting
//
ProgramPcieNativeMode (FchDataPtr);
}

61
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieLate.c
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@ -1,61 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcie controller
*
* Init Pcie Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_PCIELATE_FILECODE
/**
* FchInitLatePcie - Prepare Pcie to boot to OS.
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLatePcie (
IN VOID *FchDataPtr
)
{
}

61
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieMid.c
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@ -1,61 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcie controller
*
* Init Pcie Controller features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_PCIEMID_FILECODE
/**
* FchInitMidPcie - Config Pcie after PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidPcie (
IN VOID *FchDataPtr
)
{
}

63
src/vendorcode/amd/agesa/f12/Proc/Fch/Pcie/PcieReset.c
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@ -1,63 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Pcie Component
*
* Init Pcie features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 45603 $ @e \$Date: 2011-01-19 14:29:05 +0800 (Wed, 19 Jan 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_PCIE_PCIERESET_FILECODE
/**
* FchInitResetPcie - Config Pcie controller during Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetPcie (
IN VOID *FchDataPtr
)
{
}

86
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciEnv.c
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@ -1,86 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch SATA controller (AHCI mode)
*
* Init SATA AHCI features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_AHCIENV_FILECODE
/**
* FchInitEnvSataAhci - Config SATA Ahci controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataAhci (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Class code
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01060140, StdHeader);
//
// Device ID
//
if ( LocalCfgPtr->Sata.SataClass == SataAhci7804 ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader);
}
//
// SSID
//
if (LocalCfgPtr->Sata.SataAhciSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader);
}
}

61
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@ -1,61 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch SATA controller (AHCI mode)
*
* Init SATA AHCI features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_AHCILATE_FILECODE
/**
* FchInitLateSataAhci - Prepare SATA AHCI controller to boot to
* OS.
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateSataAhci (
IN VOID *FchDataPtr
)
{
}

68
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciLib.c
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@ -1,68 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Fch SATA AHCI controller Library
*
* SATA AHCI Library
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_AHCILIB_FILECODE
/**
* sataAhciSetDeviceNumMsi - Program AHCI controller support
* device number cap & MSI cap
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SataAhciSetDeviceNumMsi (
IN VOID *FchDataPtr
)
{
FCH_INTERFACE *LocalCfgPtr;
LocalCfgPtr = (FCH_INTERFACE *)FchDataPtr;
SataSetDeviceNumMsi (LocalCfgPtr);
}

70
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/AhciMid.c
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@ -1,70 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch SATA controller (AHCI mode)
*
* Init SATA AHCI features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_AHCIMID_FILECODE
/**
* FchInitMidSataAhci - Config SATA Ahci controller after PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidSataAhci (
IN VOID *FchDataPtr
)
{
UINT32 Bar5;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
SataAhciSetDeviceNumMsi (LocalCfgPtr);
SataBar5setting (LocalCfgPtr, &Bar5);
ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
}

218
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
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@ -1,218 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Graphics Controller family specific service procedure
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 49766 $ @e \$Date: 2011-03-29 06:18:48 +0800 (Tue, 29 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
//
// Local Routine
//
VOID FchSataCombineControlDataByte (IN UINT8 *ControlReg);
VOID FchSataCombineControlDataWord (IN UINT16 *ControlReg);
SATA_PHY_SETTING SataPhyTable[] =
{
//Gen3
0x0030, 0x0057A607,
0x0031, 0x0057A607,
0x0032, 0x0057A407,
0x0033, 0x0057A407,
0x0034, 0x0057A607,
0x0035, 0x0057A607,
0x0036, 0x0057A403,
0x0037, 0x0057A403,
//Gen2
0x0120, 0x00071302,
//Gen1
0x0110, 0x00174101
};
/**
* FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space
* register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvProgramSataPciRegs (
IN VOID *FchDataPtr
)
{
UINT8 *PortRegByte;
UINT16 *PortRegWord;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Caculate SataPortReg for SATA_ESP_PORT
//
PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode);
FchSataCombineControlDataWord (PortRegWord);
PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg);
FchSataCombineControlDataByte (PortRegByte);
//
// Set Sata PCI Configuration Space Write enable
//
SataEnableWriteAccess (StdHeader);
//
// Enables the SATA watchdog timer register prior to the SATA BIOS post
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44), AccessWidth8, 0xff, BIT0, StdHeader);
//
// SATA PCI Watchdog timer setting
// Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG44 + 2), AccessWidth8, 0, 0x20, StdHeader);
//
// BIT4:disable fast boot
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40), AccessWidth8, 0xff, BIT4, StdHeader);
//
// Enable IDE DMA read enhancement
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48 + 3), AccessWidth8, 0xff, BIT7, StdHeader);
//
// Unused SATA Ports Disabled
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG4C), AccessWidth32, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
}
/**
* FchSataCombineControlDataByte - Combine port control options
* to one control byte.
*
*
* @param[in] *ControlReg - Data pointer for control byte.
*
*/
VOID
FchSataCombineControlDataByte (
IN UINT8 *ControlReg
)
{
UINT8 Index;
UINT8 PortControl;
*ControlReg = 0;
for ( Index = 0; Index < 8; Index++ ) {
PortControl = *( ControlReg + 1 + Index );
*ControlReg |= PortControl << Index;
}
}
/**
* FchSataCombineControlDataWord - Combine port control options
* to one control Word.
*
*
* @param[in] *ControlReg - Data pointer for control byte.
*
*/
VOID
FchSataCombineControlDataWord (
IN UINT16 *ControlReg
)
{
UINT8 Index;
UINT8 PortControl;
*ControlReg = 0;
for ( Index = 0; Index < 8; Index++ ) {
PortControl = *( (UINT8 *)ControlReg + 2 + Index );
*ControlReg |= PortControl << (Index * 2);
}
}
VOID
FchProgramSataPhy (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
SATA_PHY_SETTING *PhyTablePtr;
UINT16 Index;
PhyTablePtr = &SataPhyTable[0];
for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
++PhyTablePtr;
}
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x110, StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG9C, AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80, AccessWidth16, 0x00, 0x10, StdHeader);
}

131
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataResetService.c
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@ -1,131 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch Sata controller
*
* Init Sata Controller features (PEI phase).
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE
/**
* FchInitResetSataProgram - Config Sata controller during
* Power-On
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitResetSataProgram (
IN VOID *FchDataPtr
)
{
UINT8 SataPortNum;
UINT8 PortStatusByte;
UINT8 EfuseByte;
UINT8 FchSataMode;
UINT8 FchSataInternal100Spread;
FCH_RESET_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//FchSataMode = LocalCfgPtr->Sata.SATA_MODE.SataMode.SataModeReg;
//New structure need calculate Sata Register value
//
FchSataMode = 0;
if ( LocalCfgPtr->FchReset->SataEnable ) FchSataMode |= 0x01;
if ( LocalCfgPtr->Sata6AhciCap ) FchSataMode |= 0x02;
if ( LocalCfgPtr->SataSetMaxGen2 ) FchSataMode |= 0x04;
if ( LocalCfgPtr->FchReset->IdeEnable ) FchSataMode |= 0x08;
FchSataMode |= (( LocalCfgPtr->SataClkMode ) << 4 ) ;
LocalCfgPtr->SataModeReg = FchSataMode; ///Save Back to Structure
FchSataInternal100Spread = ( UINT8 ) LocalCfgPtr->SataInternal100Spread;
SataPortNum = 0;
//
// Sata Workaround
//
for ( SataPortNum = 0; SataPortNum < 0x08; SataPortNum++ ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0xFF, 1 << SataPortNum, StdHeader);
FchStall (2, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, (0xFF ^ (1 << SataPortNum)) , 0x00, StdHeader);
FchStall (2, StdHeader);
}
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84 + 3), AccessWidth8, ~BIT2, 0, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA0), AccessWidth8, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5, StdHeader);
//
// Sata Setting for clock mode only
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0, FchSataMode);
if ( FchSataInternal100Spread ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, 0xFF, BIT4);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFB, 0x00, StdHeader);
} else {
RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccessWidth8, ~BIT4, 0x00);
}
EfuseByte = SATA_FIS_BASE_EFUSE_LOC;
GetEfuseStatus (&EfuseByte, StdHeader);
if (EfuseByte & BIT0) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, 0xFB, 0x04);
}
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth8, &PortStatusByte);
if ( ((PortStatusByte & 0xF0) == 0x10) ) {
RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_PMIOA_REG08, AccessWidth8, 0, BIT5);
}
if ( FchSataInternal100Spread ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, 0xFFFFFFFF, 0x04, StdHeader);
}
}

681
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Family/Hudson2/Hudson2SataService.c
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@ -1,681 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Graphics Controller family specific service procedure
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 48230 $ @e \$Date: 2011-03-05 06:55:12 +0800 (Sat, 05 Mar 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
UINT8 NumOfSataPorts = 8;
/**
* FchSataGpioInitial - Sata GPIO function Procedure
*
* - Private function
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchSataGpioInitial (
IN VOID *FchDataPtr
)
{
UINT32 Bar5;
UINT32 FchSataBarRegDword;
UINT32 EMb;
UINT32 SataGpioVariableDword;
UINT8 FchSataSgpio0;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
Bar5 = 0;
EMb = 0;
FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0;
SataBar5setting (LocalCfgPtr, &Bar5);
ReadMem (Bar5 + FCH_SATA_BAR5_REG1C , AccessWidth32, &FchSataBarRegDword);
EMb = (Bar5 + (( FchSataBarRegDword & 0xFFFF0000) >> 14));
if ( EMb ) {
SataGpioVariableDword = 0x03040C00;
WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword);
SataGpioVariableDword = 0x00C08240;
WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword);
SataGpioVariableDword = 0x00000001;
WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword);
if ( FchSataSgpio0 ) {
SataGpioVariableDword = 0x00000060;
} else {
SataGpioVariableDword = 0x00000061;
}
WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
RwMem ((Bar5 + FCH_SATA_BAR5_REG20), AccessWidth16, ~(BIT8), BIT8);
do {
ReadMem (Bar5 + FCH_SATA_BAR5_REG20 , AccessWidth32, &FchSataBarRegDword);
FchSataBarRegDword = FchSataBarRegDword & BIT8;
} while ( FchSataBarRegDword != 0 );
SataGpioVariableDword = 0x03040F00;
WriteMem ( Bar5 + EMb, AccessWidth32, &SataGpioVariableDword);
SataGpioVariableDword = 0x00008240;
WriteMem ( Bar5 + EMb + 4, AccessWidth32, &SataGpioVariableDword);
SataGpioVariableDword = 0x00000002;
WriteMem ( Bar5 + EMb + 8, AccessWidth32, &SataGpioVariableDword);
SataGpioVariableDword = 0x00800000;
WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
SataGpioVariableDword = 0x0F003700;
WriteMem ( Bar5 + EMb + 0x0C, AccessWidth32, &SataGpioVariableDword);
RwMem ((Bar5 + FCH_SATA_BAR5_REG20), AccessWidth16, ~(BIT8), BIT8);
do {
ReadMem (Bar5 + FCH_SATA_BAR5_REG20 , AccessWidth32, &FchSataBarRegDword);
FchSataBarRegDword = FchSataBarRegDword & BIT8;
} while ( FchSataBarRegDword != 0 );
}
}
/**
* FchInitMidProgramSataRegs - Sata Pci Configuration Space
* register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitMidProgramSataRegs (
IN VOID *FchDataPtr
)
{
UINT8 FchSataMsiCapability;
UINT8 FchSataTargetSupport8Device;
UINT8 FchSataDisableGenericMode;
UINT8 FchSataSgpio0;
UINT8 FchSataSgpio1;
UINT8 FchSataPhyPllShutDown;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchSataMsiCapability = (UINT8) LocalCfgPtr->Sata.SataMsiCapability;
FchSataTargetSupport8Device = (UINT8) LocalCfgPtr->Sata.SataTargetSupport8Device;
FchSataDisableGenericMode = (UINT8) LocalCfgPtr->Sata.SataDisableGenericMode;
FchSataSgpio0 = (UINT8) LocalCfgPtr->Sata.SataSgpio0;
FchSataSgpio1 = (UINT8) LocalCfgPtr->Sata.SataSgpio1;
FchSataPhyPllShutDown = (UINT8) LocalCfgPtr->Sata.SataPhyPllShutDown;
//
// Enabled SATA MSI capability
// SATA MSI and D3 Power State Capability
//
if ( FchSataMsiCapability ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG34), AccessWidth8, 0, 0x50, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG34), AccessWidth8, 0, 0x70, StdHeader);
}
//
// Disable SATA FLR Capability
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG70), AccessWidth16, 0x00FF, 0x00, StdHeader);
//
// Sata Target Support 8 devices function
//
if ( FchSataTargetSupport8Device ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT12, BIT12);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT12, 0x00);
}
//
// Sata Generic Mode setting
//
if ( FchSataDisableGenericMode ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT13, BIT13);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGDA, AccessWidth16, ~BIT13, 0x00);
}
//
// Sata GPIO Initial
//
if ( FchSataSgpio0 ) {
FchSataGpioInitial ( LocalCfgPtr );
}
if ( FchSataSgpio1 ) {
FchSataGpioInitial ( LocalCfgPtr );
}
//
// Sata Phy Pll Shutdown setting
//
if ( FchSataPhyPllShutDown ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, ~(BIT6), BIT6, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x87), AccessWidth8, ~(BIT6), 0x00, StdHeader);
}
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG4C), AccessWidth32, (UINT32) (~ (0x3f << 26)), (UINT32) (0x3f << 26), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG84), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader);
}
/**
* FchInitLateProgramSataRegs - Sata Pci Configuration Space
* register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateProgramSataRegs (
IN VOID *FchDataPtr
)
{
UINT8 PortNumByte;
UINT32 Bar5;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
SataBar5setting (LocalCfgPtr, &Bar5);
//
//Clear error status
//
RwMem ((Bar5 + FCH_SATA_BAR5_REG130), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
RwMem ((Bar5 + FCH_SATA_BAR5_REG1B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
RwMem ((Bar5 + FCH_SATA_BAR5_REG230), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
RwMem ((Bar5 + FCH_SATA_BAR5_REG2B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
RwMem ((Bar5 + FCH_SATA_BAR5_REG330), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
RwMem ((Bar5 + FCH_SATA_BAR5_REG3B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
RwMem ((Bar5 + FCH_SATA_BAR5_REG430), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
RwMem ((Bar5 + FCH_SATA_BAR5_REG4B0), AccessWidth32, 0xFFFFFFFF, 0xFFFFFFFF);
for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) {
RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00);
}
}
/**
* sataBar5RegSet - Sata Bar5 register setting
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SataBar5RegSet (
IN VOID *FchDataPtr
)
{
UINT32 AndMaskDword;
UINT32 OrMaskDword;
UINT32 Bar5;
UINT8 EfuseByte;
UINT8 FchSataAggrLinkPmCap;
UINT8 FchSataPortMultCap;
UINT8 FchSataPscCap;
UINT8 FchSataSscCap;
UINT8 FchSataFisBasedSwitching;
UINT8 FchSataCccSupport;
UINT8 FchSataAhciEnclosureManagement;
FCH_DATA_BLOCK *LocalCfgPtr;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
FchSataAggrLinkPmCap = (UINT8) LocalCfgPtr->Sata.SataAggrLinkPmCap;
FchSataPortMultCap = (UINT8) LocalCfgPtr->Sata.SataPortMultCap;
FchSataPscCap = (UINT8) LocalCfgPtr->Sata.SataPscCap;
FchSataSscCap = (UINT8) LocalCfgPtr->Sata.SataSscCap;
FchSataFisBasedSwitching = (UINT8) LocalCfgPtr->Sata.SataFisBasedSwitching;
FchSataCccSupport = (UINT8) LocalCfgPtr->Sata.SataCccSupport;
FchSataAhciEnclosureManagement = (UINT8) LocalCfgPtr->Sata.SataAhciEnclosureManagement;
AndMaskDword = 0;
OrMaskDword = 0;
Bar5 = 0;
SataBar5setting (LocalCfgPtr, &Bar5);
EfuseByte = SATA_FIS_BASE_EFUSE_LOC;
GetEfuseStatus (&EfuseByte, LocalCfgPtr->StdHeader);
if ( !FchSataPortMultCap ) {
AndMaskDword |= BIT12;
}
if ( FchSataAggrLinkPmCap ) {
OrMaskDword |= BIT11;
} else {
AndMaskDword |= BIT11;
}
if ( FchSataPscCap ) {
OrMaskDword |= BIT1;
} else {
AndMaskDword |= BIT1;
}
if ( FchSataSscCap ) {
OrMaskDword |= BIT26;
} else {
AndMaskDword |= BIT26;
}
if ( FchSataFisBasedSwitching ) {
if (EfuseByte & BIT1) {
AndMaskDword |= BIT10;
} else {
OrMaskDword |= BIT10;
}
} else {
AndMaskDword |= BIT10;
}
//
// Disabling CCC (Command Completion Coalescing) support.
//
if ( FchSataCccSupport ) {
OrMaskDword |= BIT19;
} else {
AndMaskDword |= BIT19;
}
if ( FchSataAhciEnclosureManagement ) {
OrMaskDword |= BIT27;
} else {
AndMaskDword |= BIT27;
}
RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth32, ~AndMaskDword, OrMaskDword);
//
// SATA ESP port setting
// These config bits are set for SATA driver to identify which ports are external SATA ports and need to
// support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
// not enable power management (HIPM & DIPM) for these ports.
//
if ( LocalCfgPtr->Sata.SataEspPort.SataPortReg != 0 ) {
RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, ~(LocalCfgPtr->Sata.SataEspPort.SataPortReg), 0);
RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0xFF00FF00, (LocalCfgPtr->Sata.SataEspPort.SataPortReg << 16));
//
// External SATA Port Indication Registers
// If any of the ports was programmed as an external port, HCAP.SXS should also be set
//
RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth32, ~(BIT20), BIT20);
} else {
//
// External SATA Port Indication Registers
// If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)
//
RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0xFF00FF00, 0x00);
RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth32, ~(BIT20), 0x00);
}
if ( FchSataFisBasedSwitching ) {
if (EfuseByte & BIT1) {
RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0x00FFFFFF, 0x00);
} else {
RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0x00FFFFFF, 0xFF000000);
}
} else {
RwMem ((Bar5 + FCH_SATA_BAR5_REGF8), AccessWidth32, 0x00FFFFFF, 0x00);
}
if ( LocalCfgPtr->Sata.BiosOsHandOff == 1 ) {
RwMem ((Bar5 + FCH_SATA_BAR5_REG24), AccessWidth8, ~BIT0, BIT0);
} else {
RwMem ((Bar5 + FCH_SATA_BAR5_REG24), AccessWidth8, ~BIT0, 0x00);
}
}
/**
* FchSataSetDeviceNumMsi - Program Sata controller support
* device number cap & MSI cap
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchSataSetDeviceNumMsi (
IN VOID *FchDataPtr
)
{
UINT32 Bar5;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
Bar5 = 0;
SataBar5setting (LocalCfgPtr, &Bar5);
//
// RAID or AHCI
//
if (LocalCfgPtr->Sata.SataMode.IdeEnable == DISABLED) {
//
// IDE2 Controller is enabled
//
if (LocalCfgPtr->Sata.SataMode.Sata6AhciCap == ENABLED) {
//
// 6 AHCI mode
//
RwMem ((Bar5 + FCH_SATA_BAR5_REG0C), AccessWidth8, 0x00, 0x3F);
RwMem ((Bar5 + FCH_SATA_BAR5_REG00), AccessWidth8, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth8, 0x07, 0x30);
} else {
RwMem ((Bar5 + FCH_SATA_BAR5_REG0C), AccessWidth8, 0x00, 0x0F);
if ( LocalCfgPtr->Sata.SataCccSupport ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth8, 0x07, 0x20);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2, StdHeader);
}
}
} else {
//
// IDE2 Controller is disabled
//
RwMem ((Bar5 + FCH_SATA_BAR5_REG00), AccessWidth8, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT1 + BIT0);
RwMem ((Bar5 + FCH_SATA_BAR5_REG0C), AccessWidth8, 0x00, 0xFF);
if ( LocalCfgPtr->Sata.SataCccSupport ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT3, StdHeader);
RwMem ((Bar5 + FCH_SATA_BAR5_REGFC), AccessWidth8, 0x07, 0x40);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG50 + 2), AccessWidth8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1, StdHeader);
}
}
}
/**
* FchSataDriveDetection - Sata drive detection
*
* - Sata Ide & Sata Ide to Ahci only
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] *Bar5Ptr Sata BAR5 base address.
*
*/
VOID
FchSataDriveDetection (
IN VOID *FchDataPtr,
IN UINT32 *Bar5Ptr
)
{
UINT32 SataBarInfo;
UINT8 PortNumByte;
UINT8 SataPortType;
UINT16 IoBaseWord;
UINT16 SataLoopVarWord;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
for ( PortNumByte = 0; PortNumByte < 4; PortNumByte++ ) {
ReadMem (*Bar5Ptr + FCH_SATA_BAR5_REG128 + PortNumByte * 0x80, AccessWidth32, &SataBarInfo);
if ( ( SataBarInfo & 0x0F ) == 0x03 ) {
if ( PortNumByte & BIT0 ) {
//
//this port belongs to secondary channel
//
ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG18), AccessWidth16, &IoBaseWord, StdHeader);
} else {
//
//this port belongs to primary channel
//
ReadPci (((UINT32) (SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG10), AccessWidth16, &IoBaseWord, StdHeader);
}
//
//if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
//
if ( LocalCfgPtr->Sata.SataClass == SataLegacyIde ) {
IoBaseWord = ( (0x170) | ((UINT16) ( (~((UINT8) (PortNumByte & BIT0) << 7)) & 0x80 )) );
}
if ( PortNumByte & BIT1 ) {
//
//this port is slave
//
SataPortType = 0xB0;
} else {
//
//this port is master
//
SataPortType = 0xA0;
}
IoBaseWord &= 0xFFF8;
LibAmdIoWrite (AccessWidth8, IoBaseWord + 6, &SataPortType, StdHeader);
//
//Wait in loop for 30s for the drive to become ready
//
for ( SataLoopVarWord = 0; SataLoopVarWord < 300000; SataLoopVarWord++ ) {
LibAmdIoRead (AccessWidth8, IoBaseWord + 7, &SataPortType, StdHeader);
if ( (SataPortType & 0x88) == 0 ) {
break;
}
FchStall (100, StdHeader);
}
}
}
}
/**
* FchShutdownUnconnectedSataPortClock - Shutdown unconnected
* Sata port clock
*
* - Sata Ide & Sata Ide to Ahci only
*
* @param[in] FchDataPtr Fch configuration structure pointer.
* @param[in] Bar5 Sata BAR5 base address.
*
*/
VOID
FchShutdownUnconnectedSataPortClock (
IN VOID *FchDataPtr,
IN UINT32 Bar5
)
{
UINT8 PortNumByte;
UINT8 PortSataStatusByte;
UINT8 NumOfPorts;
UINT8 FchSataClkAutoOff;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchSataClkAutoOff = (UINT8) LocalCfgPtr->Sata.SataClkAutoOff;
NumOfPorts = 0;
//
// Enable SATA auto clock control by default
//
for ( PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte++ ) {
ReadMem (Bar5 + FCH_SATA_BAR5_REG128 + (PortNumByte * 0x80), AccessWidth8, &PortSataStatusByte);
//
// Shutdown the clock for the port and do the necessary port reporting changes.
// Error port status should be 1 not 3
//
if ( ((PortSataStatusByte & 0x0F) != 0x03) && (! ((LocalCfgPtr->Sata.SataEspPort.SataPortReg) & (1 << PortNumByte))) ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG40 + 2), AccessWidth8, 0xFF, (1 << PortNumByte), StdHeader);
RwMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, ~(1 << PortNumByte), 00);
}
} ///end of for (PortNumByte=0;PortNumByte<6;PortNumByte++)
ReadMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, &PortSataStatusByte);
//
//if all ports are in disabled state, report at least one port
//
if ( (PortSataStatusByte & 0xFF) == 0) {
RwMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, (UINT32) ~(0xFF), 01);
}
ReadMem (Bar5 + FCH_SATA_BAR5_REG0C, AccessWidth8, &PortSataStatusByte);
for (PortNumByte = 0; PortNumByte < MAX_SATA_PORTS; PortNumByte ++) {
if (PortSataStatusByte & (1 << PortNumByte)) {
NumOfPorts++;
}
}
if ( NumOfPorts == 0) {
NumOfPorts = 0x01;
}
RwMem (Bar5 + FCH_SATA_BAR5_REG00, AccessWidth8, 0xE0, NumOfPorts - 1);
}
/**
* FchSataSetPortGenMode - Set Sata port mode (each) for
* Gen1/Gen2/Gen3
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchSataSetPortGenMode (
IN VOID *FchDataPtr
)
{
UINT32 Bar5;
UINT8 PortNumByte;
UINT8 PortModeByte;
UINT16 SataPortMode;
BOOLEAN FchSataHotRemovalEnh;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
FchSataHotRemovalEnh = LocalCfgPtr->Sata.SataHotRemovalEnh;
SataBar5setting (LocalCfgPtr, &Bar5);
SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode;
PortNumByte = 0;
while ( PortNumByte < 8 ) {
PortModeByte = (UINT8) (SataPortMode & 3);
if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) {
if ( PortModeByte == BIT0 ) {
//
// set GEN 1
//
RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x10);
}
if ( PortModeByte == BIT1 ) {
//
// set GEN2 (default is GEN3)
//
RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0x0F, 0x20);
}
RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFF, 0x01);
}
SataPortMode >>= 2;
PortNumByte ++;
}
FchStall (1000, StdHeader);
SataPortMode = (UINT16)LocalCfgPtr->Sata.SataPortMd.SataPortMode;
PortNumByte = 0;
while ( PortNumByte < 8 ) {
PortModeByte = (UINT8) (SataPortMode & 3);
if ( (PortModeByte == BIT0) || (PortModeByte == BIT1) ) {
RwMem (Bar5 + FCH_SATA_BAR5_REG12C + PortNumByte * 0x80, AccessWidth8, 0xFE, 0x00);
}
PortNumByte ++;
SataPortMode >>= 2;
}
//
// Sata Hot Removal Enhance setting
//
if ( FchSataHotRemovalEnh ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80), AccessWidth16, ~BIT8, BIT8, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REGA8), AccessWidth16, ~BIT0, BIT0, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG80), AccessWidth16, ~BIT8, 0, StdHeader);
}
}

86
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciEnv.c
View File

@ -1,86 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch SATA controller (Ide2Ahci mode)
*
* Init SATA Ide2Ahci features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_IDE2AHCIENV_FILECODE
/**
* FchInitEnvSataIde2Ahci - Config SATA Ide2Ahci controller
* before PCI emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvSataIde2Ahci (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
// Class code
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01018F40, StdHeader);
//
// Device ID
//
if ( LocalCfgPtr->Sata.SataClass == SataIde2Ahci7804 ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AMDAHCI_DID, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG02), AccessWidth16, 0, FCH_SATA_AHCI_DID, StdHeader);
}
//
// SSID
//
if (LocalCfgPtr->Sata.SataAhciSsid != NULL ) {
RwPci ((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Sata.SataAhciSsid, StdHeader);
}
}

82
src/vendorcode/amd/agesa/f12/Proc/Fch/Sata/Ide2AhciLate.c
View File

@ -1,82 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Config Fch SATA controller (Ide2Ahci mode)
*
* Init SATA Ide2Ahci features.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: FCH
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
*/
#include "FchPlatform.h"
#include "Filecode.h"
#define FILECODE PROC_FCH_SATA_IDE2AHCILATE_FILECODE
/**
* FchInitLateSataIde2Ahci - Prepare SATA Ide2Ahci controller to
* boot to OS.
*
* - Set class ID to Ide2Ahci (if set to Ide2Ahci * Mode)
* - Enable Ide2Ahci interrupt
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitLateSataIde2Ahci (
IN VOID *FchDataPtr
)
{
UINT32 Bar5;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
//
//program the AHCI class code
//
RwPci (((SATA_BUS_DEV_FUN << 16) + FCH_SATA_REG08), AccessWidth32, 0, 0x01060100, StdHeader);
SataBar5setting (LocalCfgPtr, &Bar5);
//
//Set interrupt enable bit
//
RwMem ((Bar5 + 0x04), AccessWidth8, (UINT32)~0, BIT1);
ShutdownUnconnectedSataPortClock (LocalCfgPtr, Bar5);
}

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