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Re-enable UART on galp5, default to disabled NVIDIA GPU

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Change-Id: I7dffdce4d213f083f1742695943fcff0c4859e80
This commit is contained in:
Jeremy Soller
2020-11-30 10:56:45 -07:00
parent c051009031
commit fd8c25ab61
3 changed files with 11 additions and 3 deletions
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2
src/mainboard/system76/galp5/bootblock.c
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@@ -7,5 +7,5 @@
void bootblock_mainboard_init(void) { void bootblock_mainboard_init(void) {
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
dgpu_power_enable(1); dgpu_power_enable(0);
} }

4
src/mainboard/system76/galp5/devicetree.cb
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@@ -280,6 +280,10 @@ chip soc/intel/tigerlake
#TODO Disable ME and HECI #TODO Disable ME and HECI
register "HeciEnabled" = "1" register "HeciEnabled" = "1"
end end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoPci"
end
device ref pcie_rp5 on device ref pcie_rp5 on
# PCIe root port #5 x4, Clock 2 (NVIDIA GPU) # PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
register "PcieRpEnable[4]" = "1" register "PcieRpEnable[4]" = "1"

8
src/mainboard/system76/galp5/gpio.h
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@@ -14,6 +14,10 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// UART2_RXD
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
// DGPU_RST#_PCH // DGPU_RST#_PCH
PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP), PAD_CFG_TERM_GPO(GPP_U4, 0, NONE, DEEP),
// DGPU_PWR_EN // DGPU_PWR_EN
@@ -183,9 +187,9 @@ static const struct pad_config gpio_table[] = {
// PCH_I2C_SCL // PCH_I2C_SCL
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
// UART2_RXD // UART2_RXD
PAD_NC(GPP_C20, NONE), PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
// UART2_TXD // UART2_TXD
PAD_NC(GPP_C21, NONE), PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
// LAN_PLT_RST# // LAN_PLT_RST#
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST), PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
// PCH_GPP_C23 - 4.7k pull-down // PCH_GPP_C23 - 4.7k pull-down