mb/intel/tglrvp: add Tiger Lake memory initialization support
Update memory parameters based on memory type supported by Tiger lake RVP 1. Update dq/dqs mappings 2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory 3. Add SPD data bin files for supported memory types 4. Update other FSPM UPDs as part of memory initialization BUG=none BRANCH=none TEST= build tglrvp flash and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Srinidhi N Kaushik
Patrick Georgi
parent
1f9112f798
commit
fdba0cd6af
@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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* Copyright (C) 2019-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -21,6 +21,11 @@
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/* Board/FAB ID Command */
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#define EC_FAB_ID_CMD 0x0D
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/* TGL-U Board IDs */
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#define TGL_U_LP4_SAMSUNG 0x3
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#define TGL_U_LP4_HYNIX 0xB
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#define TGL_U_LP4_MICRON 0x13
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/*
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* Returns board information (board id[15:8] and
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* Fab info[7:0]) on success and < 0 on error
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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* Copyright (C) 2019-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -12,11 +12,55 @@
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <console/console.h>
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#include <fsp/api.h>
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#include <soc/romstage.h>
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#include <spd_bin.h>
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#include <string.h>
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#include <soc/meminit_tgl.h>
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#include <baseboard/variants.h>
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#include <cbfs.h>
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#include "board_id.h"
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#include "spd/spd.h"
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static uintptr_t mainboard_get_spd_index(void)
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{
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uint8_t board_id = (get_board_id() & 0xFF);
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int spd_index;
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printk(BIOS_INFO, "board id is 0x%x\n", board_id);
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switch (board_id) {
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case TGL_U_LP4_MICRON:
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spd_index = SPD_ID_MICRON;
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break;
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case TGL_U_LP4_SAMSUNG:
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spd_index = SPD_ID_SAMSUNG;
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break;
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case TGL_U_LP4_HYNIX:
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spd_index = SPD_ID_HYNIX;
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break;
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default:
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spd_index = SPD_ID_MICRON;
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printk(BIOS_WARNING, "Invalid board_id 0x%x\n", board_id);
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}
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printk(BIOS_INFO, "SPD index is 0x%x\n", spd_index);
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return spd_index;
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}
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void mainboard_memory_init_params(FSPM_UPD *mupd)
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{
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/* ToDo : Fill FSP-M memory params */
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FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
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const struct mb_lpddr4x_cfg *mem_config = variant_memory_params();
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const struct spd_info spd_info = {
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.read_type = READ_SPD_CBFS,
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.spd_spec.spd_index = mainboard_get_spd_index(),
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};
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bool half_populated = false;
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meminit_lpddr4x_dimm0(mem_cfg, mem_config, &spd_info, half_populated);
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}
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@ -0,0 +1,32 @@
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23 11 11 0E 1B 21 F9 08 00 40 00 00 0A 01 00 00
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00 00 05 0F 92 54 01 00 8A 00 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 92 00 A7 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 56 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -1,7 +1,7 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2019 Intel Corporation.
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## Copyright (C) 2019-2020 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -13,8 +13,22 @@
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## GNU General Public License for more details.
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##
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romstage-y += spd_util.c
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SPD_BIN = $(obj)/spd.bin
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SPD_SOURCES = empty # 0b000
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SPD_SOURCES = Micron-MT53D1G64D8SQ-046
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SPD_SOURCES += Samsung-K4UBE3D4AA-MGCL
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SPD_SOURCES += Hynix-H9HKNNNEBMAV-4267
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SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
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# Include spd ROM data
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$(SPD_BIN): $(SPD_DEPS)
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for f in $+; \
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do for c in $$(cat $$f | grep -v ^#); \
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do printf $$(printf '\%o' 0x$$c); \
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done; \
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done > $@
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cbfs-files-y += spd.bin
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spd.bin-file := $(SPD_BIN)
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spd.bin-type := spd
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@ -0,0 +1,32 @@
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23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00
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48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0
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02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -0,0 +1,32 @@
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23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00
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48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
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04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
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20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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* Copyright (C) 2019-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -16,14 +16,16 @@
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#ifndef MAINBOARD_SPD_H
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#define MAINBOARD_SPD_H
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#include <stdint.h>
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/* SPD index definition should be matched with the order of SPD_SOURCES */
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#define SPD_ID_MICRON 0x0
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#define SPD_ID_SAMSUNG 0x1
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#define SPD_ID_HYNIX 0x2
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#define RCOMP_TARGET_PARAMS 0x5
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void mainboard_fill_dq_map_ch0(void *dq_map_ptr);
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void mainboard_fill_dq_map_ch1(void *dq_map_ptr);
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void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr);
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void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr);
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void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
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void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
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void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
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void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
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void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
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void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
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void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
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void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
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#endif
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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* Copyright (C) 2019-2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -17,6 +17,7 @@
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#define __BASEBOARD_VARIANTS_H__
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#include <soc/gpio.h>
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#include <soc/meminit_tgl.h>
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#include <stdint.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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@ -27,4 +28,7 @@ const struct pad_config *variant_gpio_table(size_t *num);
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const struct pad_config *variant_early_gpio_table(size_t *num);
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const struct cros_gpio *variant_cros_gpios(size_t *num);
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size_t variant_memory_sku(void);
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const struct mb_lpddr4x_cfg *variant_memory_params(void);
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#endif /*__BASEBOARD_VARIANTS_H__ */
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@ -1,7 +1,7 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2019 Intel Corporation.
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## Copyright (C) 2019-2020 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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@ -15,4 +15,6 @@
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bootblock-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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59
src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
Normal file
59
src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
Normal file
@ -0,0 +1,59 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2020 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/cpu.h>
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#include <baseboard/variants.h>
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#include <intelblocks/mp_init.h>
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size_t __weak variant_memory_sku(void)
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{
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return 0;
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}
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static const struct mb_lpddr4x_cfg mem_config = {
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/* DQ byte map */
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.dq_map = {
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{ 0, 1, 6, 7, 3, 2, 5, 4, /* Byte 0 */
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15, 8, 9, 14, 12, 11, 10, 13 }, /* Byte 1 */
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{ 11, 12, 8, 15, 9, 14, 10, 13, /* Byte 2 */
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3, 4, 7, 0, 6, 1, 5, 2 }, /* Byte 3 */
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{ 4, 5, 3, 2, 7, 1, 0, 6, /* Byte 4 */
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11, 10, 12, 13, 8, 9, 14, 15 }, /* Byte 5 */
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{ 12, 11, 8, 13, 14, 15, 9, 10, /* Byte 6 */
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4, 7, 3, 2, 1, 6, 0, 5 }, /* Byte 7 */
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{ 11, 10, 9, 8, 12, 13, 15, 14, /* Byte 0 */
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4, 5, 6, 7, 3, 2, 0, 1 }, /* Byte 1 */
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{ 0, 7, 1, 6, 3, 5, 2, 4, /* Byte 2 */
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9, 8, 10, 11, 14, 15, 13, 12 }, /* Byte 3 */
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{ 4, 5, 6, 1, 3, 2, 7, 0, /* Byte 4 */
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10, 13, 12, 11, 14, 9, 15, 8 }, /* Byte 5 */
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{ 10, 12, 9, 15, 8, 11, 13, 14, /* Byte 6 */
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3, 4, 1, 2, 6, 0, 5, 7 } /* Byte 7 */
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},
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/* DQS CPU<>DRAM map */
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.dqs_map = {
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/* Ch 0 1 2 3 */
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{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 },
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{ 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }
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},
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.ect = 1, /* Early Command Training */
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};
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const struct mb_lpddr4x_cfg *__weak variant_memory_params(void)
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{
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return &mem_config;
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}
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