bonw14
Change-Id: I533acb5e835de97c1ac52a201bca95671f53d932
This commit is contained in:
Jeremy Soller
@@ -1,5 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
struct drivers_i2c_tas5825m_config {
|
||||
//TODO
|
||||
// Used to uniquely identify the AMP
|
||||
int id;
|
||||
};
|
||||
|
||||
@@ -3,6 +3,7 @@
|
||||
#include <console/console.h>
|
||||
#include <device/smbus.h>
|
||||
#include <device/pci.h>
|
||||
#include "chip.h"
|
||||
#include "tas5825m.h"
|
||||
|
||||
int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value) {
|
||||
@@ -29,14 +30,7 @@ int tas5825m_set_book(struct device *dev, uint8_t book) {
|
||||
return tas5825m_write_at(dev, 0x7F, book);
|
||||
}
|
||||
|
||||
__weak int tas5825m_setup(struct device *dev) {
|
||||
struct drivers_i2c_tas5825m_config *config = dev->chip_info;
|
||||
|
||||
if (!config) {
|
||||
printk(BIOS_ERR, "tas5825m: failed to find config\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
__weak int tas5825m_setup(struct device *dev, int id) {
|
||||
printk(BIOS_ERR, "tas5825m: setup not implemented\n");
|
||||
return -1;
|
||||
}
|
||||
@@ -45,12 +39,20 @@ static void tas5825m_init(struct device *dev) {
|
||||
if (dev->enabled && dev->path.type == DEVICE_PATH_I2C &&
|
||||
ops_smbus_bus(get_pbus_smbus(dev))) {
|
||||
printk(BIOS_DEBUG, "tas5825m at %s\n", dev_path(dev));
|
||||
int res = tas5825m_setup(dev);
|
||||
if (res) {
|
||||
printk(BIOS_ERR, "tas5825m init failed: %d\n", res);
|
||||
|
||||
struct drivers_i2c_tas5825m_config *config = dev->chip_info;
|
||||
if (config) {
|
||||
printk(BIOS_DEBUG, "tas5825m id %d\n", config->id);
|
||||
int res = tas5825m_setup(dev, config->id);
|
||||
if (res) {
|
||||
printk(BIOS_ERR, "tas5825m init failed: %d\n", res);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "tas5825m init successful\n");
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "tas5825m init successful\n");
|
||||
printk(BIOS_ERR, "tas5825m: failed to find config\n");
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -7,6 +7,6 @@ int tas5825m_write_at(struct device *dev, uint8_t addr, uint8_t value);
|
||||
int tas5825m_write_block_at(struct device *dev, uint8_t addr, const uint8_t * values, uint8_t length);
|
||||
int tas5825m_set_page(struct device *dev, uint8_t page);
|
||||
int tas5825m_set_book(struct device *dev, uint8_t book);
|
||||
int tas5825m_setup(struct device *dev);
|
||||
int tas5825m_setup(struct device *dev, int id);
|
||||
|
||||
#endif // TAS5825M_H
|
||||
|
||||
@@ -321,6 +321,7 @@ chip soc/intel/cannonlake
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end # tas5825m
|
||||
end # SMBus
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
|
||||
#define amp_set_book(B) R(tas5825m_set_book(dev, B))
|
||||
|
||||
int tas5825m_setup(struct device * dev) {
|
||||
int tas5825m_setup(struct device * dev, int id) {
|
||||
int res = 0;
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
87
src/mainboard/system76/bonw14/Kconfig
Normal file
87
src/mainboard/system76/bonw14/Kconfig
Normal file
@@ -0,0 +1,87 @@
|
||||
if BOARD_SYSTEM76_BONW14
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
select DRIVERS_I2C_HID
|
||||
select DRIVERS_I2C_TAS5825M
|
||||
select DRIVERS_SYSTEM76_DGPU
|
||||
select EC_SYSTEM76_EC
|
||||
select EC_SYSTEM76_EC_COLOR_KEYBOARD
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_SMI_HANDLER
|
||||
select INTEL_LPSS_UART_FOR_CONSOLE
|
||||
select MAINBOARD_HAS_LPC_TPM
|
||||
select MAINBOARD_HAS_TPM2
|
||||
select NO_UART_ON_SUPERIO
|
||||
select PCIEXP_HOTPLUG
|
||||
select SOC_INTEL_CANNONLAKE_PCH_H
|
||||
select SOC_INTEL_COMETLAKE
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA
|
||||
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
|
||||
select SPD_READ_BY_WORD
|
||||
select SYSTEM_TYPE_LAPTOP
|
||||
select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
|
||||
|
||||
# Hack for correct FSP headers until coreboot is updated
|
||||
config FSP_HEADER_PATH
|
||||
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/Include/"
|
||||
|
||||
# Hack for correct FSP blobs until coreboot is updated
|
||||
config FSP_FD_PATH
|
||||
default "3rdparty/fsp/CometLakeFspBinPkg/CometLakeS/FSP.fd"
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default "system76/bonw14"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "bonw14"
|
||||
|
||||
config MAINBOARD_SMBIOS_PRODUCT_NAME
|
||||
string
|
||||
default "Bonobo WS"
|
||||
|
||||
config MAINBOARD_VERSION
|
||||
string
|
||||
default "bonw14"
|
||||
|
||||
config CBFS_SIZE
|
||||
hex
|
||||
default 0xA00000
|
||||
|
||||
config SUBSYSTEM_VENDOR_ID
|
||||
hex
|
||||
default 0x1558
|
||||
|
||||
config SUBSYSTEM_DEVICE_ID
|
||||
hex
|
||||
default 0x7714
|
||||
|
||||
config CONSOLE_POST
|
||||
bool
|
||||
default y
|
||||
|
||||
config UART_FOR_CONSOLE
|
||||
int
|
||||
default 2
|
||||
|
||||
config MAX_CPUS
|
||||
int
|
||||
default 20
|
||||
|
||||
config DIMM_MAX
|
||||
int
|
||||
default 4
|
||||
|
||||
config DIMM_SPD_SIZE
|
||||
int
|
||||
default 512
|
||||
|
||||
config POST_DEVICE
|
||||
bool
|
||||
default n
|
||||
|
||||
endif
|
||||
2
src/mainboard/system76/bonw14/Kconfig.name
Normal file
2
src/mainboard/system76/bonw14/Kconfig.name
Normal file
@@ -0,0 +1,2 @@
|
||||
config BOARD_SYSTEM76_BONW14
|
||||
bool "bonw14"
|
||||
4
src/mainboard/system76/bonw14/Makefile.inc
Normal file
4
src/mainboard/system76/bonw14/Makefile.inc
Normal file
@@ -0,0 +1,4 @@
|
||||
bootblock-y += bootblock.c
|
||||
ramstage-y += ramstage.c
|
||||
ramstage-y += hda_verb.c
|
||||
ramstage-y += tas5825m.c
|
||||
512
src/mainboard/system76/bonw14/acpi/dgpu.asl
Normal file
512
src/mainboard/system76/bonw14/acpi/dgpu.asl
Normal file
@@ -0,0 +1,512 @@
|
||||
Device (\_SB.PCI0.PEG0) {
|
||||
Name (_ADR, 0x00010000)
|
||||
|
||||
Device (PEGP) {
|
||||
Name (_ADR, Zero)
|
||||
|
||||
// Convert a byte to a hex string, trimming extra parts
|
||||
Method (BHEX, 1) {
|
||||
Local0 = ToHexString(Arg0)
|
||||
Return (Mid(Local0, SizeOf(Local0) - 2, 2))
|
||||
}
|
||||
|
||||
// UUID to string
|
||||
Method (IDST, 1) {
|
||||
Local0 = ""
|
||||
Fprintf(
|
||||
Local0,
|
||||
"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
|
||||
BHEX(DerefOf(Arg0[3])),
|
||||
BHEX(DerefOf(Arg0[2])),
|
||||
BHEX(DerefOf(Arg0[1])),
|
||||
BHEX(DerefOf(Arg0[0])),
|
||||
BHEX(DerefOf(Arg0[5])),
|
||||
BHEX(DerefOf(Arg0[4])),
|
||||
BHEX(DerefOf(Arg0[7])),
|
||||
BHEX(DerefOf(Arg0[6])),
|
||||
BHEX(DerefOf(Arg0[8])),
|
||||
BHEX(DerefOf(Arg0[9])),
|
||||
BHEX(DerefOf(Arg0[10])),
|
||||
BHEX(DerefOf(Arg0[11])),
|
||||
BHEX(DerefOf(Arg0[12])),
|
||||
BHEX(DerefOf(Arg0[13])),
|
||||
BHEX(DerefOf(Arg0[14])),
|
||||
BHEX(DerefOf(Arg0[15]))
|
||||
)
|
||||
Return (Local0)
|
||||
}
|
||||
|
||||
// Safe hex conversion, checks type first
|
||||
Method (SFST, 1) {
|
||||
Local0 = ObjectType(Arg0)
|
||||
If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
|
||||
Return (ToHexString(Arg0))
|
||||
} Else {
|
||||
Return (Concatenate("Type: ", Arg0))
|
||||
}
|
||||
}
|
||||
|
||||
Method (_DSM, 4, Serialized) {
|
||||
Debug = "NVIDIA _DSM"
|
||||
Printf(" Arg0: %o", IDST(Arg0))
|
||||
Printf(" Arg1: %o", SFST(Arg1))
|
||||
Printf(" Arg2: %o", SFST(Arg2))
|
||||
Printf(" Arg3: %o", SFST(Arg3))
|
||||
|
||||
If (Arg0 == ToUUID ("d4a50b75-65c7-46f7-bfb7-41514cea0244")) {
|
||||
If (Arg1 != 0x0102) {
|
||||
Printf(" Invalid Arg1, return 0x80000002")
|
||||
Return (0x80000002)
|
||||
}
|
||||
|
||||
If (Arg2 == 0) {
|
||||
Printf(" Arg2 == 0x00, return some buffer")
|
||||
Return (Buffer (4) {
|
||||
0x01, 0x00, 0x11, 0x00
|
||||
})
|
||||
}
|
||||
|
||||
If (Arg2 == 0x10) {
|
||||
CreateWordField (Arg3, 0x02, BFF0)
|
||||
Printf(" Arg2 = 0x10, return buffer %o", ToHexString(BFF0))
|
||||
If (BFF0 == 0x564B) { // 'VK'
|
||||
Printf(" Return GVK")
|
||||
Return (Buffer (0xD5) {
|
||||
0xA6,
|
||||
0x92,
|
||||
0x17,
|
||||
0xE2,
|
||||
0x85,
|
||||
0x2A,
|
||||
0xED,
|
||||
0x48,
|
||||
0x4B,
|
||||
0x56,
|
||||
0xD5,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x01,
|
||||
0x00,
|
||||
0x37,
|
||||
0x35,
|
||||
0x31,
|
||||
0x31,
|
||||
0x31,
|
||||
0x35,
|
||||
0x38,
|
||||
0x37,
|
||||
0x39,
|
||||
0x38,
|
||||
0x34,
|
||||
0x39,
|
||||
0x47,
|
||||
0x65,
|
||||
0x6E,
|
||||
0x75,
|
||||
0x69,
|
||||
0x6E,
|
||||
0x65,
|
||||
0x20,
|
||||
0x4E,
|
||||
0x56,
|
||||
0x49,
|
||||
0x44,
|
||||
0x49,
|
||||
0x41,
|
||||
0x20,
|
||||
0x43,
|
||||
0x65,
|
||||
0x72,
|
||||
0x74,
|
||||
0x69,
|
||||
0x66,
|
||||
0x69,
|
||||
0x65,
|
||||
0x64,
|
||||
0x20,
|
||||
0x47,
|
||||
0x53,
|
||||
0x79,
|
||||
0x6E,
|
||||
0x63,
|
||||
0x20,
|
||||
0x52,
|
||||
0x65,
|
||||
0x61,
|
||||
0x64,
|
||||
0x79,
|
||||
0x20,
|
||||
0x50,
|
||||
0x6C,
|
||||
0x61,
|
||||
0x74,
|
||||
0x66,
|
||||
0x6F,
|
||||
0x72,
|
||||
0x6D,
|
||||
0x20,
|
||||
0x66,
|
||||
0x6F,
|
||||
0x72,
|
||||
0x20,
|
||||
0x43,
|
||||
0x4C,
|
||||
0x45,
|
||||
0x56,
|
||||
0x4F,
|
||||
0x20,
|
||||
0x32,
|
||||
0x30,
|
||||
0x30,
|
||||
0x35,
|
||||
0x39,
|
||||
0x30,
|
||||
0x38,
|
||||
0x38,
|
||||
0x30,
|
||||
0x20,
|
||||
0x20,
|
||||
0x20,
|
||||
0x20,
|
||||
0x20,
|
||||
0x20,
|
||||
0x2D,
|
||||
0x20,
|
||||
0x31,
|
||||
0x39,
|
||||
0x27,
|
||||
0x3B,
|
||||
0x36,
|
||||
0x28,
|
||||
0x53,
|
||||
0x5E,
|
||||
0x26,
|
||||
0x2B,
|
||||
0x35,
|
||||
0x39,
|
||||
0x55,
|
||||
0x56,
|
||||
0x32,
|
||||
0x30,
|
||||
0x58,
|
||||
0x44,
|
||||
0x26,
|
||||
0x32,
|
||||
0x44,
|
||||
0x5C,
|
||||
0x23,
|
||||
0x2E,
|
||||
0x31,
|
||||
0x39,
|
||||
0x32,
|
||||
0x49,
|
||||
0x3E,
|
||||
0x25,
|
||||
0x3B,
|
||||
0x41,
|
||||
0x57,
|
||||
0x50,
|
||||
0x5A,
|
||||
0x56,
|
||||
0x2C,
|
||||
0x3E,
|
||||
0x5F,
|
||||
0x38,
|
||||
0x20,
|
||||
0x2D,
|
||||
0x20,
|
||||
0x43,
|
||||
0x6F,
|
||||
0x70,
|
||||
0x79,
|
||||
0x72,
|
||||
0x69,
|
||||
0x67,
|
||||
0x68,
|
||||
0x74,
|
||||
0x20,
|
||||
0x32,
|
||||
0x30,
|
||||
0x31,
|
||||
0x34,
|
||||
0x20,
|
||||
0x4E,
|
||||
0x56,
|
||||
0x49,
|
||||
0x44,
|
||||
0x49,
|
||||
0x41,
|
||||
0x20,
|
||||
0x43,
|
||||
0x6F,
|
||||
0x72,
|
||||
0x70,
|
||||
0x6F,
|
||||
0x72,
|
||||
0x61,
|
||||
0x74,
|
||||
0x69,
|
||||
0x6F,
|
||||
0x6E,
|
||||
0x20,
|
||||
0x41,
|
||||
0x6C,
|
||||
0x6C,
|
||||
0x20,
|
||||
0x52,
|
||||
0x69,
|
||||
0x67,
|
||||
0x68,
|
||||
0x74,
|
||||
0x73,
|
||||
0x20,
|
||||
0x52,
|
||||
0x65,
|
||||
0x73,
|
||||
0x65,
|
||||
0x72,
|
||||
0x76,
|
||||
0x65,
|
||||
0x64,
|
||||
0x2D,
|
||||
0x35,
|
||||
0x38,
|
||||
0x39,
|
||||
0x36,
|
||||
0x38,
|
||||
0x34,
|
||||
0x30,
|
||||
0x32,
|
||||
0x39,
|
||||
0x33,
|
||||
0x38,
|
||||
0x35,
|
||||
0x28,
|
||||
0x52,
|
||||
0x29,
|
||||
})
|
||||
}
|
||||
|
||||
If (BFF0 == 0x4452) { // 'DR'
|
||||
Printf(" Return GDK")
|
||||
Return (Buffer (0xAA) {
|
||||
0xB4,
|
||||
0x6B,
|
||||
0x02,
|
||||
0x49,
|
||||
0x41,
|
||||
0x16,
|
||||
0x1C,
|
||||
0xD2,
|
||||
0x52,
|
||||
0x44,
|
||||
0xAA,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x01,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xDE,
|
||||
0x10,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x09,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x34,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x01,
|
||||
0x00,
|
||||
0x47,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x02,
|
||||
0x00,
|
||||
0x45,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x03,
|
||||
0x00,
|
||||
0x5A,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x04,
|
||||
0x00,
|
||||
0x58,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x05,
|
||||
0x00,
|
||||
0x56,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x06,
|
||||
0x00,
|
||||
0x54,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x07,
|
||||
0x00,
|
||||
0x52,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08,
|
||||
0x00,
|
||||
0x50,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x01,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xD9,
|
||||
0x1C,
|
||||
0x04,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x02,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x41,
|
||||
0x5D,
|
||||
0xC9,
|
||||
0x00,
|
||||
0x01,
|
||||
0x24,
|
||||
0x2E,
|
||||
0x00,
|
||||
0x02,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x01,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xD9,
|
||||
0x1C,
|
||||
0x04,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x03,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xE0,
|
||||
0x7C,
|
||||
0x97,
|
||||
0x01,
|
||||
0xC1,
|
||||
0x3D,
|
||||
0x9C,
|
||||
0x1B,
|
||||
0x41,
|
||||
0x60,
|
||||
0x68,
|
||||
0x9E,
|
||||
0x35,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
If (Arg2 == 0x14) {
|
||||
Printf(" Arg2 == 0x14, return backlight package")
|
||||
Return (Package (9) {
|
||||
0x8000A450,
|
||||
0x0200,
|
||||
Zero,
|
||||
Zero,
|
||||
One,
|
||||
One,
|
||||
200,
|
||||
32,
|
||||
1000
|
||||
})
|
||||
}
|
||||
|
||||
Printf(" Unknown Arg2, return 0x80000002")
|
||||
Return (0x80000002)
|
||||
}
|
||||
|
||||
Printf(" Unknown Arg0, return 0x80000001")
|
||||
Return (0x80000001)
|
||||
}
|
||||
|
||||
Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices
|
||||
{
|
||||
Return (Package (3) {
|
||||
0x80008320,
|
||||
0x80006330,
|
||||
0x8000A450
|
||||
})
|
||||
}
|
||||
|
||||
Device (HDM0) {
|
||||
Name (_ADR, 0x80008320)
|
||||
}
|
||||
|
||||
Device (DSP0) {
|
||||
Name (_ADR, 0x80006330)
|
||||
}
|
||||
|
||||
Device (DSP1) {
|
||||
Name (_ADR, 0x8000A450)
|
||||
}
|
||||
}
|
||||
}
|
||||
11
src/mainboard/system76/bonw14/acpi/gpe.asl
Normal file
11
src/mainboard/system76/bonw14/acpi/gpe.asl
Normal file
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
// GPP_K6 SCI
|
||||
Method (_L06, 0, Serialized) {
|
||||
Debug = Concatenate("GPE _L06: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO))
|
||||
If (\_SB.PCI0.LPCB.EC0.ECOK) {
|
||||
If (\_SB.PCI0.LPCB.EC0.WFNO == One) {
|
||||
Notify(\_SB.LID0, 0x80)
|
||||
}
|
||||
}
|
||||
}
|
||||
15
src/mainboard/system76/bonw14/acpi/mainboard.asl
Normal file
15
src/mainboard/system76/bonw14/acpi/mainboard.asl
Normal file
@@ -0,0 +1,15 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#define EC_GPE_SCI 0x03 /* GPP_K3 */
|
||||
#define EC_GPE_SWI 0x06 /* GPP_K6 */
|
||||
#include <ec/system76/ec/acpi/ec.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
#include "sleep.asl"
|
||||
}
|
||||
|
||||
Scope (\_GPE) {
|
||||
#include "gpe.asl"
|
||||
}
|
||||
|
||||
#include "dgpu.asl"
|
||||
11
src/mainboard/system76/bonw14/acpi/sleep.asl
Normal file
11
src/mainboard/system76/bonw14/acpi/sleep.asl
Normal file
@@ -0,0 +1,11 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Method called from _PTS prior to enter sleep state */
|
||||
Method (MPTS, 1) {
|
||||
\_SB.PCI0.LPCB.EC0.PTS (Arg0)
|
||||
}
|
||||
|
||||
/* Method called from _WAK prior to wakeup */
|
||||
Method (MWAK, 1) {
|
||||
\_SB.PCI0.LPCB.EC0.WAK (Arg0)
|
||||
}
|
||||
8
src/mainboard/system76/bonw14/board_info.txt
Normal file
8
src/mainboard/system76/bonw14/board_info.txt
Normal file
@@ -0,0 +1,8 @@
|
||||
Vendor name: System76
|
||||
Board name: bonw14
|
||||
Category: laptop
|
||||
Release year: 2020
|
||||
ROM package: SOIC-8
|
||||
ROM protocol: SPI
|
||||
ROM socketed: n
|
||||
Flashrom support: y
|
||||
9
src/mainboard/system76/bonw14/bootblock.c
Normal file
9
src/mainboard/system76/bonw14/bootblock.c
Normal file
@@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <bootblock_common.h>
|
||||
#include <gpio.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void bootblock_mainboard_init(void) {
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
325
src/mainboard/system76/bonw14/devicetree.cb
Normal file
325
src/mainboard/system76/bonw14/devicetree.cb
Normal file
@@ -0,0 +1,325 @@
|
||||
chip soc/intel/cannonlake
|
||||
# Lock Down
|
||||
register "common_soc_config" = "{
|
||||
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
|
||||
// Touchpad I2C bus
|
||||
.i2c[0] = {
|
||||
.speed = I2C_SPEED_FAST,
|
||||
.rise_time_ns = 80,
|
||||
.fall_time_ns = 110,
|
||||
},
|
||||
}"
|
||||
|
||||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
# ACPI (soc/intel/cannonlake/acpi.c)
|
||||
# Enable s0ix
|
||||
register "s0ix_enable" = "0"
|
||||
|
||||
# PM Timer Enabled
|
||||
register "PmTimerDisabled" = "0"
|
||||
|
||||
# Disable DPTF
|
||||
register "dptf_enable" = "0"
|
||||
|
||||
# CPU (soc/intel/cannonlake/cpu.c)
|
||||
# Power limit
|
||||
register "power_limits_config" = "{
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
|
||||
.tdp_pl1_override = 125,
|
||||
// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
|
||||
.tdp_pl2_override = 160,
|
||||
}"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# Enable Enhanced Intel SpeedStep
|
||||
register "eist_enable" = "1"
|
||||
|
||||
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
|
||||
register "enable_c6dram" = "1"
|
||||
|
||||
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
|
||||
# Serial I/O
|
||||
register "SerialIoDevMode" = "{
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus
|
||||
[PchSerialIoIndexUART2] = PchSerialIoPci, // Debug console
|
||||
}"
|
||||
|
||||
# SATA
|
||||
register "SataMode" = "Sata_AHCI"
|
||||
register "SataSalpSupport" = "0"
|
||||
|
||||
register "SataPortsEnable[0]" = "0"
|
||||
register "SataPortsEnable[1]" = "1" # SATA1A (SSD)
|
||||
register "SataPortsEnable[2]" = "0"
|
||||
register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3)
|
||||
register "SataPortsEnable[4]" = "1" # SATA4 (SSD2)
|
||||
register "SataPortsEnable[5]" = "0"
|
||||
register "SataPortsEnable[6]" = "0"
|
||||
register "SataPortsEnable[7]" = "0"
|
||||
|
||||
register "SataPortsDevSlp[0]" = "0"
|
||||
register "SataPortsDevSlp[1]" = "0"
|
||||
register "SataPortsDevSlp[2]" = "0"
|
||||
register "SataPortsDevSlp[3]" = "0"
|
||||
register "SataPortsDevSlp[4]" = "0"
|
||||
register "SataPortsDevSlp[5]" = "0"
|
||||
register "SataPortsDevSlp[6]" = "0"
|
||||
register "SataPortsDevSlp[7]" = "0"
|
||||
|
||||
# Audio
|
||||
register "PchHdaDspEnable" = "0"
|
||||
register "PchHdaAudioLinkHda" = "1"
|
||||
register "PchHdaAudioLinkDmic0" = "0"
|
||||
register "PchHdaAudioLinkDmic1" = "0"
|
||||
register "PchHdaAudioLinkSsp0" = "0"
|
||||
register "PchHdaAudioLinkSsp1" = "0"
|
||||
register "PchHdaAudioLinkSsp2" = "0"
|
||||
register "PchHdaAudioLinkSndw1" = "0"
|
||||
register "PchHdaAudioLinkSndw2" = "0"
|
||||
register "PchHdaAudioLinkSndw3" = "0"
|
||||
register "PchHdaAudioLinkSndw4" = "0"
|
||||
|
||||
# USB
|
||||
register "SsicPortEnable" = "0"
|
||||
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB
|
||||
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[10]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[11]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[12]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
register "usb2_ports[14]" = "USB2_PORT_EMPTY"
|
||||
register "usb2_ports[15]" = "USB2_PORT_EMPTY"
|
||||
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3
|
||||
register "usb3_ports[4]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[5]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[6]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[7]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[8]" = "USB3_PORT_EMPTY"
|
||||
register "usb3_ports[9]" = "USB3_PORT_EMPTY"
|
||||
|
||||
# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
|
||||
register "PcieClkSrcUsage[7]" = "0x40"
|
||||
|
||||
# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
|
||||
register "PcieRpEnable[0]" = "1"
|
||||
register "PcieRpLtrEnable[0]" = "1"
|
||||
register "PcieRpHotPlug[0]" = "1"
|
||||
register "PcieClkSrcUsage[6]" = "0"
|
||||
|
||||
# PCI Express root port #5 x4, Clock 10 (USB 3.2)
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
register "PcieClkSrcUsage[10]" = "4"
|
||||
|
||||
# PCI Express root port #9 x4, Clock 8 (SSD)
|
||||
register "PcieRpEnable[8]" = "1"
|
||||
register "PcieRpLtrEnable[8]" = "1"
|
||||
register "PcieClkSrcUsage[8]" = "8"
|
||||
|
||||
# PCI Express root port #13 x1, Clock 0 (WLAN)
|
||||
register "PcieRpEnable[12]" = "1"
|
||||
register "PcieRpLtrEnable[12]" = "1"
|
||||
register "PcieClkSrcUsage[0]" = "12"
|
||||
|
||||
# PCI Express root port #14 x1, Clock 1 (GLAN)
|
||||
register "PcieRpEnable[13]" = "1"
|
||||
register "PcieRpLtrEnable[13]" = "1"
|
||||
register "PcieClkSrcUsage[1]" = "13"
|
||||
|
||||
# PCI Express root port #15 x1, Clock 4 (Card Reader)
|
||||
register "PcieRpEnable[14]" = "1"
|
||||
register "PcieRpLtrEnable[14]" = "1"
|
||||
register "PcieClkSrcUsage[4]" = "14"
|
||||
|
||||
# PCI Express root port #17 x4, Clock 14 (SSD2)
|
||||
register "PcieRpEnable[16]" = "1"
|
||||
register "PcieRpLtrEnable[16]" = "1"
|
||||
register "PcieClkSrcUsage[14]" = "16"
|
||||
|
||||
# PCI Express root port #21 x4, Clock 15 (SSD3)
|
||||
register "PcieRpEnable[20]" = "1"
|
||||
register "PcieRpLtrEnable[20]" = "1"
|
||||
register "PcieClkSrcUsage[15]" = "20"
|
||||
|
||||
# Set all clocks sources to the same clock request
|
||||
register "PcieClkSrcClkReq[0]" = "0"
|
||||
register "PcieClkSrcClkReq[1]" = "1"
|
||||
register "PcieClkSrcClkReq[2]" = "2"
|
||||
register "PcieClkSrcClkReq[3]" = "3"
|
||||
register "PcieClkSrcClkReq[4]" = "4"
|
||||
register "PcieClkSrcClkReq[5]" = "5"
|
||||
register "PcieClkSrcClkReq[6]" = "6"
|
||||
register "PcieClkSrcClkReq[7]" = "7"
|
||||
register "PcieClkSrcClkReq[8]" = "8"
|
||||
register "PcieClkSrcClkReq[9]" = "9"
|
||||
register "PcieClkSrcClkReq[10]" = "10"
|
||||
register "PcieClkSrcClkReq[11]" = "11"
|
||||
register "PcieClkSrcClkReq[12]" = "12"
|
||||
register "PcieClkSrcClkReq[13]" = "13"
|
||||
register "PcieClkSrcClkReq[14]" = "14"
|
||||
register "PcieClkSrcClkReq[15]" = "15"
|
||||
|
||||
# Misc
|
||||
register "Device4Enable" = "1"
|
||||
register "HeciEnabled" = "0"
|
||||
register "Heci3Enabled" = "0"
|
||||
register "AcousticNoiseMitigation" = "1"
|
||||
#register "dmipwroptimize" = "1"
|
||||
#register "satapwroptimize" = "1"
|
||||
|
||||
# TODO: painfully verify this shit
|
||||
# Power
|
||||
# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 11:10
|
||||
# WARNING: must then be mapped from FSP value to PCH value
|
||||
register "PchPmSlpS3MinAssert" = "3" # 50ms
|
||||
# sudo devmem2 0xfe001020 (pmc_bar + GEN_PMCON_A), bits 5:4
|
||||
# WARNING: must then be mapped from FSP value to PCH value
|
||||
register "PchPmSlpS4MinAssert" = "1" # 1s
|
||||
# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 19:18
|
||||
# WARNING: must then be mapped from FSP value to PCH value
|
||||
register "PchPmSlpSusMinAssert" = "4" # 4s
|
||||
# sudo devmem2 0xfe001818 (pmc_bar + PM_CFG), bits 17:16
|
||||
# WARNING: must then be mapped from FSP value to PCH value
|
||||
register "PchPmSlpAMinAssert" = "4" # 2s
|
||||
|
||||
# Thermal
|
||||
# rdmsr --bitfield 31:24 --decimal 0x1A2
|
||||
register "tcc_offset" = "13"
|
||||
|
||||
# LPC (soc/intel/cannonlake/lpc.c)
|
||||
# LPC configuration from lspci -s 1f.0 -xxx
|
||||
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
|
||||
register "gen1_dec" = "0x000c0081"
|
||||
# Address 0x88: Decode 0x68 - 0x6F (PMC)
|
||||
register "gen2_dec" = "0x00040069"
|
||||
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
|
||||
register "gen3_dec" = "0x00fc0E01"
|
||||
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
|
||||
register "gen4_dec" = "0x00fc0F01"
|
||||
|
||||
# PM Util (soc/intel/cannonlake/pmutil.c)
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
|
||||
register "gpe0_dw0" = "PMC_GPP_K"
|
||||
register "gpe0_dw1" = "PMC_GPP_G"
|
||||
register "gpe0_dw2" = "PMC_GPP_E"
|
||||
|
||||
# Actual device tree
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 01.0 on end # GPU Port
|
||||
#TODO: is this enough to disable iGPU?
|
||||
device pci 02.0 off end # Integrated Graphics Device
|
||||
device pci 04.0 on end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 13.0 off end # Integrated Sensor Hub
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on end # Shared SRAM
|
||||
#chip drivers/intel/wifi
|
||||
# register "wake" = "PME_B0_EN_BIT"
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
#end
|
||||
device pci 14.5 off end # SDCard
|
||||
device pci 15.0 on
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""PNP0C50""
|
||||
register "generic.desc" = ""Synaptics Touchpad""
|
||||
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
|
||||
register "generic.probed" = "1"
|
||||
register "hid_desc_reg_offset" = "0x20"
|
||||
device i2c 2c on end
|
||||
end
|
||||
end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 off end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 off end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 on end # UART #2
|
||||
device pci 1a.0 off end # eMMC
|
||||
device pci 1b.0 on end # PCI Express Port 17
|
||||
device pci 1b.1 off end # PCI Express Port 18
|
||||
device pci 1b.2 off end # PCI Express Port 19
|
||||
device pci 1b.3 off end # PCI Express Port 20
|
||||
device pci 1b.4 on end # PCI Express Port 21
|
||||
device pci 1b.5 off end # PCI Express Port 22
|
||||
device pci 1b.6 off end # PCI Express Port 23
|
||||
device pci 1b.7 off end # PCI Express Port 24
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 on end # PCI Express Port 13
|
||||
device pci 1d.5 on end # PCI Express Port 14
|
||||
device pci 1d.6 on end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on # LPC Interface
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 0c31.0 on end
|
||||
end
|
||||
end
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 off end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end # tas5825m
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "1"
|
||||
device i2c 4f on end # (8bit address: 0x9e)
|
||||
end # tas5825m
|
||||
end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
29
src/mainboard/system76/bonw14/dsdt.asl
Normal file
29
src/mainboard/system76/bonw14/dsdt.asl
Normal file
@@ -0,0 +1,29 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0 and up
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/cannonlake/acpi/platform.asl>
|
||||
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Device (\_SB.PCI0) {
|
||||
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
|
||||
#include <soc/intel/cannonlake/acpi/southbridge.asl>
|
||||
}
|
||||
|
||||
#include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB.PCI0.LPCB) {
|
||||
#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
}
|
||||
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
253
src/mainboard/system76/bonw14/gpio.h
Normal file
253
src/mainboard/system76/bonw14/gpio.h
Normal file
@@ -0,0 +1,253 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#ifndef __ACPI__
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
/* Pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
//TODO: add early GPIO settings
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
|
||||
};
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
//TODO: GPIO names and verify everything
|
||||
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD2, NATIVE, PWROK),
|
||||
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD6, UP_20K, PWROK, NF1),
|
||||
PAD_CFG_GPI(GPD7, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPD11, UP_20K, PWROK),
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1),
|
||||
_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_A12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A15, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_A17, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A19, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_A20, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_A21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_A23, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B0, 0x42080100, 0x3000), // TPM_PIRQ#
|
||||
PAD_CFG_GPI(GPP_B1, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_B3, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_B4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // WLAN_CLKREQ#
|
||||
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GLAN_CLKREQ#
|
||||
PAD_CFG_GPI(GPP_B7, UP_20K, PLTRST), // GPIO_CR_RESET_R
|
||||
PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), // CR_GPIO_WAKE_N_R
|
||||
PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // CR_CLKREQ#
|
||||
PAD_CFG_GPI(GPP_B10, UP_20K, PLTRST), // PRSNT#
|
||||
PAD_CFG_TERM_GPO(GPP_B11, 1, NONE, DEEP),
|
||||
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_B15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B19, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_B20, 0x42040100, 0x0000),
|
||||
PAD_CFG_GPI(GPP_B21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_B22, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C2, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_C8, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_C9, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C10, DN_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_C11, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_C12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C15, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C18, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C19, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_C22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_C23, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3),
|
||||
PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1),
|
||||
PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1),
|
||||
PAD_CFG_GPI(GPP_D9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D14, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D16, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_D21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_D23, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), // M.2_SSD1_DET_N
|
||||
PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), // VCCIO_0_CTRL
|
||||
PAD_CFG_GPI(GPP_E3, UP_20K, DEEP), // SMI#
|
||||
PAD_CFG_GPI(GPP_E4, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), // TP_ATTN#
|
||||
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // PCH_SATAHDD_LED#
|
||||
PAD_CFG_GPI(GPP_E9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), // M.2_SSD2_DET_N
|
||||
PAD_CFG_TERM_GPO(GPP_F2, 0, UP_20K, PLTRST), // GPP_F2_TBT_RST#
|
||||
PAD_CFG_NF(GPP_F3, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF2),
|
||||
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_F7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F8, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F9, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F10, UP_20K, DEEP), // PCH_CONFIG_JUMPER
|
||||
PAD_CFG_TERM_GPO(GPP_F11, 0, NONE, DEEP), // SSD1_PWR_DN#
|
||||
PAD_CFG_GPI(GPP_F12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F13, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_F15, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_F21, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_F22, 1, UP_20K, DEEP), // DGPU_RST#_PCH
|
||||
PAD_CFG_TERM_GPO(GPP_F23, 0, NONE, DEEP), // GC_OFF_EN
|
||||
PAD_CFG_GPI(GPP_G0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G1, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G3, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G4, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G5, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_G7, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), // TBT_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // MXM_REQ#
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // SSD_CLKREQ#
|
||||
PAD_CFG_GPI(GPP_H3, NONE, PLTRST),
|
||||
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // PE_CLKREQ#
|
||||
PAD_CFG_GPI(GPP_H5, NONE, PLTRST),
|
||||
PAD_CFG_GPI(GPP_H6, NONE, PLTRST), // WLAN_GPIO_WAKE_N
|
||||
PAD_CFG_TERM_GPO(GPP_H7, 0, NONE, DEEP), // PCIE_SSD2_RESET
|
||||
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // SSD2_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // SSD3_CLKREQ#
|
||||
PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_H11, 0, NONE, DEEP), // SSD3_PWR_DN#
|
||||
PAD_CFG_GPI(GPP_H12, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H13, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H14, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_H15, 0x40880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_H16, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H17, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H18, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H21, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H22, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_H23, UP_20K, DEEP),
|
||||
_PAD_CFG_STRUCT(GPP_I0, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I1, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I2, 0x46080100, 0x0000),
|
||||
_PAD_CFG_STRUCT(GPP_I3, 0x46080100, 0x0000),
|
||||
PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),
|
||||
PAD_CFG_TERM_GPO(GPP_I5, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I6, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I7, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_I8, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I9, 1, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I10, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I11, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I12, 0, NONE, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_I13, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_I14, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF2),
|
||||
PAD_CFG_GPI(GPP_J2, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J3, UP_20K, DEEP),
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J7, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J8, NONE, DEEP, NF1),
|
||||
PAD_CFG_NF(GPP_J9, UP_20K, DEEP, NF1),
|
||||
PAD_CFG_GPI(GPP_J10, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_J11, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K0, UP_20K, DEEP), // PCH_GPIO_PK_MUTE
|
||||
PAD_CFG_GPI(GPP_K1, UP_20K, DEEP), // PCH_GPIO_WOOFER_MUTE
|
||||
PAD_CFG_GPI(GPP_K2, UP_20K, DEEP), // DGPU_PWRGD
|
||||
_PAD_CFG_STRUCT(GPP_K3, 0x80880100, 0x3000), // SCI#
|
||||
PAD_CFG_GPI(GPP_K4, UP_20K, DEEP), // GPU_EVENT#_R
|
||||
PAD_CFG_TERM_GPO(GPP_K5, 0, NONE, DEEP), // DP_MUX_SW
|
||||
_PAD_CFG_STRUCT(GPP_K6, 0x40880100, 0x0000), // SWI#
|
||||
PAD_CFG_GPI(GPP_K7, UP_20K, DEEP), // E3100_PWR_EN
|
||||
PAD_CFG_TERM_GPO(GPP_K8, 0, NONE, DEEP), // SSD4_PWR_DN#
|
||||
PAD_CFG_GPI(GPP_K9, UP_20K, DEEP), // TBTA_HRESET
|
||||
PAD_CFG_GPI(GPP_K10, UP_20K, DEEP), // MIC_SENSE_PCH
|
||||
PAD_CFG_GPI(GPP_K11, UP_20K, DEEP), // XFI_SENSE_PCH
|
||||
_PAD_CFG_STRUCT(GPP_K12, 0x82880100, 0x3000),
|
||||
PAD_CFG_GPI(GPP_K13, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K14, 0, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K15, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K16, 0, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K17, UP_20K, DEEP),
|
||||
PAD_CFG_TERM_GPO(GPP_K18, 1, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_K19, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K20, UP_20K, DEEP),
|
||||
PAD_CFG_GPI(GPP_K21, NONE, DEEP), // GC6_FB_EN
|
||||
PAD_CFG_TERM_GPO(GPP_K22, 0, UP_5K, DEEP), // GPU_PWR_EN#
|
||||
PAD_CFG_TERM_GPO(GPP_K23, 0, NONE, PLTRST),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
35
src/mainboard/system76/bonw14/hda_verb.c
Normal file
35
src/mainboard/system76/bonw14/hda_verb.c
Normal file
@@ -0,0 +1,35 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef HDA_VERB_H
|
||||
#define HDA_VERB_H
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x15587714, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x15587714),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x4094022d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451120),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
// Enable DMIC microphone on ALC1220
|
||||
0x02050036,
|
||||
0x02042a6a,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
||||
#endif
|
||||
10
src/mainboard/system76/bonw14/ramstage.c
Normal file
10
src/mainboard/system76/bonw14/ramstage.c
Normal file
@@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
|
||||
/* Configure pads prior to SiliconInit() in case there's any
|
||||
* dependencies during hardware initialization. */
|
||||
cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
93
src/mainboard/system76/bonw14/romstage.c
Normal file
93
src/mainboard/system76/bonw14/romstage.c
Normal file
@@ -0,0 +1,93 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/cnl_memcfg_init.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct cnl_mb_cfg memcfg = {
|
||||
/* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */
|
||||
.spd[0] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa0},
|
||||
},
|
||||
.spd[1] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa2},
|
||||
},
|
||||
.spd[2] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa4},
|
||||
},
|
||||
.spd[3] = {
|
||||
.read_type = READ_SMBUS,
|
||||
.spd_spec = {.spd_smbus_address = 0xa6},
|
||||
},
|
||||
|
||||
/*
|
||||
* For each channel, there are 3 sets of DQ byte mappings,
|
||||
* where each set has a package 0 and a package 1 value (package 0
|
||||
* represents the first 64-bit lpddr4 chip combination, and package 1
|
||||
* represents the second 64-bit lpddr4 chip combination).
|
||||
* The first three sets are for CLK, CMD, and CTL.
|
||||
* The fsp package actually expects 6 sets, but the last 3 sets are
|
||||
* not used in CNL, so we only define the three sets that are used
|
||||
* and let the meminit_lpddr4() routine take care of clearing the
|
||||
* unused fields for the caller.
|
||||
*/
|
||||
.dq_map[DDR_CH0] = {
|
||||
{0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0},
|
||||
//{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
|
||||
},
|
||||
.dq_map[DDR_CH1] = {
|
||||
{0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC},
|
||||
//{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00}
|
||||
},
|
||||
|
||||
/*
|
||||
* DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a
|
||||
* mapping of a dq bit on the CPU to the bit it's connected to on
|
||||
* the memory part. The array index represents the dqs bit number
|
||||
* on the memory part, and the values in the array represent which
|
||||
* pin on the CPU that DRAM pin connects to.
|
||||
*/
|
||||
.dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7},
|
||||
.dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7},
|
||||
|
||||
/*
|
||||
* Rcomp resistor values. These values represent the resistance in
|
||||
* ohms of the three rcomp resistors attached to the DDR_COMP_0,
|
||||
* DDR_COMP_1, and DDR_COMP_2 pins on the DRAM.
|
||||
*/
|
||||
.rcomp_resistor = { 121, 75, 100 },
|
||||
|
||||
/*
|
||||
* Rcomp target values. These will typically be the following
|
||||
* values for Cannon Lake : { 80, 40, 40, 40, 30 }
|
||||
*/
|
||||
.rcomp_targets = { 50, 26, 20, 20, 26 },
|
||||
|
||||
/*
|
||||
* Indicates whether memory is interleaved.
|
||||
* Set to 1 for an interleaved design,
|
||||
* set to 0 for non-interleaved design.
|
||||
*/
|
||||
.dq_pins_interleaved = 1,
|
||||
|
||||
/*
|
||||
* VREF_CA configuration.
|
||||
* Set to 0 VREF_CA goes to both CH_A and CH_B,
|
||||
* set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B,
|
||||
* set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B.
|
||||
*/
|
||||
.vref_ca_config = 2,
|
||||
|
||||
/* Early Command Training */
|
||||
.ect = 0,
|
||||
};
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *memupd) {
|
||||
// Allow memory clocks higher than 2933 MHz
|
||||
memupd->FspmConfig.SaOcSupport = 1;
|
||||
// Set primary display to PCIe graphics
|
||||
memupd->FspmConfig.PrimaryDisplay = 1;
|
||||
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
|
||||
}
|
||||
971
src/mainboard/system76/bonw14/tas5825m-normal.c
Normal file
971
src/mainboard/system76/bonw14/tas5825m-normal.c
Normal file
@@ -0,0 +1,971 @@
|
||||
static int tas5825m_setup_normal(struct device * dev) {
|
||||
int res = 0;
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x03, 0x02);
|
||||
amp_write_at(0x01, 0x11);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x46, 0x11);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
{
|
||||
amp_write_at(0x02, 0x00);
|
||||
amp_write_at(0x53, 0x00);
|
||||
amp_write_at(0x54, 0x00);
|
||||
amp_write_at(0x29, 0x7C);
|
||||
amp_write_at(0x03, 0x02);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
{
|
||||
amp_write_at(0x29, 0x00);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x03, 0x12);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x48, 0x0C);
|
||||
}
|
||||
|
||||
amp_set_book(0x64);
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00,
|
||||
0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
|
||||
0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
|
||||
0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00,
|
||||
0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84,
|
||||
0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02,
|
||||
0x60, 0x00, 0x01
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x02);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
|
||||
0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
|
||||
0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
|
||||
0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31,
|
||||
0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31,
|
||||
0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80,
|
||||
0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F,
|
||||
0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68,
|
||||
0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B,
|
||||
0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0,
|
||||
0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E,
|
||||
0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0,
|
||||
0x1C, 0x11, 0xAB
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x03);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
|
||||
0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
|
||||
0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
|
||||
0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26,
|
||||
0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40,
|
||||
0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11,
|
||||
0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F,
|
||||
0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27,
|
||||
0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82,
|
||||
0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0,
|
||||
0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0,
|
||||
0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0,
|
||||
0x1C, 0x51, 0xBB
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x04);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
|
||||
0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
|
||||
0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98,
|
||||
0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30,
|
||||
0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26,
|
||||
0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2,
|
||||
0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00,
|
||||
0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2,
|
||||
0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0,
|
||||
0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0,
|
||||
0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80,
|
||||
0x27, 0x80, 0xEA
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x05);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
|
||||
0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
|
||||
0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
|
||||
0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00,
|
||||
0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06,
|
||||
0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51,
|
||||
0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0,
|
||||
0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2,
|
||||
0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00,
|
||||
0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE,
|
||||
0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88,
|
||||
0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86,
|
||||
0xC1, 0x01, 0x9D
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x06);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
|
||||
0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
|
||||
0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03,
|
||||
0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04,
|
||||
0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26,
|
||||
0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60,
|
||||
0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80,
|
||||
0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82,
|
||||
0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0,
|
||||
0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86,
|
||||
0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84,
|
||||
0x82, 0x04, 0x07
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x07);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
|
||||
0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
|
||||
0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
|
||||
0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04,
|
||||
0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03,
|
||||
0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00,
|
||||
0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57,
|
||||
0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82,
|
||||
0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C,
|
||||
0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80,
|
||||
0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4,
|
||||
0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4,
|
||||
0x1F, 0x31, 0xA8
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x08);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
|
||||
0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
|
||||
0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
|
||||
0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04,
|
||||
0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71,
|
||||
0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71,
|
||||
0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B,
|
||||
0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00,
|
||||
0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44,
|
||||
0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0,
|
||||
0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0,
|
||||
0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86,
|
||||
0xA1, 0x01, 0xC6
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x09);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
|
||||
0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
|
||||
0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
|
||||
0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11,
|
||||
0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11,
|
||||
0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80,
|
||||
0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81,
|
||||
0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44,
|
||||
0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43,
|
||||
0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84,
|
||||
0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80,
|
||||
0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84,
|
||||
0xC3, 0x03, 0x5F
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0A);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
|
||||
0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
|
||||
0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
|
||||
0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03,
|
||||
0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00,
|
||||
0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98,
|
||||
0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51,
|
||||
0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40,
|
||||
0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00,
|
||||
0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0,
|
||||
0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02,
|
||||
0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84,
|
||||
0xD0, 0x04, 0x09
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0B);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
|
||||
0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
|
||||
0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
|
||||
0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00,
|
||||
0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01,
|
||||
0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01,
|
||||
0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68,
|
||||
0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78,
|
||||
0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84,
|
||||
0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08,
|
||||
0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08,
|
||||
0x60, 0x06, 0x12
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0C);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
|
||||
0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
|
||||
0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
|
||||
0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04,
|
||||
0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00,
|
||||
0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11,
|
||||
0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3,
|
||||
0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82,
|
||||
0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81,
|
||||
0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00,
|
||||
0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F,
|
||||
0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84,
|
||||
0xC2, 0x04, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0D);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
|
||||
0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
|
||||
0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00,
|
||||
0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20,
|
||||
0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D,
|
||||
0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10,
|
||||
0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA,
|
||||
0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0,
|
||||
0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x18);
|
||||
{
|
||||
amp_write_block_at(0x30, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1B);
|
||||
{
|
||||
amp_write_block_at(0x6C, {
|
||||
0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
|
||||
0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x1C, {
|
||||
0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x3C, {
|
||||
0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x54, {
|
||||
0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
|
||||
0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x74, {
|
||||
0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x1D);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1D);
|
||||
{
|
||||
amp_write_block_at(0x1C, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1D);
|
||||
{
|
||||
amp_write_block_at(0x3C, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x5B, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x7A, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x0C, {
|
||||
0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x24, {
|
||||
0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
|
||||
0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x44, {
|
||||
0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x8C);
|
||||
|
||||
amp_set_page(0x0E);
|
||||
{
|
||||
amp_write_block_at(0x5C, {
|
||||
0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
|
||||
0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
|
||||
0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
|
||||
0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8
|
||||
});
|
||||
amp_write_block_at(0x7B, {
|
||||
0xC1, 0xF8, 0x59, 0x7F, 0x63
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0F);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
|
||||
0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05,
|
||||
0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF,
|
||||
0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F,
|
||||
0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB,
|
||||
0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8,
|
||||
0xBB, 0x98, 0xC8
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x10);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
|
||||
0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
|
||||
0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x40, 0x00);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_block_at(0x7D, {
|
||||
0x11, 0xFF
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_at(0x51, 0x05);
|
||||
}
|
||||
|
||||
amp_set_page(0x02);
|
||||
{
|
||||
amp_write_at(0x19, 0xDF);
|
||||
}
|
||||
|
||||
amp_set_book(0x8C);
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_block_at(0x2C, {
|
||||
0x00, 0x71, 0x94, 0x9A
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0A);
|
||||
{
|
||||
amp_write_block_at(0x64, {
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0B);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x0C, 0xCC, 0xCD,
|
||||
0x00, 0x0C, 0xCC, 0xCD, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x28, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0E);
|
||||
{
|
||||
amp_write_block_at(0x5C, {
|
||||
0x00, 0x03, 0x69, 0xC5, 0x00, 0xA9, 0x15, 0xB8,
|
||||
0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0F);
|
||||
{
|
||||
amp_write_block_at(0x5C, {
|
||||
0x7F, 0xF9, 0x2C, 0x60, 0x01, 0x33, 0x51, 0x50,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x07);
|
||||
{
|
||||
amp_write_block_at(0x64, {
|
||||
0x00, 0x80, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x6C, {
|
||||
0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0xAA);
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_block_at(0x30, {
|
||||
0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85,
|
||||
0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E,
|
||||
0xF8, 0x5C, 0x9F, 0x28, 0x07, 0xD1, 0x27, 0x3E,
|
||||
0xF0, 0x5D, 0xB1, 0x85, 0x07, 0xD1, 0x27
|
||||
});
|
||||
amp_write_block_at(0x4F, {
|
||||
0x3E, 0x0F, 0xA1, 0x3C, 0x1E, 0xF8, 0x5C, 0x9F,
|
||||
0x28, 0x08, 0x00, 0x00, 0x00, 0xF0, 0x71, 0x4C,
|
||||
0x87, 0x07, 0x91, 0xC6, 0x22, 0x0F, 0x8E, 0xB3,
|
||||
0x79, 0xF8, 0x6E, 0x39, 0xDE, 0x08, 0x00
|
||||
});
|
||||
amp_write_block_at(0x6E, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x02);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7, 0x0B,
|
||||
0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08, 0xF5,
|
||||
0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58, 0xFE, 0x57,
|
||||
0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4, 0x51
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x2E, 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2, 0xB0,
|
||||
0x7B, 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE, 0x92,
|
||||
0xE5, 0xFE, 0xEA, 0x2A, 0xF4, 0x05, 0x41, 0x6D,
|
||||
0x1B, 0xFE, 0x8A, 0x4B, 0xFE, 0x09, 0x6F
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x71, 0xB3, 0xF4, 0xC9, 0x2E, 0xBA, 0x02, 0xE0,
|
||||
0x4E, 0xFB, 0x0B, 0x36, 0xD1, 0x46, 0xFB, 0xB0,
|
||||
0x3F, 0x52, 0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50,
|
||||
0x29, 0xD7, 0x05, 0x3A, 0xF8, 0x0F, 0x0C
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xAF, 0xD6, 0x29, 0xFB, 0x3E, 0x46, 0x00, 0x08,
|
||||
0x17, 0x5D, 0x4C, 0xF0, 0xBC, 0xDB, 0x13, 0x07,
|
||||
0x34, 0x29, 0xCB, 0x0F, 0x43, 0x24, 0xED, 0xF8,
|
||||
0xB4, 0x78, 0xEA
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x03);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x07, 0xFC, 0xDB, 0x0F, 0xF0, 0x3A, 0xC4, 0xBE,
|
||||
0x07, 0xC9, 0x51, 0x50, 0x0F, 0xC5, 0x3B, 0x42,
|
||||
0xF8, 0x39, 0xD3, 0xA1, 0x07, 0xFC, 0x38, 0xBF,
|
||||
0xF0, 0x47, 0x14, 0xF2, 0x07, 0xBE, 0x4A
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x80, 0x0F, 0xB8, 0xEB, 0x0E, 0xF8, 0x45, 0x7C,
|
||||
0xC1, 0x07, 0xEB, 0xF6, 0xEF, 0xF1, 0x08, 0x7E,
|
||||
0x56, 0x07, 0x17, 0x63, 0xC3, 0x0E, 0xF7, 0x81,
|
||||
0xAA, 0xF8, 0xFC, 0xA5, 0x4E, 0x08, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07,
|
||||
0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85, 0x07,
|
||||
0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E, 0xF8,
|
||||
0x5C, 0x9F, 0x28
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x04);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x07, 0xD1, 0x27, 0x3E, 0xF0, 0x5D, 0xB1, 0x85,
|
||||
0x07, 0xD1, 0x27, 0x3E, 0x0F, 0xA1, 0x3C, 0x1E,
|
||||
0xF8, 0x5C, 0x9F, 0x28, 0x08, 0x00, 0x00, 0x00,
|
||||
0xF0, 0x71, 0x4C, 0x87, 0x07, 0x91, 0xC6
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x22, 0x0F, 0x8E, 0xB3, 0x79, 0xF8, 0x6E, 0x39,
|
||||
0xDE, 0x08, 0x21, 0xA6, 0xC8, 0xF0, 0xA9, 0xF7,
|
||||
0x0B, 0x07, 0x3B, 0x34, 0x61, 0x0F, 0x56, 0x08,
|
||||
0xF5, 0xF8, 0xA3, 0x24, 0xD7, 0x08, 0x58
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0xFE, 0x57, 0xF8, 0xB7, 0x23, 0xC8, 0x01, 0xF4,
|
||||
0x51, 0x2E, 0x07, 0x48, 0xDC, 0x38, 0xFD, 0xB2,
|
||||
0xB0, 0x7B, 0x0A, 0x8B, 0x89, 0x0F, 0xFA, 0xBE,
|
||||
0x92, 0xE5, 0xFE, 0xEA, 0x2A, 0xF4, 0x05
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x41, 0x6D, 0x1B, 0xFE, 0x8A, 0x4B, 0xFE, 0x09,
|
||||
0x6F, 0x71, 0xB3, 0xF4, 0xC9, 0x2E, 0xBA, 0x02,
|
||||
0xE0, 0x4E, 0xFB, 0x0B, 0x36, 0xD1, 0x46, 0xFB,
|
||||
0xB0, 0x3F, 0x52
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x05);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x07, 0x86, 0xC1, 0xF0, 0xF3, 0x50, 0x29, 0xD7,
|
||||
0x05, 0x3A, 0xF8, 0x0F, 0x0C, 0xAF, 0xD6, 0x29,
|
||||
0xFB, 0x3E, 0x46, 0x00, 0x08, 0x17, 0x5D, 0x4C,
|
||||
0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x34, 0x29
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xCB, 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78,
|
||||
0xEA, 0x07, 0xFB, 0x25, 0x84, 0xF0, 0x49, 0xA3,
|
||||
0xCE, 0x07, 0xC7, 0xA6, 0xCB, 0x0F, 0xB6, 0x5C,
|
||||
0x32, 0xF8, 0x3D, 0x33, 0xB1, 0x08, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x06);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0E);
|
||||
{
|
||||
amp_write_block_at(0x6C, {
|
||||
0x00, 0x86, 0x43, 0x99, 0xFF, 0x02, 0xE6, 0x50,
|
||||
0x00, 0x77, 0xAC, 0xFD, 0x0F, 0xD7, 0xE6, 0xBF,
|
||||
0xF8, 0x27, 0x42, 0x5B
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0F);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81,
|
||||
0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x81, 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB,
|
||||
0xA1, 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18,
|
||||
0x9F, 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A,
|
||||
0x64, 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A,
|
||||
0x71, 0xC7
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x30, 0x00);
|
||||
amp_write_at(0x60, 0x02);
|
||||
amp_write_at(0x62, 0x09);
|
||||
amp_write_at(0x4C, 0x30);
|
||||
amp_write_at(0x03, 0x03);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x78, 0x80);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x60, 0x00);
|
||||
amp_write_at(0x64, 0x02);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x4E, 0xBB);
|
||||
amp_write_at(0x4F, 0xB0);
|
||||
amp_write_at(0x03, 0x03);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x78, 0x80);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
971
src/mainboard/system76/bonw14/tas5825m-sub.c
Normal file
971
src/mainboard/system76/bonw14/tas5825m-sub.c
Normal file
@@ -0,0 +1,971 @@
|
||||
static int tas5825m_setup_sub(struct device * dev) {
|
||||
int res = 0;
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x03, 0x02);
|
||||
amp_write_at(0x01, 0x11);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x46, 0x11);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
{
|
||||
amp_write_at(0x02, 0x04);
|
||||
amp_write_at(0x53, 0x00);
|
||||
amp_write_at(0x54, 0x00);
|
||||
amp_write_at(0x29, 0x7C);
|
||||
amp_write_at(0x03, 0x02);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
{
|
||||
amp_write_at(0x29, 0x00);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x03, 0x12);
|
||||
}
|
||||
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
amp_set_page(0x00);
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x48, 0x0C);
|
||||
}
|
||||
|
||||
amp_set_book(0x64);
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00,
|
||||
0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
|
||||
0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00,
|
||||
0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xFC, 0x00, 0x00, 0x00, 0x82, 0x00, 0x93, 0x00,
|
||||
0xFC, 0x00, 0x00, 0x8F, 0x00, 0xFF, 0xEF, 0x84,
|
||||
0x49, 0x03, 0x27, 0x84, 0x02, 0x04, 0x06, 0x02,
|
||||
0x60, 0x00, 0x01
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x02);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05,
|
||||
0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D,
|
||||
0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F,
|
||||
0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x01, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31,
|
||||
0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31,
|
||||
0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80,
|
||||
0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F,
|
||||
0x31, 0xA8, 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68,
|
||||
0xF1, 0xC3, 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B,
|
||||
0x03, 0x27, 0x02, 0x70, 0x00, 0x04, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x41, 0x03, 0x37, 0x80, 0x07, 0x00, 0x80, 0xE0,
|
||||
0x00, 0x11, 0xA9, 0x84, 0x82, 0x00, 0xE0, 0x8E,
|
||||
0xFC, 0x04, 0x10, 0xF0, 0x1C, 0x11, 0xAA, 0xF0,
|
||||
0x1C, 0x11, 0xAB
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x03);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD,
|
||||
0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8,
|
||||
0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37,
|
||||
0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x20, 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26,
|
||||
0x30, 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40,
|
||||
0xE0, 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11,
|
||||
0xB3, 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x51, 0xB5, 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F,
|
||||
0x51, 0xB7, 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27,
|
||||
0x80, 0xEA, 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82,
|
||||
0x04, 0x05, 0x84, 0x51, 0x03, 0x75, 0xE2
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x6B, 0xC0, 0x00, 0x80, 0x07, 0x00, 0x80, 0xE0,
|
||||
0x80, 0x31, 0xB8, 0x84, 0x82, 0x40, 0xE0, 0xF0,
|
||||
0x1C, 0x51, 0xB9, 0xF0, 0x1C, 0x51, 0xBA, 0xF0,
|
||||
0x1C, 0x51, 0xBB
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x04);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5,
|
||||
0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F,
|
||||
0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x20, 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98,
|
||||
0x4A, 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30,
|
||||
0x48, 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26,
|
||||
0x32, 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2,
|
||||
0x40, 0xE0, 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00,
|
||||
0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2,
|
||||
0x00, 0x02, 0x08, 0x60, 0x06, 0x12, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xD3, 0x03, 0x4F, 0xF0, 0x1C, 0x51, 0xBE, 0xF0,
|
||||
0x1C, 0x51, 0xBF, 0xF0, 0x1C, 0x51, 0xC0, 0xF0,
|
||||
0x1F, 0x51, 0xC1, 0x84, 0xA1, 0x03, 0x65, 0x80,
|
||||
0x27, 0x80, 0xEA
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x05);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83,
|
||||
0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68,
|
||||
0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33,
|
||||
0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00,
|
||||
0x7F, 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06,
|
||||
0x11, 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51,
|
||||
0xC4, 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0,
|
||||
0x04, 0x01, 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2,
|
||||
0x50, 0x01, 0x84, 0x53, 0x03, 0x25, 0x80, 0x00,
|
||||
0xC4, 0x04, 0x8F, 0x30, 0x00, 0x00, 0x88
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x67, 0x03, 0x00, 0xE4, 0x00, 0x11, 0x9B, 0xEE,
|
||||
0x64, 0x60, 0x00, 0x02, 0xD3, 0x00, 0x10, 0x88,
|
||||
0x47, 0x00, 0x80, 0x10, 0x00, 0x18, 0x02, 0x86,
|
||||
0xC1, 0x01, 0x9D
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x06);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E,
|
||||
0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C,
|
||||
0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x04, 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03,
|
||||
0x67, 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04,
|
||||
0x02, 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26,
|
||||
0x30, 0x02, 0x78, 0x00, 0x03, 0x02, 0x68
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x02, 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60,
|
||||
0x06, 0x12, 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80,
|
||||
0x71, 0xA9, 0x02, 0x28, 0x03, 0x55, 0x84, 0x82,
|
||||
0x00, 0xE0, 0x84, 0x2A, 0x04, 0x00, 0xF0
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, 0xF0,
|
||||
0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, 0x86,
|
||||
0xA1, 0x01, 0xAE, 0x80, 0x27, 0x80, 0xE8, 0x84,
|
||||
0x82, 0x04, 0x07
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x07);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0,
|
||||
0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF,
|
||||
0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1,
|
||||
0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x05, 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04,
|
||||
0x08, 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03,
|
||||
0x6D, 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00,
|
||||
0x82, 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x12, 0xBC, 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57,
|
||||
0xA0, 0x00, 0x84, 0x82, 0x04, 0x09, 0x84, 0x82,
|
||||
0x20, 0xE0, 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C,
|
||||
0x31, 0xA1, 0xF0, 0x1C, 0x31, 0xA2, 0xF0
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x1F, 0x31, 0xA3, 0xE4, 0x00, 0x11, 0xA6, 0x80,
|
||||
0x27, 0x80, 0xE1, 0xF4, 0x00, 0x11, 0xA4, 0xF4,
|
||||
0x1D, 0x31, 0xA5, 0xF4, 0x1C, 0x31, 0xA7, 0xF4,
|
||||
0x1F, 0x31, 0xA8
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x08);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3,
|
||||
0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F,
|
||||
0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D,
|
||||
0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xA9, 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04,
|
||||
0x10, 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71,
|
||||
0xAB, 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71,
|
||||
0xAD, 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x80, 0xEB, 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B,
|
||||
0x03, 0x3D, 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00,
|
||||
0x10, 0x20, 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44,
|
||||
0x26, 0x30, 0x84, 0xC3, 0x03, 0x57, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xC2, 0x60, 0xE0, 0xE0, 0x10, 0x11, 0xB3, 0xF0,
|
||||
0x1C, 0x71, 0xB4, 0xF0, 0x1C, 0x71, 0xB5, 0xF0,
|
||||
0x1C, 0x71, 0xB6, 0xF0, 0x1F, 0x71, 0xB7, 0x86,
|
||||
0xA1, 0x01, 0xC6
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x09);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F,
|
||||
0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76,
|
||||
0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80,
|
||||
0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xE0, 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11,
|
||||
0xBA, 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11,
|
||||
0xBC, 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80,
|
||||
0xE8, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x81, 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81,
|
||||
0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, 0x08, 0x44,
|
||||
0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43,
|
||||
0x03, 0x76, 0x08, 0x00, 0x30, 0x48, 0x02
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, 0x84,
|
||||
0x41, 0x03, 0x46, 0xE4, 0x10, 0x40, 0x00, 0x80,
|
||||
0x40, 0xC0, 0x82, 0x84, 0xC2, 0x00, 0xE0, 0x84,
|
||||
0xC3, 0x03, 0x5F
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0A);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD,
|
||||
0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12,
|
||||
0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE,
|
||||
0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xC0, 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03,
|
||||
0x66, 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00,
|
||||
0x00, 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98,
|
||||
0x6B, 0x08, 0x00, 0x30, 0x68, 0x84, 0x43
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x03, 0x46, 0x08, 0x60, 0x26, 0x33, 0x84, 0x51,
|
||||
0x03, 0x26, 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40,
|
||||
0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00,
|
||||
0x50, 0x28, 0x08, 0x60, 0x06, 0x11, 0x8C
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xFF, 0x03, 0x24, 0x84, 0xCB, 0x03, 0x66, 0xE0,
|
||||
0x10, 0x51, 0xC4, 0x84, 0x80, 0x41, 0x00, 0x02,
|
||||
0xA3, 0x00, 0x10, 0xE4, 0x00, 0x00, 0x00, 0x84,
|
||||
0xD0, 0x04, 0x09
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0B);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01,
|
||||
0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C,
|
||||
0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00,
|
||||
0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00,
|
||||
0x80, 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01,
|
||||
0x9D, 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01,
|
||||
0x9E, 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x01, 0x9C, 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC,
|
||||
0x00, 0x00, 0x02, 0x70, 0x00, 0x04, 0x02, 0x68,
|
||||
0x00, 0x01, 0x02, 0x60, 0x00, 0x03, 0x02, 0x78,
|
||||
0x00, 0x02, 0x84, 0x49, 0x03, 0x6E, 0x84
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x41, 0x03, 0x6F, 0x84, 0xC8, 0x04, 0x10, 0x84,
|
||||
0xC0, 0x04, 0x0A, 0x04, 0x81, 0x91, 0x20, 0x08,
|
||||
0x60, 0x26, 0x30, 0x0D, 0x00, 0x10, 0x10, 0x08,
|
||||
0x60, 0x06, 0x12
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0C);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9,
|
||||
0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA,
|
||||
0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC,
|
||||
0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xAE, 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04,
|
||||
0x0E, 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00,
|
||||
0xE8, 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11,
|
||||
0xAF, 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x11, 0xB1, 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3,
|
||||
0x00, 0x1A, 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82,
|
||||
0x04, 0x0F, 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81,
|
||||
0xE0, 0x80, 0x84, 0x43, 0x03, 0x6F, 0x80
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x07, 0x12, 0xBD, 0x02, 0xC0, 0x00, 0x00, 0x00,
|
||||
0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x11, 0x8F,
|
||||
0x00, 0xFF, 0xFF, 0x84, 0x58, 0x04, 0x01, 0x84,
|
||||
0xC2, 0x04, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0D);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00,
|
||||
0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00,
|
||||
0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82,
|
||||
0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x50, 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00,
|
||||
0x00, 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20,
|
||||
0x00, 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D,
|
||||
0x1E, 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x26, 0x33, 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10,
|
||||
0x40, 0x83, 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA,
|
||||
0x61, 0x00, 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0,
|
||||
0x2C, 0x09, 0x84, 0xCA, 0x21, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xFC, 0x50, 0x00, 0x8F, 0x00, 0x00, 0x01
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x18);
|
||||
{
|
||||
amp_write_block_at(0x30, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1B);
|
||||
{
|
||||
amp_write_block_at(0x6C, {
|
||||
0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00,
|
||||
0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x1C, {
|
||||
0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x3C, {
|
||||
0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x54, {
|
||||
0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48,
|
||||
0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1C);
|
||||
{
|
||||
amp_write_block_at(0x74, {
|
||||
0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x1D);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1D);
|
||||
{
|
||||
amp_write_block_at(0x1C, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1D);
|
||||
{
|
||||
amp_write_block_at(0x3C, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x5B, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x7A, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x0C, {
|
||||
0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x24, {
|
||||
0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78,
|
||||
0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0xFD, {
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x78);
|
||||
|
||||
amp_set_page(0x1E);
|
||||
{
|
||||
amp_write_block_at(0x44, {
|
||||
0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x8C);
|
||||
|
||||
amp_set_page(0x0E);
|
||||
{
|
||||
amp_write_block_at(0x5C, {
|
||||
0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF,
|
||||
0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C,
|
||||
0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7,
|
||||
0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8
|
||||
});
|
||||
amp_write_block_at(0x7B, {
|
||||
0xC1, 0xF8, 0x59, 0x7F, 0x63
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0F);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9,
|
||||
0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xE9, 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05,
|
||||
0x54, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF,
|
||||
0x48, 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F,
|
||||
0x76, 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB,
|
||||
0x98, 0xC8, 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x04, 0x81, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x0F, 0x3F, 0xE5, 0xC9, 0xF8,
|
||||
0xBB, 0x98, 0xC8
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x10);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5,
|
||||
0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27,
|
||||
0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x40, 0x00);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_block_at(0x7D, {
|
||||
0x11, 0xFF
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_at(0x51, 0x05);
|
||||
}
|
||||
|
||||
amp_set_page(0x02);
|
||||
{
|
||||
amp_write_at(0x19, 0xDF);
|
||||
}
|
||||
|
||||
amp_set_book(0x8C);
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_block_at(0x2C, {
|
||||
0x00, 0x71, 0x94, 0x9A
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0A);
|
||||
{
|
||||
amp_write_block_at(0x64, {
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0B);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x1E, 0x5A, 0x84,
|
||||
0x00, 0x1E, 0x5A, 0x84, 0x00, 0x40, 0x26, 0xE7,
|
||||
0x00, 0x40, 0x26, 0xE7, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x28, {
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0E);
|
||||
{
|
||||
amp_write_block_at(0x5C, {
|
||||
0x00, 0x03, 0x69, 0xC5, 0x00, 0xEB, 0x8F, 0xA8,
|
||||
0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0F);
|
||||
{
|
||||
amp_write_block_at(0x5C, {
|
||||
0x7F, 0xF9, 0x2C, 0x60, 0x01, 0xEB, 0x55, 0xAC,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x07);
|
||||
{
|
||||
amp_write_block_at(0x64, {
|
||||
0x00, 0x80, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x6C, {
|
||||
0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
|
||||
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0xAA);
|
||||
|
||||
amp_set_page(0x01);
|
||||
{
|
||||
amp_write_block_at(0x30, {
|
||||
0x00, 0x01, 0x0A, 0x7A, 0x00, 0x02, 0x14, 0xF5,
|
||||
0x00, 0x01, 0x0A, 0x7A, 0x0F, 0x7B, 0xDB, 0x58,
|
||||
0xF8, 0x7F, 0xFA, 0xBE, 0x00, 0x01, 0x0A, 0x7A,
|
||||
0x00, 0x02, 0x14, 0xF5, 0x00, 0x01, 0x0A
|
||||
});
|
||||
amp_write_block_at(0x4F, {
|
||||
0x7A, 0x0F, 0x7B, 0xDB, 0x58, 0xF8, 0x7F, 0xFA,
|
||||
0xBE, 0x07, 0xFD, 0xF9, 0x62, 0xF0, 0x25, 0x7A,
|
||||
0x1B, 0x07, 0xDC, 0xC4, 0xC6, 0x0F, 0xDA, 0x85,
|
||||
0xE5, 0xF8, 0x25, 0x41, 0xD8, 0x08, 0x00
|
||||
});
|
||||
amp_write_block_at(0x6E, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x02);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x07, 0xF7, 0xFF, 0xB5, 0xF0, 0x4F, 0x8C, 0x33,
|
||||
0x07, 0xBA, 0x32, 0x37, 0x0F, 0xB0, 0x73, 0xCD,
|
||||
0xF8, 0x4D, 0xCE, 0x15, 0x07, 0xFA, 0x6B, 0x45,
|
||||
0xF0, 0x68, 0xC7, 0x1B, 0x07, 0x9E, 0xF0
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xFB, 0x0F, 0x97, 0x38, 0xE5, 0xF8, 0x66, 0xA3,
|
||||
0xC0, 0x07, 0xFE, 0x8C, 0x9C, 0xF0, 0x34, 0xCF,
|
||||
0xDE, 0x07, 0xCD, 0x94, 0xFF, 0x0F, 0xCB, 0x30,
|
||||
0x22, 0xF8, 0x33, 0xDE, 0x65, 0x07, 0xFE
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x73, 0xDB, 0xF0, 0x38, 0x93, 0x60, 0x07, 0xCA,
|
||||
0x38, 0xAE, 0x0F, 0xC7, 0x6C, 0xA0, 0xF8, 0x37,
|
||||
0x53, 0x77, 0x07, 0xF8, 0xC1, 0xBE, 0xF0, 0x88,
|
||||
0xCB, 0x7D, 0x07, 0x82, 0x08, 0xA9, 0x0F
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x77, 0x34, 0x83, 0xF8, 0x85, 0x35, 0x99, 0x08,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x03);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4,
|
||||
0xF0, 0x22, 0x72, 0x97, 0x07, 0xEE, 0xC6
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xB4, 0x0F, 0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C,
|
||||
0xCB, 0x07, 0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67,
|
||||
0xAD, 0x07, 0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98,
|
||||
0x53, 0xF8, 0x33, 0xBE, 0x30, 0x08, 0x13
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C, 0x07, 0xDE,
|
||||
0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85, 0xF8, 0x0E,
|
||||
0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x04);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x05);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x07, 0xEE, 0xC6, 0xB4, 0xF0, 0x22,
|
||||
0x72, 0x97, 0x07, 0xEE, 0xC6, 0xB4, 0x0F
|
||||
});
|
||||
amp_write_block_at(0x65, {
|
||||
0xDD, 0x77, 0x9C, 0xF8, 0x22, 0x5C, 0xCB, 0x07,
|
||||
0xF4, 0x93, 0x76, 0xF0, 0x34, 0x67, 0xAD, 0x07,
|
||||
0xD7, 0xAE, 0x5A, 0x0F, 0xCB, 0x98, 0x53, 0xF8,
|
||||
0x33, 0xBE, 0x30
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x06);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x13, 0x15, 0xCB, 0xF0, 0x0E, 0xB9, 0x1C,
|
||||
0x07, 0xDE, 0xDC, 0x2A, 0x0F, 0xF1, 0x86, 0x85,
|
||||
0xF8, 0x0E, 0x4D, 0xAB, 0x08, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0E);
|
||||
{
|
||||
amp_write_block_at(0x6C, {
|
||||
0x00, 0x85, 0xC0, 0x8D, 0xFF, 0x02, 0x2B, 0x75,
|
||||
0x00, 0x78, 0xBE, 0x6E, 0x0F, 0xE2, 0x46, 0xF6,
|
||||
0xF8, 0x1D, 0x0E, 0x9A
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_page(0x0F);
|
||||
{
|
||||
amp_write_block_at(0x08, {
|
||||
0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFE, 0xAA, 0xC3,
|
||||
0xFF, 0xFD, 0x55, 0x85, 0xFF, 0xFE, 0xAA
|
||||
});
|
||||
amp_write_block_at(0x27, {
|
||||
0xC3, 0x0F, 0x2F, 0x01, 0x62, 0xF8, 0xCB, 0xA9,
|
||||
0xA8, 0x07, 0x98, 0xD5, 0xEF, 0xF0, 0xCE, 0x54,
|
||||
0x23, 0x07, 0x98, 0xD5, 0xEF, 0x0F, 0x2F, 0x01,
|
||||
0x62, 0xF8, 0xCB, 0xA9, 0xA8, 0x00, 0x00
|
||||
});
|
||||
amp_write_block_at(0x46, {
|
||||
0x38, 0xE4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A,
|
||||
0x71, 0xC7
|
||||
});
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x30, 0x00);
|
||||
amp_write_at(0x60, 0x02);
|
||||
amp_write_at(0x62, 0x09);
|
||||
amp_write_at(0x4C, 0x30);
|
||||
amp_write_at(0x03, 0x03);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x78, 0x80);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x60, 0x00);
|
||||
amp_write_at(0x64, 0x02);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x4E, 0xBB);
|
||||
amp_write_at(0x4F, 0xB0);
|
||||
amp_write_at(0x03, 0x03);
|
||||
}
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
{
|
||||
// Page 0
|
||||
|
||||
amp_write_at(0x78, 0x80);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
31
src/mainboard/system76/bonw14/tas5825m.c
Normal file
31
src/mainboard/system76/bonw14/tas5825m.c
Normal file
@@ -0,0 +1,31 @@
|
||||
#include <delay.h>
|
||||
#include <drivers/i2c/tas5825m/tas5825m.h>
|
||||
|
||||
#define R(F) { \
|
||||
res = F; \
|
||||
if (res < 0) return res; \
|
||||
}
|
||||
|
||||
#define amp_write_at(A, V) R(tas5825m_write_at(dev, A, V))
|
||||
|
||||
#define amp_write_block_at(A, ...) { \
|
||||
const uint8_t _values[] = __VA_ARGS__; \
|
||||
R(tas5825m_write_block_at(dev, A, _values, ARRAY_SIZE(_values))); \
|
||||
}
|
||||
|
||||
#define amp_set_page(P) R(tas5825m_set_page(dev, P))
|
||||
|
||||
#define amp_set_book(B) R(tas5825m_set_book(dev, B))
|
||||
|
||||
#include "tas5825m-normal.c"
|
||||
#include "tas5825m-sub.c"
|
||||
|
||||
int tas5825m_setup(struct device * dev, int id) {
|
||||
if (id == 0) {
|
||||
return tas5825m_setup_normal(dev);
|
||||
} else if (id == 1) {
|
||||
return tas5825m_setup_sub(dev);
|
||||
} else {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
@@ -324,6 +324,7 @@ chip soc/intel/cannonlake
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end # tas5825m
|
||||
end # SMBus
|
||||
|
||||
@@ -17,7 +17,7 @@
|
||||
|
||||
#define amp_set_book(B) R(tas5825m_set_book(dev, B))
|
||||
|
||||
int tas5825m_setup(struct device * dev) {
|
||||
int tas5825m_setup(struct device * dev, int id) {
|
||||
int res = 0;
|
||||
|
||||
amp_set_book(0x00);
|
||||
|
||||
Reference in New Issue
Block a user