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src/southbridge: change "unsigned" to "unsigned int"

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Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth
2019-10-23 21:46:03 -06:00
committed by Patrick Georgi
parent 5331a7cff9
commit ff744bf0ee
67 changed files with 256 additions and 256 deletions
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2
src/southbridge/amd/amd8111/acpi.c
View File

@@ -100,7 +100,7 @@ static int lsmbus_block_write(struct device *dev, uint8_t cmd, u8 bytes,
#if CONFIG(HAVE_ACPI_TABLES)
unsigned pm_base;
unsigned int pm_base;
#endif
static void acpi_init(struct device *dev)

8
src/southbridge/amd/amd8111/amd8111.c
View File

@@ -21,15 +21,15 @@ void amd8111_enable(struct device *dev)
{
struct device *lpc_dev;
struct device *bus_dev;
unsigned index;
unsigned reg_old, reg;
unsigned int index;
unsigned int reg_old, reg;
/* See if we are on the bus behind the amd8111 pci bridge */
bus_dev = dev->bus->dev;
if ((bus_dev->vendor == PCI_VENDOR_ID_AMD) &&
(bus_dev->device == PCI_DEVICE_ID_AMD_8111_PCI))
{
unsigned devfn;
unsigned int devfn;
devfn = bus_dev->path.pci.devfn + (1 << 3);
lpc_dev = pcidev_path_behind(bus_dev->bus, devfn);
index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
@@ -37,7 +37,7 @@ void amd8111_enable(struct device *dev)
index = 16;
}
} else {
unsigned devfn;
unsigned int devfn;
devfn = (dev->path.pci.devfn) & ~7;
lpc_dev = pcidev_path_behind(dev->bus, devfn);
index = dev->path.pci.devfn & 7;

2
src/southbridge/amd/amd8111/amd8111.h
View File

@@ -17,6 +17,6 @@
#include <device/device.h>
void amd8111_enable(struct device *dev);
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn);
#endif /* AMD8111_H */

42
src/southbridge/amd/amd8111/amd8111_smbus.h
View File

@@ -29,7 +29,7 @@ static inline void smbus_delay(void)
outb(0x80, 0x80);
}
static int smbus_wait_until_ready(unsigned smbus_io_base)
static int smbus_wait_until_ready(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@@ -48,7 +48,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static int smbus_wait_until_done(unsigned smbus_io_base)
static int smbus_wait_until_done(unsigned int smbus_io_base)
{
unsigned long loops;
loops = SMBUS_TIMEOUT;
@@ -64,10 +64,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device)
static int do_smbus_recv_byte(unsigned int smbus_io_base, unsigned int device)
{
unsigned global_status_register;
unsigned byte;
unsigned int global_status_register;
unsigned int byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -110,10 +110,10 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned int device)
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device,
unsigned value)
static int do_smbus_send_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int value)
{
unsigned global_status_register;
unsigned int global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -153,11 +153,11 @@ static int do_smbus_send_byte(unsigned smbus_io_base, unsigned int device,
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device,
static int do_smbus_read_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int address)
{
unsigned global_status_register;
unsigned byte;
unsigned int global_status_register;
unsigned int byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -200,10 +200,10 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned int device,
return byte;
}
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device,
static int do_smbus_write_byte(unsigned int smbus_io_base, unsigned int device,
unsigned int address, unsigned char val)
{
unsigned global_status_register;
unsigned int global_status_register;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
@@ -239,11 +239,11 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned int device,
return 0;
}
static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device,
unsigned cmd, u8 bytes, u8 *buf)
static int do_smbus_block_read(unsigned int smbus_io_base, unsigned int device,
unsigned int cmd, u8 bytes, u8 *buf)
{
unsigned global_status_register;
unsigned i;
unsigned int global_status_register;
unsigned int i;
u8 msglen;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
@@ -296,11 +296,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned int device,
return i;
}
static int do_smbus_block_write(unsigned smbus_io_base, unsigned int device,
unsigned cmd, u8 bytes, const u8 *buf)
static int do_smbus_block_write(unsigned int smbus_io_base, unsigned int device,
unsigned int cmd, u8 bytes, const u8 *buf)
{
unsigned global_status_register;
unsigned i;
unsigned int global_status_register;
unsigned int i;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
return SMBUS_WAIT_UNTIL_READY_TIMEOUT;

20
src/southbridge/amd/amd8111/early_ctrl.c
View File

@@ -19,7 +19,7 @@
#include <southbridge/amd/common/reset.h>
#include "amd8111.h"
unsigned get_sbdn(unsigned bus)
unsigned int get_sbdn(unsigned int bus)
{
pci_devfn_t dev;
@@ -34,7 +34,7 @@ unsigned get_sbdn(unsigned bus)
}
static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
static void enable_cf9_x(unsigned int sbbusn, unsigned int sbdn)
{
pci_devfn_t dev;
uint8_t byte;
@@ -48,9 +48,9 @@ static void enable_cf9_x(unsigned sbbusn, unsigned sbdn)
static void enable_cf9(void)
{
unsigned sblk = get_sblk();
unsigned sbbusn = get_sbbusn(sblk);
unsigned sbdn = get_sbdn(sbbusn);
unsigned int sblk = get_sblk();
unsigned int sbbusn = get_sbbusn(sblk);
unsigned int sbdn = get_sbdn(sbbusn);
enable_cf9_x(sbbusn, sbdn);
}
@@ -63,7 +63,7 @@ void do_board_reset(void)
outb(0x0e, 0x0cf9); // make sure cf9 is enabled
}
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
void enable_fid_change_on_sb(unsigned int sbbusn, unsigned int sbdn)
{
pci_devfn_t dev;
@@ -76,7 +76,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
}
static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
static void soft_reset_x(unsigned int sbbusn, unsigned int sbdn)
{
pci_devfn_t dev;
@@ -91,9 +91,9 @@ static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
void do_soft_reset(void)
{
unsigned sblk = get_sblk();
unsigned sbbusn = get_sbbusn(sblk);
unsigned sbdn = get_sbdn(sbbusn);
unsigned int sblk = get_sblk();
unsigned int sbbusn = get_sbbusn(sblk);
unsigned int sbdn = get_sbdn(sbbusn);
return soft_reset_x(sbbusn, sbdn);

4
src/southbridge/amd/amd8111/early_smbus.c
View File

@@ -64,13 +64,13 @@ static inline int smbus_write_byte(unsigned int device, unsigned int address,
return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}
static inline int smbus_block_read(unsigned int device, unsigned cmd, u8 bytes,
static inline int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes,
u8 *buf)
{
return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
}
static inline int smbus_block_write(unsigned int device, unsigned cmd, u8 bytes,
static inline int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf)
{
return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);

8
src/southbridge/amd/amd8111/reset.c
View File

@@ -21,7 +21,7 @@
#define PCI_DEV_INVALID (0xffffffffU)
static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
static pci_devfn_t pci_io_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
{
pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
@@ -41,9 +41,9 @@ static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
void do_board_reset(void)
{
pci_devfn_t dev;
unsigned bus;
unsigned node = 0;
unsigned link = get_sblk();
unsigned int bus;
unsigned int node = 0;
unsigned int link = get_sblk();
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.

20
src/southbridge/amd/amd8132/bridge.c
View File

@@ -43,8 +43,8 @@ static void amd8132_walk_children(struct bus *bus,
}
struct amd8132_bus_info {
unsigned sstatus;
unsigned rev;
unsigned int sstatus;
unsigned int rev;
int master_devices;
int max_func;
};
@@ -65,9 +65,9 @@ static void amd8132_count_dev(struct device *dev, void *ptr)
static void amd8132_pcix_tune_dev(struct device *dev, void *ptr)
{
struct amd8132_bus_info *info = ptr;
unsigned cap;
unsigned status, cmd, orig_cmd;
unsigned max_read, max_tran;
unsigned int cap;
unsigned int status, cmd, orig_cmd;
unsigned int max_read, max_tran;
int sibs;
if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
@@ -133,10 +133,10 @@ static void amd8132_pcix_tune_dev(struct device *dev, void *ptr)
}
static void amd8132_scan_bus(struct bus *bus,
unsigned min_devfn, unsigned max_devfn)
unsigned int min_devfn, unsigned int max_devfn)
{
struct amd8132_bus_info info;
unsigned pos;
unsigned int pos;
/* Find the children on the bus */
pci_scan_bus(bus, min_devfn, max_devfn);
@@ -162,7 +162,7 @@ static void amd8132_scan_bus(struct bus *bus,
*/
if (!bus->children)
{
unsigned pcix_misc;
unsigned int pcix_misc;
/* Disable all of my children */
disable_children(bus);
@@ -198,7 +198,7 @@ static void amd8132_pcix_init(struct device *dev)
{
uint32_t dword;
uint8_t byte;
unsigned chip_rev;
unsigned int chip_rev;
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
@@ -368,7 +368,7 @@ static void ioapic_enable(struct device *dev)
static void amd8132_ioapic_init(struct device *dev)
{
uint32_t dword;
unsigned chip_rev;
unsigned int chip_rev;
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);