As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Updated Authors file is in a separate commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia0a07df6ca1fdaa2837ce8839057057cbd44d157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently SPI vendor IDs are magic numbers in spi_flash.c. These definitions
are needed for AMD's fch_spi. So add the definitions to spi_generic.h and use
it at spi_flash.c
BUG=b:136595978
TEST=Build test of several platforms that don't use stoneyridge. Build and boot
grunt (using stoneyridge new fch_spi).
Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Variable length arrays were a feature added in C99 that allows the
length of an array to be determined at runtime. Eg.
int sum(size_t n) {
int arr[n];
...
}
This adds a small amount of runtime overhead, but is also very
dangerous, since it allows use of an unlimited amount of stack memory,
potentially leading to stack overflow. This is only worsened in
coreboot, which often has very little stack space to begin with. Citing
concerns like this, all instances of VLA's were recently removed from the
Linux kernel. In the immortal words of Linus Torvalds [0],
AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and
much _slower_ code (and more fragile code), than just using a fixed
key size would have done. [...] Anyway, some of these are definitely
easy to just fix, and using VLA's is actively bad not just for
security worries, but simply because VLA's are a really horribly bad
idea in general in the kernel.
This patch follows suit and zaps all VLA's in coreboot. Some of the
existing VLA's are accidental ones, and all but one can be replaced with
small fixed-size buffers. The single tricky exception is in the SPI
controller interface, which will require a rewrite of old drivers
to remove [1].
[0] https://lkml.org/lkml/2018/3/7/621
[1] https://ticket.coreboot.org/issues/217
Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch moves SPI_FLASH time-outs from spi/spi_flash_internal.h for
SPI SW-sequencing to include/spi-generic.h to provide also for
SPI HW-sequencing.
tested on siemens/bdx1 and checked if all includes of
spi_flash_internal.h on other places provide an include of
spi-generic.h before
Change-Id: I837f1a027b836996bc42389bdf7dbab7f0e9db09
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds support to read SPI flash in Dual SPI mode, where both
MISO and MOSI lines are used for output mode (specifically Fast Read
Dual Output (0x3b) where the command is still sent normally, not Fast
Read Dual I/O (0xbb) whose additional benefit should be extremely
marginal for our use cases but which would be more complicated to
implement). This feature needs to be supported by both the flash chip
and the controller, so we add a new dual_spi flag (and a new flags field
to hold it) to the spi_flash structure and a new optional xfer_dual()
function pointer to the spi_ctrlr structure. When both are provided,
Dual SPI mode is used automatically, otherwise things work as before.
This patch only adds the dual_spi flag exemplary to all Winbond and
Gigadevice chips, other vendors need to be added as needed.
Change-Id: Ic6808224c99af32b6c5c43054135c8f4c03c1feb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All SPI flash chip drivers currently in coreboot use the generic read
functions (spi_flash_cmd_read_fast()/_slow()) as their read callback.
The only use case for specialized read callbacks we have left is with
specialized flash controllers like Intel fast_spi (which sort of
impersonate the flash chip driver by implementing their own probe
function).
This patch unifies the behavior for all normal flash drivers by making
the read callback optional and letting them all fall back to a default
read implementation that handles normal fast/slow reading. Most of the
drivers used to install the respective callback after checking
CONFIG_SPI_FLASH_NO_FAST_READ, but some hardcoded either slow or fast
writes. I have found no indications for why this is and spot-checked
datasheets for affected vendors to make sure they all support both
commands, so I assume this is just some old inaccuracy rather than
important differences that need preserving. (Please yell if you
disagree.)
Also take the opportunity to refactor some of the common spi_flash.c
code a bit because I felt there are too many nested functions that don't
really do enough on their own, and centralizing stuff a bit should make
it easier to follow the code flow. (Some of this is in preparation for
the next patch.)
Change-Id: I2096a3ce619767b41b1b0c0c2b8e95b2bd90a419
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch changes the Gigadevice SPI flash driver to adopt the same
structure packing improvements for the hardcoded parameters of
individual chips that was implemented for Winbond last year. This cuts
the size of the hardcoded info nearly in half and should save us a few
hundred bytes in every stage.
Change-Id: I9910dcb9b649f51b317f3f8fcba49e5e893f67d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SPI transfer speed logging in cbfs_spi is super useful, doesn't get
in the way (just adding one line per stage, essentially) and should have
no notable overhead. Let's enable it by default for the BIOS_DEBUG log
level rather than having to recompile to get it.
Also fix an issue with building this code on MIPS due to lack of 64-bit
division primitives. (This means MIPS and arm32 board may display
incorrect results when reading more than 4MB in a single transfer, which
sounds very unlikely.)
Change-Id: I03c77938afe01fdcecf917e8c4c25cc29cdc764e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.
Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move Winbond M25PXX command values to spi_winbond.h
file.
The command values will be used for programming SPI
contoller of Intel Braswell, using this include file.
Update winbond.c file with coreboot header.
BUG=N/A
TEST=Facebook FBG-1701 with flashrom
Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Static scan-build indicates a possible invalid return from function
spi_flash_cmd_erase(). The root cause is because the scan believes it's
possible for offset to be above the end address in the first pass, thus
not setting a value for variable ret. Assign initial value of -1 to
variable ret to make checker happy.
BUG=b:112253891
TEST=build grunt
Change-Id: If548728ff90b755c69143eabff6aeff01e8fd483
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/31473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some SPI controllers support both READ and WRITE protection
add a variable to the protect API for the callers to specify
the kind of protection they want (Read/Write/Both).
Also, update the callers and protect API implementation.
BUG=None
BRANCH=None
TEST=test that the mrc cache is protected as expected on soraka.
Also tried if the read protection is applied correctly.
Change-Id: I093884c4768b08a378f21242ac82e430ac013d15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add S25FL208K (ID 0x4014), S25FL132K (ID 0x4016) and S25FL164K (ID 0x4017)
chips in a way similar to S25FL116K (ID 0x4015) chip from the same family.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9bf7197bbc0d12797c8ed100c673628de9c140f7
Reviewed-on: https://review.coreboot.org/c/30874
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Extend the generic flash interface to probe for write protected regions.
Add Winbond custom code to return flash protection.
Tested on Cavium EVB CN81xx using W25Q128.
Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25082
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The device tree now supports 'hidden' and the status can be found in
`struct device.hidden`. A new acpi_device_status() will return the
expected setting of STA from a `struct device`.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28567
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
