Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the
OS driver and ACPI thinking they own the GPIO. This can cause timing
problems because it's not clear which system should be controlling the
GPIO. I'm making this an error because we should really clean these up.
BUG=b:210694108
TEST=Boot guybrush and see error:
> I2C: 02:5d: ERROR: Exposing GPIOs in Power Resource and _CRS
> \_SB.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc42ed81fff295fb168a0b343e96b3a650b1c84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Instead of having callbacks into serial console code to set up the
coreboot table have the coreboot table code call IP specific code to get
serial information. This makes it easier to reuse the information as the
return value can be used in a different context (e.g. when filling in a
FDT).
This also removes boilerplate code to set up lb_console entries by
setting entry based on the type in struct lb_uart.
Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This reverts commit 672bd9bee5.
Reason for revert: Gmeet resolution dropped. When system starts
Gmeet video call, it uses the hardware accelerated encoder as per
the expectation. But, as soon as another system connects to the call,
the immediate fallback observed from hardware to software encoder.
Due to this, Gmeet resolution dropped from 720p to 180p.
Currently, this issue observed on AlderLake-N SoC based fanless
platforms. This issue is not seen on fan based systems.
BUG=b:246535768,b:235254828
BRANCH=None
TEST=Built and tested on Alderlake-N systems. With this revert
Gmeet resolution drop not observed.
Change-Id: Idaeaeaed47be44166a7cba9a0a1fac50d2688e50
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
BRANCH=none
BUG=b:234776154
TEST=build and boot Nirwen UFS, copy ISH firmware to host
file system /lib/firmware/intel/adln_ish.bin
check "dmesg |grep ish", it should show:
ish-loader: ISH firmware intel/adlnrvp_ish.bin loaded
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I89782b0b7dde1fca0130472a38628e72dfd5c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
When system_uuid CBFS file is present and contains the UUID
in a string format, the driver will parse it and convert to binary
format to populate the SMBIOS type 1 UUID field.
TEST=Add UUID file and boot MSI PRO Z690-A DDR4 WIFI and check with
dmidecode if the UUID is populated correctly.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I22f22f4e8742716283d2fcaba4894c06cef3a4bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64639
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On newer systems such as Alder Lake it has been noticed that Intel PTT
control area is not writable until PTT is switched to ready state. The
EDK2 CRB drivers always initialize the command/response buffer address
and size registers before invoking the TPM command. See STEP 2 in
PtpCrbTpmCommand function in
tianocore/edk2/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c
Doing the same in coreboot allowed to perform PTT TPM startup
successfully and measure the components to PCRs in ramstage on an
Alder Lake S platform.
TEST=Enable measured boot and see Intel PTT is started successfully
and no errors occur during PCR extends on MSI PRO Z690-A DDR4 WIFI.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia8e473ecc1a520851d6d48ccad9da35c6f91005d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63957
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
CB:67670 recently changed the format of the MRC metadata header, but
left the signature the same. That kinda defeats the purpose of having a
signature which is to make a data structure recognizable (because now
the same signature can refer to two different structures that cannot be
otherwise distinguished). While we don't know of any use case where
anything other than coreboot currently parses this data structure (other
than a ChromeOS-internal utility that's about to be removed), it's
probably better to still switch to a different signature for the new
header format just to stay on the safe side (e.g. if we ever need to
start parsing this somewhere else in the future).
CB:67670 only landed a week ago so hopefully the old signature + new
format variant hasn't had much time to escape into the wild yet.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic08b23862720db832a08dc4c6818894492f43cc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68012
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Example for Alder Lake PTT:
Handle 0x004C, DMI type 43, 31 bytes
TPM Device
Vendor ID: INTC
Specification Version: 2.0
Firmware Revision: 600.18
Description: Intel iTPM
Characteristics:
TPM Device characteristics not supported
OEM-specific Information: 0x00000000
TEST=Execute dmidecode and see the type 43 is populated with PTT
on MSI PRO Z690-A WIFI DDR4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I05289f98969bd431017aff1aa77be5806d6f1838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
The current IPU ES entry value is always set to true for ADL-N and
kernel picks the ES version of the main IPU FW even for the production
bootloader but loading is not successful due to the authentication
failure.
Alderlake-N silicon has the same CPU id for all the SKU's and
also the production binaries are backward compatible with ES parts.
This change removes the IPU ES support ACPI entry since the
kernel needs to load the production IPU main firmware on both the
ES/QS parts.
BUG=b:248249032
TEST=Verify the Camera functionality by enabling the IPU secure mode
on ADL-N variants with both ES/QS silicon.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I75b222e6f2b1ccdc5b6c448eb60afff3c1da3a8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The current MRC cache update process is slow (28 ms on nissa), because
cbmem is not cached in romstage. Specifically, the new MRC data returned
by the FSP is stored in the FSP reserved memory in cbmem, so operations
on the new data (computing the checksum, comparing to the old data) are
slow.
Replace the data checksum in the MRC header with a hash, and compare
hashes instead of comparing the full data. This has two benefits:
1. The xxhash function is faster than computing an IP checksum (4 ms vs
14 ms on uncached data on nissa).
2. There's no need to memcmp() the full MRC data, which takes 14 ms on
nissa.
Before:
550:starting to load ChromeOS VPD 867,930 (4,664)
3:after RAM initialization 896,020 (28,090)
4:end of romstage 906,274 (10,254)
After:
550:starting to load ChromeOS VPD 864,820 (4,649)
3:after RAM initialization 869,652 (4,831)
4:end of romstage 879,909 (10,257)
BUG=b:242667207
TEST=Check that MRC caching still works as expected on nissa. Corrupt
the MRC cache and check that memory is retrained.
Change-Id: I1b7848d1d05e555b61e0f1cb605550dfe3449c6d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67670
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create Kconfig options and boot state machine callback in ramstage for
an early initialization of the PTN3460 DP-to-LVDS bridge. This allows
showing the bootsplash screen on mainboards utilizing this chip during
the PCI device enumeration.
BUG=none
TEST=Select PTN3460_EARLY_INIT config switch in mainboard Kconfig and
check the log for "Attempting PTN3460 early init" message. If the
board (e.g. siemens/mc_apl7 in this case) is also configured for
showing the bootsplash logo, it should be now visible.
Change-Id: I5424d062b3fb63c78cfced3971376353be11c504
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67681
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since mono_time is now 64-bit, the utility functions interfacing with
mono_time should also be 64-bit so precision isn't lost.
Fixed build errors related to printing the now int64_t result of
stopwatch_duration_[m|u]secs in various places.
BUG=b:237082996
BRANCH=All
TEST=Boot dewatt
Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This reverts commit f83b7d494e.
It turns out we have tests which use `futility validate_rec_mrc` to
validate the MRC cache, which includes verifying the data checksum.
Revert this to allow the tests to pass while we figure out how to fix
this.
BUG=b:245277259, b:242667207
TEST=None
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: Id913d00584444c21cb94668bdc96f4de51af7cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On some platforms the HFSTS4 bit 19 does not indicate active PTT.
Instead of ME HFSTS4, use TXT FTIF register to check active TPM for
the current boot. Discrete TPM shall be deactivated when PTT is
enabled so this always should return true value of PTT state.
Leave the old method for backwards compatibility if TXT FTIF would not
be applicable for older microarchitectures.
Based on DOC #560297.
TEST=Check if PTT is detected as active on MSI PRO Z690-A DDR4 WIFI
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3a55c9f38f5bb94fb1186592446a28e675c1207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Currently, the "loading FSP-S" timestamp is added in fsp_silicon_init().
However, most Intel platforms actually load FSP-S earlier than this, in
soc_fsp_load(). So the timestamp is added in the wrong place.
Add the timestamp in fsps_load() instead, after the load_done early
return so that it will only be added for the first call.
Before:
949:finished CSE firmware sync 961,833 (17,998)
17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495)
18:finished LZ4 decompress (ignore for x86) 1,018,797 (469)
30:device enumeration 1,035,096 (16,298)
971:loading FSP-S 1,048,082 (12,986)
954:calling FspSiliconInit 1,049,331 (1,249)
After:
949:finished CSE firmware sync 959,355 (16,370)
971:loading FSP-S 978,139 (18,784)
17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656)
18:finished LZ4 decompress (ignore for x86) 1,016,271 (475)
30:device enumeration 1,032,567 (16,295)
954:calling FspSiliconInit 1,046,867 (14,300)
BUG=b:239769975
TEST="loading FSP-S" is added in the right place on nivviks (see above).
Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds a driver for a new RTC from Micro Crystal. Supported
features are:
* configure backup voltage switchover via devicetree
* configure backup capacitor charging mode via devicetree
* set date if a voltage drop on backup voltage was detected
to either a user definable (devicetree) or coreboot build date
Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This workaround was added since reading the firmware version on Ti50
versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is
using Ti50 this old anymore, so remove the workaround.
BUG=b:224650720,b:236911319
TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the
firmware version:
[INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c
Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
When MRC_SAVE_HASH_IN_TPM is selected, mrc_data_valid() uses the TPM
hash to verify the MRC cache data, not the checksum. However, we still
calculate the checksum when updating the cache. Skip this calculation
when MRC_SAVE_HASH_IN_TPM is selected to save boot time.
On nissa, this reduces boot time by ~14 ms:
Before:
3:after RAM initialization 854,298 (28,226)
After:
3:after RAM initialization 849,626 (14,463)
Note, the reason the calculation is so slow is that the new MRC data
lives in CBMEM, which is not yet marked as cacheable in romstage.
BUG=b:242667207
TEST=MRC caching still works as expected on nivviks. After clearing
the MRC cache, memory training happens on the next boot, but doesn't on
subsequent boots.
Change-Id: Ifbb75ecfa17421c0565aec1f3eb48d950244f821
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This patch implements EFI_PEI_MP_SERVICES_PPI structure definitions
with APIs that return mp_api_unsupported().
The reason behind this change is to fix an FSP issue where FSP assumes
ownership of the APs (Application Processors) upon passing a `NULL`
pointer to the CpuMpPpi FSP-S UPD.Hence, this patch implements
`MP_SERVICES_PPI_DEFAULT` config to fill EFI_PEI_MP_SERVICES_PPI with
`mp_api_unsupported` APIs.
Later this data structure can be passed to the CpuMpPpi UPD to avoid
APs from getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.
TEST=Able to build and boot Google/Taeko with this patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I31fcaa2aa633071b6d6bfa05dbe891ef87978d2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reading firmware_version register is supported on Ti50 version
0.22.4. Therefore correct the help text of the Kconfig option
TI50_FIRMWARE_VERSION_NOT_SUPPORTED.
Also change the message level to BIOS_WARNING.
BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I66a0ef896c9dc4cd0f586555a55dbcd1cfd863f9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66906
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add GPIO configuration and device tree to enable the chip.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=Patch linux with NXP's pending drivers
UWB device is probed and can respond to a simple hello packet
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move the `offset` parameter into pciexp_find_extended_cap(). If it's
called with `0`, we start a new search. If it's an existing offset,
we continue the search.
This makes it easier to search for multiple occurences of a capa-
bility in a single loop.
Change-Id: I80115372a82523b90460d97f0fd0fa565c3f56cb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add a new driver for NXP UWB SR1xx (e.g., SR150) device.
The driver was originally written by Tim Wawrzynczak as a WIP in
CL:3503703, and was based on drivers/spi/acpi.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=On ghost (with follow-up CL), patch linux with NXP's pending
drivers
-> UWB device is probed and can respond to a simple hello
packet
Co-authored-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I5b1b0a5c1b48d0b09e7ab5f2ea6b6bc2fba2a7d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66466
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot uses TianoCore interchangeably with EDK II, and whilst the
meaning is generally clear, it's not the payload it uses. EDK II is
commonly written as edk2.
coreboot builds edk2 directly from the edk2 repository. Whilst it
can build some components from edk2-platforms, the target is still
edk2.
[1] tianocore.org - "Welcome to TianoCore, the community supporting"
[2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform
firmware development environment for the UEFI and UEFI Platform
Initialization (PI) specifications."
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Recent changes to both coreboot and edk2 means that UefiPayloadPkg
seems to work on all hardware. It has been tested on:
* Intel Core 2nd, 3rd, 4th, 5th, 6th, 8th, 8th, 9th, 10th,
11th and 12th generation processors
* Intel Small Core BYT, BSW, APL, GLK and GLK-R processors
* AMD Stoney Ridge and Picasso
This includes the problematic Lenovo X230s. The most likely fixes are:
* Configuring the PCI Base and Length in edk2
* Fixes to the HostBridgeLib in edk2
* Adjustment to the SD/eMMC initialisation timeout
This means we can now remove the already deprecated option for
CorebootPayloadPkg and the legacy 8254 timer build option.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ice7b7576eb3d32ea46e5138266b7df3fbcdcf7ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
