Some chips (fintek [1,2]) have registers with specific selector-fields
that can affect the address space of the device (for example, switch the
register bank). At the same time, these registers contain fields that
should not change after they are configured in BIOS (for example, set
the port to 2E/2F or 4E/4F). In this case, the selector should take into
account the mask of the register fields and there is no convenient and
easy way to add this in the code in the utility. The selector-fields
should be set manually before the dump and this action is done several
times.
This patch adds an extra-selector mechanism that allows superiotool to
make a correct dump in automatic mode.
Just add a structure with an index, mask, and value for the selector
inside the superio_registers chip for the corresponding LDN to switch
the register bank:
{FINTEK_F81966_DID, "F81962/F81964/F81966/F81967", {
* * *
{NOLDN, "Global",
{0x28,0x2a,0x2b,0x2c,EOT},
{0x00,0x00,0x00,0x00,EOT},
{.idx = 0x27, .mask = 0xd, .val = 0x1} /* update extra selector */
},
{0x03, "LPT",
{0x30,0x60,0x61,0x70,0x74,0xf0,EOT},
{NANA,0x03,0x78,0x07,0x03,0xc2,EOT} /* without extra selector */
},
* * *
Tested with Fintek F81966 on Asrock IMB-1222:
- run superiotool on Ubuntu and dump the registers for the board with
the vendor's firmware;
- add the superio chip initialization code to the board configuration
in coreboot and build the project;
- boot Ubuntu on the board with coreboot and re-dump the registers;
- the register values from the board configuration code are the same
in both dumps.
Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e
(Global) -- ESEL[27h] 0x00 (Port Select Register) --
idx 02 07 20 21 23 24 25 26 27 28 29 2a 2b 2c 2d
val 00 0b 15 02 19 34 5a 23 80 a0 f0 45 02 e3 2e
def NA 00 15 02 19 34 00 23 02 a0 00 00 02 0c 28
* * *
The changes do not affect the configuration of existing chips, which
was tested on the Asrock H110-STX motherboard with Nuvoton NCT5539D
(the dump before and after the changes are the same).
[1] CB:83004
[2] CB:83019
Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83196
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the non-public "ITE IT8659E-I Preliminary Specification V0.7.2
(For H Version)".
TEST=Dump IT8659E configuration on the new Protectli platform
Change-Id: Ic036f8b99d5bd0107be7850fc4509da1bf020fe5
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reformat alternate dump output to show default values before read
values, and to use brackets to visually indicate which values differ
from the defaults.
old output:
Register dump:
idx val def
0x07: 0x0b (0x00)
0x10: 0xff (0xff)
0x11: 0xff (0xff)
...
new output:
Register dump:
idx def val
0x07: 0x00 [0x0b]
0x10: 0xff 0xff
0x11: 0xff 0xff
...
TEST=build/dump registers from Erying SRMJ4 w/Nuvoton NCT6796D.
Change-Id: Idef2cc136151328b114620eb297ab8fd62b71bcd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80004
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Registers and default values taken from public datasheet:
https://www.nuvoton.com/resource-files/NCT6796D_Datasheet_V0_6.pdf
TEST=build/dump SIO registers on Erying SRMJ4 mainboard
Change-Id: I0ff940a17b0c38a5ca66e90dd4e075a2b04dcfc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80003
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fails to build on musl libc as pci/types.h expects "POSIX types", which
are not implemented, instead of stdint.h when using pre-C99 versions.
Change-Id: Id1cf5bd72a0b4d76c87dc62c443d02df18ddd3fe
Signed-off-by: Nicholas Sudsgaard <devel@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77791
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IT8784E is basically a IT8786E stripped from serial ports 3-6.
There are very few minor register differences in EC IO space and GPIO
LDN, which are covered by this patch.
Based on IT8784E-I Preliminary Specification V0.7.1 (non-public).
TEST=Dump SIO configuration on Protectli VP4670 (vault_cml).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5de8aeaff9697b854281391083f77a1083d12fe6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Remove duplicated definitions of ARRAY_SIZE macro across util/ dir.
Instead of duplicates, use the one from commonlib/bsd/helpers.h file.
BUG=b:231765496
TEST=make -C util/cbfstool; make -C util/cbmem;
make -C util/intelmetool; make -C util/superiotool
Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74474
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Grzegorz Bernacki
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- use __linux__ instead of __GLIBC__ guard for Linux-specific includes
- use POSIX ioperm instead of deprecated iopl
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I99613007aa9feddcb1041f31085cdeb195ff7a68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Use tool from INSTALL variable to create directory instead of mkdir to
be compatible with other cross-compilation buildsystems (like Yocto).
Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com>
Change-Id: I9d455f3d1a6d86c88b8e22da825fe14f9630e971
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70103
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also comment out the SMSC FDC37M602 which has a conflicting
ID and has never had the LDN/register layout anyway.
Tested on a Dell Latitude E6400
Change-Id: I5b1900e6ef599c422a1d6eca7a2ac4691d56d874
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69481
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There doesn't seem to be a datasheet available for the NCT6685D, but
there is one for the NCT6686D. The 85D seems to return the same ID as
the 86D, and the registers do seem to be returning valid data other than
LDN 0xf which returns all 1s. The LDN and register layout appears to be
identical to the NCT6687D-W.
Tested on a Lenovo ThinkCentre M900 with a NCT6685D.
Change-Id: I4de0e7b86422a14ab9ccb15b7571597611d755d5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix readouts from the hardware monitor on Fintek F71808A Super I/O.
The HWM port is +5 to the base address stored in LDN 0x4 at index 0x60/0x61.
Referred to util/superiotool/winbond.c and the Linux kernel driver f71882fg.
Tested on a HP 500-319na (Memphis-S / IPM87-MP).
Signed-off-by: Ravi Mistry <rvstry@protonmail.com>
Change-Id: I2b2b98c62f9305c6f4885c2ce3b1444801dcb9d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Parallel Port has LDN 1 and Serial Pot has LDN 2. Fix typo made in the
patch adding register definitions for NCT6687D Super I/O chip.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If850d2a0a03bd41e3d855f347fd182831bcfcdca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Based on public NCT6686D hardware datasheet revision 0.5 which should
be similar to NCT6687D.
TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Datasheet is not publicly available. Derive which registers to dump from
IT8625E, since there are mainboards that can use either chip depending
on BOM configuration. Default values are taken from an HP 280 G2 running
a coreboot build that does not configure the Super I/O.
Change-Id: Icc8c56e9cd19e940e85176ac51b8ef978275eb71
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Registers and their default values are from the datasheet ("IT8720F",
"Preliminary Specification V0.1").
Tested on an Acer G43T-AM3.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I69987be4f5cb50b3c20f06733f30b308891d5ad0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
There were several default values given for GPIO data and status
registers. As all GPIO are configured as inputs by default, we
can't predict the values of these registers, hence set their
default values to NANA.
Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Clay Daniels <clay.daniels.jr@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These were originally ignored only inside util/ but these files
shouldn't be tracked anywhere.
Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.
Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for dumping registers, default values for
EC on ITE IT8128F. Taken from datasheet 'IT8728F V0.4.2'
Test: 'superiotool -d -e' on board with IT8728F Super IO
Change-Id: I7074b740565edf458d6894c066b61c083a657cb8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In a few cases a license was added: Stuff coming from Linux is
"GPL-2.0" (not GPL-2.0-only!), build-release is by me and got the
usual GPL-2.0-only treatment. uio_usbdebug and spkmodem had their
licenses propagate to all their files.
Change-Id: Ia5712bbaa417cb9e937834512351fcc0acfa16be
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41202
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have the git history which is a more reliable librarian.
Change-Id: Idbcc5ceeb33804204e56d62491cb58146f7c9f37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
The SCH5317 can have either 0x85 or 0x8c as device ID. However, the
former results in false positives on any ITE IT85xx series embedded
controller, which has led some people to think that chip was actually in
their laptops. Moreover, there is no register dump for the SCH5317.
Since nobody has touched this in over a decade, avoid further confusion
by dropping the misleading definition.
Change-Id: I4d1d34d1b88b878461499e52f1a916ee1e33210d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Values as per "IT8772E Preliminary Specification V0.4 (For F Version)".
Some values are unclear on this document, but is the only one I have.
Change-Id: I6d74984f453c47d6ec71963a7dcab961a22a5964
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the SCH5627 datasheet which is similiar
SCH5545 id 0xc4, SCH5627 id 0xc6.
Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for AST2400 Super I/O.
The device doesn't have an ID register, so probe for scratch register
not to read as 0xff.
Tested on platform which has an AST2400.
Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Based on not publicly available IT8613E Preliminary Specification V0.3.
Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
F81866 detection tested with the iBASE SI-613:
superiotool r4.9-420-g034e5e6
Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e
F8196* detection is based on chip IDs provided by iBASE, but untested.
Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39
Signed-off-by: Kyle Stevenson <kstevenson@comqi.com>
Reviewed-on: https://review.coreboot.org/c/31052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ITE8528 which can be found on the wedge100s.
Most registers are dumped from hardware.
No datasheet is publicy available.
Change-Id: I24b12c0032157a4959336f8b51dadbe7b2e09d66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Based on IT8786E-I V0.4.1 datasheet with following remark:
"Please note that the IT8786E-I V0.4.1 is
applicable only to the D version."
Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibf6e290abb01ae1b6b28173a83e88d1d99663ad4
Reviewed-on: https://review.coreboot.org/c/30334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some Unix systems (GuixSD, NixOS) do not install programs like
Bash and Python to /usr/bin, and /usr/bin/env has to be used to
locate these instead.
Change-Id: I7546bcb881c532adc984577ecb0ee2ec4f2efe00
Signed-off-by: Yegor Timoshenko <yegortimoshenko@riseup.net>
Reviewed-on: https://review.coreboot.org/28953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There is no datasheet available for this SuperIO, but dumping all
possible registers on a Dell Optiplex GX520 resulted in data that was
similar to other supported chips. Data also matches what is set in the
BIOS, e.g. the parallel and serial ports' addresses.
Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The SCH3112, SCH3116 and SCH5127 were lacking a pin dump. Since their
datasheets are available, add their pin dumps.
The SCH3112, SCH3114 and SCH3116 are almost identical, they only differ
in the number of serial ports. Some values in the SCH3114 dump were
inaccurate, that has been fixed as well.
Datasheets used:
- SCH311X: DS00001872A
- SCH5127: DS00002081A
Change-Id: Ic985526be9b09e0452eaf883904dfaf709b7e907
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/28794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
