The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.
Fixes Thunderbolt on RPL-HX boards using Maple Ridge and Barlow Ridge
controllers.
Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has been updated with a Thunderbolt 5 controller (Barlow
Ridge).
Identified chip changes from the schematics:
- JHL8540_MP -> JHL9580_QS
- TPS65994BF -> TPS65994BH
- IT5570E-128 -> IT5570E-256
Change-Id: I784e489cdd034febeaaac0182ab5b4fe672381ec
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Go through the schematics and update GPIOs for the unit. In particular,
explicitly mark unconnected pins and pins without placed components as
not connected.
Change-Id: I5a81115850d7bf3ecabeae29058e86cea51ac390
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Since these boards will use S0ix they need to leave CSME enabled for the
CPU to reach C10.
Change-Id: I70c908402c9964508bb9c439d48d24773f5a35ab
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The newer batch of these boards do not de-assert VW PLTRST# on S3
resume, causes the units to not power on in the EC code. Switch them to
S0ix by default, but leave S3 available.
Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Sending the disable and EOP commands will not work if flash descriptor
override is set on Meteor Lake.
Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee
Signed-off-by: Jeremy Soller <Jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The darp10 has a second fan but no dGPU. The NFAN Method must exist, so
use the default hwmon names of "fan1" and "fan2" for labels.
Change-Id: Icde5dec82262d9262b046c1557167801af8e5cb2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I202c0607c2cdac1df59f42fb41735704dd5bd95c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Fixes using USB3 devices at USB3 speeds in all ports.
This fix requires `EnableTcssCovTypeA`, which is not available in the
coreboot FSP headers and not available upstream as Intel still has not
made a Client FSP release.
Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Lemur Pro 13 (lemp13) is an Intel Meteor Lake-U based board.
There are 2 variants to differentiate which keyboard design the unit
uses, as they require different EC firmware.
Change-Id: Icac8c7dafd6371881622d797f399f8ddbe13cbce
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.
Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].
[1]: https://github.com/system76/smart-amp
Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.
Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d
Signed-off-by: Jeremy Soller <jeremy@sysetm76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Intel introduced a new UPD specifically for setting the HDA subsystem ID
in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be
locked with a default value of 0 by that point.
Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20).
TEST=PCI config space for HDA device has subsystem ID set.
Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The ACPI is adjusted based on SOFTWARE_CONNECTION_MANAGER, so set
the UPD to match this to avoid the connection type being
mismatched.
If it's mismatched, the TBT port will timeout.
TEST=Boot starbook/rpl and check TBT 4 dock is correctly identified.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3ab68c01f682723dab39870f0676e59ae3d89add
Add a new driver for discrete Thunderbolt controllers. This allows using
e.g. Maple Ridge devices on Raptor Point PCH.
Ref: Titan Ridge BIOS Implementation Guide v1.4
Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The
driver provides ACPI support for dynamically powering on and off the
GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU
power in romstage.
References:
- DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide
- DG-09954-001: NVIDIA GN20/QN20 Software Design Guide
Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Apply CB:75284 to Meteor Lake.
CB:52731 introduced support for reading SPD from the EEPROM via SMBus.
Replace the now unneeded workaround for DDR5 with filling in the correct
channels for DDR5.
Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
CB:52731 introduced support for reading SPD from the EEPROM via SMBus.
Replace the now unneeded workaround for DDR5 with filling in the correct
channels for DDR5.
Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume
on S3 with the error `TPM_RC_VALUE`.
Per TPM2 spec, handle the failure by performing a TPM Restart.
> The startup behavior defined by this specification is different than
> TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter
> Failure Mode if no state is available when the TPM receives
> Startup(STATE). This is not the case in this specification. It is up
> to the CRTM to take corrective action if it the TPM returns
> TPM_RC_VALUE in response to Startup(STATE).
Fixes the following error from being repeatedly logged in Linux:
> kernel: tpm tpm0: A TPM error (256) occurred attempting get random
Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59
Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This updated microcode fixes the recent voltage issues on the Raptor
Lake S platform. Intel provided this specific microcode just as an
attachment [1]. Thus, we've uploaded it to our own blobs repository,
which is why the path is changed.
Microcode signature:
sig 0x000b0671, pf_mask 0x32, 2024-07-18, rev 0x0129
[1] https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/issues/81
Change-Id: I6d01e38476b0d3dc5281ea1d85bac87043d122dd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84132
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id a8db7df:
2023-07-24 16:05:01 +0000 - (mb/google: amd projects: Add signed verstage files)
to commit id 45f1b75:
2024-08-29 11:51:27 +0200 - (soc/intel/raptorlake: Add microcode for 06-b7-01)
This brings in 7 new commits:
45f1b75 soc/intel/raptorlake: Add microcode for 06-b7-01
a0fdf22 soc/mediatek/mt8186: Update DRAM binary from 0.1.0 to 0.1.1
c641a81 mb/erying/tgl: Add blobs necessary for platform bring-up
30e541a soc/mediatek/mt8192: Update dram.elf from 1.6.3 to 1.8.3
ba6e8a4 soc/intel: Remove Quark blobs
1f31acc soc/mediatek/mt8188: Update DRAM blob to 0.1.2
542c27d mb/starlabs/starbook: Consolidate version history
Change-Id: I7553ea2112cb336866bdff3c24c02f8a7fd15811
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch eliminates the LPC_IOE_COMA_EN and LPC_IOE_COMB_EN IO enables
from the io_enables variable in the pch_early_iorange_init() function
because lpc_io_setup_comm_a_b() is intended to activate legacy COM
ports like COM-A (0x3F8 - 0x3FF) and COM_B (0x2F8 - 0x2FF).
These COM ports are being activated unconditionally, which is
undesirable for the Intel Alder Lake platform and causes traffic over
the IO bus.
As a result, this code is being removed and platforms that select
DRIVERS_UART_8250IO can activate legacy COM ports.
BUG=b:354066052
TEST=Able to boot google/redrix to the operating system and confirm
that there was no traffic over legacy COMs while being monitored
using the eSPI analyzer.
Change-Id: I7a6e38bd151f823d37c07ee89a800489122cc209
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84080
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sync checklist with release template; add new heading for paragraph
on pushing the signed tag to make it stand out.
Change-Id: Id49b3f38d3501382b7fb7ac791190c0cacd58a11
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84034
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are the final release notes before the release is tagged. They
will be updated after the tag is in place with any differences,
including changing the "upcoming release" notice with the notice that
it has been released.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I449e8490d72976c8f723dc3b5ab3b77d7b16e3a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84046
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation for the upcoming release, add the template for the
24.11 release and update index.md.
Change-Id: I1e524f1db0090bf8815b08315f9cbc9894965af7
Signed-off-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84036
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:348258637
TEST=Local build successfully and boot to OS normally.
Change-Id: I59c420c03a8f01d185f616a2212798266b4251e0
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
EE change GPP_C1 from pull-up to OD&no pull-up in PCH GPIO Table.
BUG=b:358472598
TEST=Build and verified test result by EE team
Change-Id: I84d1b42a39bebbcd610cebc46f979018fc79238f
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83904
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some targets cannot be supported by clang as clang generates slightly
larger binaries which the hardware won't accept. This is usually the
case with CONFIG_CHROMEOS.
Change-Id: I88cf8ce16fb6c61c19d615e396f5871179b06fc8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69747
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on nivviks, check BRDS is shown in SSDT.
Change-Id: I0908ff500434401bf89a5313427cf304f32cf929
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
PCIE WLAN Bluetooth is on port8, need to correct USB port for PCIE WLAN
bluetooth companion device.
BUG=b:345596420
TEST=Build and test on revin, check BRDS is shown in SSDT.
Change-Id: Ie8174567b863e1afe8b0a27e644e24e9d3de6d19
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84020
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
The current region_end() implementation is susceptible to overflow
if the region is at the end of the addressable space. A common case
with the memory-mapped flash of x86 directly below the 32-bit limit.
Note: This patch also changes console output to inclusive limits.
IMO, to the better.
Change-Id: Ic4bd6eced638745b7e845504da74542e4220554a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
A few differences with the original link targets:
- 'libs' is now supported on all arch even though only x86 uses it
- compiler_rt is included on arch that previously did not (arm). This
however has no impact as there compiler_rt is not defined for those
arch in xcompile
- LIBGCC_FILE_NAME_bootblock is not included, but this was not defined
anywhere so this is a noop
Change-Id: I64f7686894c99732d06972e7ba327061db6d7c44
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83574
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the boilerplate --oformat out of the makefile.mk
Change-Id: Ib78934fff4a31c4375da2038efca5027b813b07b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83999
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add the condition of unprovisioned fw_config to enable all storages
and devices. It's for first boot on all storags and preliminary test
in factory when fw_config is unprovisioned.
BUG=None
TEST=Build jubilant firmware and boot to OS on storages when fw_config
is unprovisioned and ensure all devices are enable.
Change-Id: Ia14632744c34548e2c201dfc58d82515cdd02df0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84002
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Storage devices are very critical to boot to OS. When probe list is
defined for storage devices, all of them get disabled when fw_config is
unprovisioned - a typical situation in the factory. Fix this by
configuring the storage devices in device/override tree to probe and
enable them when fw_config is unprovisioned.
BUG=None
TEST=Build Brox firmware and boot to OS when fw_config is unprovisioned.
Change-Id: I0537f7d1d83293b9b3408f0aadf11fa2e7908163
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83984
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
