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48035 Commits

Author SHA1 Message Date
Sheng-Liang Pan
a1459caa88 mb/google/dedede/var/taranza: Add Wifi SAR for taranza 
BUG=b:297276380
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot
chromeos-bootimage

Cq-Depend: chrome-internal:6373154

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If21c7a7d329b0b1cc2c73dadb0c5b8a5b8ab27e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77399
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
 2023-08-26 21:22:05 +00:00
Tyler Wang
d97bd1574b mb/google/rex/var/karis: Remove WWAN module 
According to the schematic, karis does not have a WWAN module, remove
related settings.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I653e3b4fae8a53018a6004528d1cfb3a6c883687
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77427
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:19:11 +00:00
Elyes Haouas
ce655f5bd5 vendorcode/intel/edk2: Use C99 flexible arrays 
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.

Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-26 21:17:24 +00:00
Subrata Banik
0c602b614d mb/google/rex/var/rex0: Use FW_CONFIG to select the correct SAR table 
This patch changes the SAR table selection logic to use FW_CONFIG which
will eventually help to support different WiFi SAR tables.

TEST=Able to build and boot google/rex.

Change-Id: I8f1244e3c3715bc3fbe6be1ade87817ff19836de
Signed-off-by: YH Lin <yueherngl@google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77428
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:16:45 +00:00
Martin Roth
09202cce26 vc/intel: Remove unnecessary Kconfig options 
These Kconfig options were being used basically as #define statements,
which is unnecessary. This isn't a good use of Kconfig options and would
be better just as #defines if actually needed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2023-08-26 21:14:45 +00:00
Martin Roth
8b703954c3 vc/siemens: Only add the include path for hwlib when needed 
This patch moves the line adding hwlib to the include path to the inner
makefile so that it doesn't get added to every build, but only when
CONFIG_USE_SIEMENS_HWILIB=y

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id668b76366a554efff560cec746e637487ebdbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:13:50 +00:00
Martin Roth
81da643c13 vc/amd: Only pull in Makefiles & dirs that are needed 
This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled
into the build when they aren't needed.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-26 21:13:20 +00:00
Martin Roth
c12b290c5d vc/eltan: Only pull in vc/eltan/security Makefile when enabled 
This change tells the build to only pull vc/eltan/security/Makefile.inc
into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-26 21:12:17 +00:00
Wisley Chen
8e42ebeea2 mb/google/nissa/var/yaviks: Disable SUSCLK based on fw_config 
Disable SUSCLK for MT7922 based on FW_CONFIG to avoid power leakage.

BUG=b:296511904, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=build and verified by EE

Change-Id: I9a6bf0ab7cc77f95e0d64f1380eac9e022fc08e4
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77383
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:11:00 +00:00
Cliff Huang
5790a05237 soc/intel/meteorlake: Add PMC GPIO GPE group mapping 
Add two missing mapping for GPIO GPE routes

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I3f0d13cf7c07201856e934f22efc4cc8c4ea5bf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77423
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-26 21:08:46 +00:00
Nico Huber
b2893e22e6 memrange: Honor limit in the last step of top-down stealing 
We only checked that the resource fits below the given `limit` in
memranges_find_entry(), but then accidentally placed it at the top
of the found memrange. As most resources have only a coarse limit,
e.g. the 4G barrier of 32-bit space, this became only visible when
artificially setting an unusual, lower limit on a resource.

So, for the final placement, use `MIN(limit, range end)` instead
of the range's end alone.

Change-Id: I3cc62ac3d427683c00ba0ac9f991fca62e99ce44
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-08-26 20:29:37 +00:00
David Wu
8a58483072 mb/google/brask/var/kuldax: Set customized_leds value for RTL8111K 
Set customized_leds value for RTL8111K to fix led can't work.

BUG=b:297093096
BRANCH=firmware-brya-14505.B
TEST=Verified RTL8125 and RTL8111K led can work normally.

Change-Id: Icb8624005e7e24398abdd242570970c6bfa8a09f
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77390
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 14:41:30 +00:00
Chen-Tsung Hsieh
c61be60b97 mb/google/brya: Create nokris variant 
Create the nokris variant of the nissa reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:285838647
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_NOKRIS

Change-Id: If7cb00ce978236746dfe4d097d1f20aeebb96a35
Signed-off-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-08-25 14:41:06 +00:00
Krishna Prasad Bhat
055b874658 commonlib: Add PSR backup eventlog types 
Add new eventlog types to support logging of Platform Service Record
(PSR) backup related messages. Eventlog entries are added on PSR data
backup success/failure and also when PSR data is lost.

BRANCH=None
BUG=b:273207144
TEST=Verify elog event added after PSR data backup command is sent
cse_lite: PSR_HECI_FW_DOWNGRADE_BACKUP command sent
...
ELOG: Event(B9) added with size 10 at 2023-07-27 06:44:49 UTC

Change-Id: I01ce3f7ea24ff0fdbb7a202ec3c75973b59d4c14
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77004
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 14:39:45 +00:00
Jakub Czapiga
1e3138fe0b mb/google/rex/var/ovis: Update PWM_BUZZER GPIO config 
BUG=b:271491845
TEST=Build and boot google/ovis on Rex P1 with buzzer added on GPP_B08

Change-Id: I44718ea15c93a075b6468f335a869a2cfa585273
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76049
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-08-25 14:38:48 +00:00
Sean Rhodes
6319ef9718 soc/intel/apollolake: Correct the logic for the legacy 8254 timer 
The `use_8254` should be flipped, the same as the other Intel
SOCs.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d6c859c0910b796d2ae5874a560ff9974578106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2023-08-25 14:38:31 +00:00
Mark Hsieh
2cd2263c32 mb/google/nissa/var/joxer: set the DB_USB field in FW_CONFIG 
Joxer will have SKUs with no type-c on daughter board, add fw_config
for EC control it.

BUG=b:297131468
TEST=USE="project_joxer emerge-nissa coreboot"

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie8098f72e29a10ebbaf3ba3b09d6a002d09fd35a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77394
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 14:37:45 +00:00
Anand Vaikar
2c3cded4bc mb/amd/birman: Enable two USB4 xHCI controller devices 
TEST: Boot to ubuntu OS and verify that USB4 devices are listed in lspci command
00:08.3/06:00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c0
00:08.3/06:00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15c1

Change-Id: I6253a7694702179454bc1ca14825fd4f3b949c13
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-08-25 12:46:42 +00:00
Felix Held
4ff1d63fc4 soc/amd/common/include/root_complex: add IOHC MISC SMN base addresses 
The Genoa server SoC has 4 IOHC PCI roots instead of the 1 the mobile
SoCs have, so add the additional 3 SMN base address definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72dba39bff7c7a739e1dfddd80e7f22e65b5f139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77395
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 12:24:01 +00:00
Felix Singer
53a43f14da drivers/intel/fsp2/Makefile.inc: Deduplicate compression type checks 
When LZMA compression is selected, then it's not needed to check if LZ4
compression is selected in addition. So instead of handling both cases
separately, check for LZ4 only if LZMA is not selected.

This applies to the cases of both, FSP-M and FSP-S.

Change-Id: I4ea61a38baf4c29bf522a50a26c6b47292e67960
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77323
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-25 10:03:20 +00:00
Tyler Wang
fa17a9d03c mb/google/rex/var/karis: Add SOC_TCHSCR_INT settings to gpio table 
Karis use I2C touchscreen only, add SOC_TCHSCR_INT(GPP_C07) to ramstage
gpio table.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: Ie715cfbe1984dbe38cd933312304b42ce9088806
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-08-25 03:23:46 +00:00
Kapil Porwal
33a5722bd7 mb/google/rex/var/karis: Fix incorrect GPIO pad numbers 
Fix incorrect GPIO pad numbers. GPP_F19 was mistakenly used instead of
GPP_F14, GPP_F15 and GPP_F16 GPIOs.

BUG=none
TEST=none

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I219b78a5e92d9c56799964ea88615c27aed2e92e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77401
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-25 03:23:19 +00:00
Arthur Heymans
1312ef49b3 Kconfig: Add option to make clang the default compiler 
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie910f654abdb8d79c686363d2bd8af4ceeea4087
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76436
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 22:08:59 +00:00
Riku Viitanen
f442eadcad mb/hp/compaq_elite_8300_usdt: enable mSATA 
Tested with a Kingston UV500.
It works the same (3Gb/s) as with vendor FW.

According to smartctl -a /dev/sda:
SATA Version is:  SATA 3.1, 6.0 Gb/s (current: 3.0 Gb/s)

Change-Id: I5c714351586e6084029ce4c54fb47cbae4d3405b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77376
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 22:07:14 +00:00
Johannes Hahn
6117a2d296 mb/siemens/fa_ehl: Remove RTC RV3028C7 
Delete this RTC from the configuration as fa_ehl mainboard
uses a different real time clock.

Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: Ifd6b68d05a094cb4c890f1ffce62d89b771e23c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
 2023-08-24 14:03:05 +00:00
Johannes Hahn
7f99551d5c mb/siemens/fa_ehl: Remove TPM 
The mainboard currently does not make use of a dedicated TPM.
Although it has one assembled. This TPM is not connected
via LPC hence it is turned off in the devicetree.

Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I96cc38c3812d76d654339ad5b2b7f88fd1327779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77351
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
 2023-08-24 14:02:45 +00:00
Johannes Hahn
a9d8531c8c mb/siemens/fa_ehl: Remove NC_FPGA 
fa_ehl mainboard does not make use of the SIEMENS NC_FPGA
as it is not placed on this board.

Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Change-Id: I5f1f796e4339ba37d461d6818c2bb6ba028b89c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
 2023-08-24 14:02:24 +00:00
Stanley Wu
00e92f4538 mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED config 
Enable bit 9 for 100M mode green LED blink.

Reference: 
- RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration

BUG=b:293983804
TEST=emerge-dedede coreboot and verify LAN LED behavior

Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-08-24 13:39:49 +00:00
Wisley Chen
d6c2e054f8 mb/google/nissa/var/yaviks: rename DB_NONE to DB_1A 
Yaviks doesn't have none DB sku, and rename to DB_1A for yahiko.

BUG=b:294928078, b:294456574
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: Icb952c0716d446d5feb5580f357120a27193284e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77384
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 13:37:20 +00:00
Cliff Huang
711f84d177 soc/intel/metorlake: Fix PMC GPIO group assignment 
Those values need to match with the ones defined in PMC PWRM
GPIO CFG register.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I8e84df83caab794e2fe7186e89e78343c2b55fd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 13:33:50 +00:00
Johannes Hahn
377153d58d mainboard/siemens/fa_ehl: Add new mainboard based on mc_ehl2 
Add a new mainboard called fa_ehl which is based on Siemens's
'mc_ehl2'. This commit simply copies the mainboard directory and
adjusts the naming to match the new board's name. Moreover a variants
scheme is provided for possible alternative implementations. Follow-up
commits will introduce the needed changes for the new mainboard.

Change-Id: Ia389c8812d14db8b663547e6336e900becbc8be6
Signed-off-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76444
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
 2023-08-24 13:31:17 +00:00
Arthur Heymans
736d4d25df acpi: Add function to add ARM PL011 to ACPI DBG2 
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I3c3f7f579ec0ec4fdb72e1f6b785026daab17bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76297
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 13:20:06 +00:00
Michał Żygowski
06cb997b0a soc/intel/apollolake: Move the PMC definitions to pmc.h file 
Add a pmc.h file, which is needed for OC watchdog compilation. The PMC
definitions from pm.h are moved to pmc.h.

TEST=Build UP Squared and Intel GLKRVP sucessfully.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2726aaae1ce60d15a3944dadcf793def2dcb3a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
 2023-08-24 12:59:48 +00:00
Yidi Lin
eb6642d8e4 soc/mediatek/mt8188: Remove GPT timer init 
GPT timer init is no longer needed after DRAM blob is switching to ARM
arch timer.

BUG=b:229800119
TEST=boot to kernel

Change-Id: Iec1f93c96e791220feed4225959ef15c074ba577
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77388
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:55:41 +00:00
Won Chung
d597320d8e mb/google/brya/var/vell: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I62103563ec49769cd842fedf8c2c55118c55aa14
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:54:19 +00:00
Won Chung
4eaa0a929f mb/google/brya/var/taniks: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I12fa83987869b9a52940a49e9f7897d62abf59ff
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:54:02 +00:00
Won Chung
020d43e553 mb/google/brya/var/taeko: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I07e85f28c4f260d04317ec594e162db20f3d4ddd
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:53:50 +00:00
Won Chung
7f5c6d21c6 mb/google/brya/var/volmar: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie7982d1001c4a65322b4e6fdbd70b20c8eee6f0e
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:53:24 +00:00
Won Chung
d64da18c4a mb/google/brya/var/primus: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I78eee4c5f11b06fbc104182a4313c20be91b821b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76905
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:53:08 +00:00
Won Chung
f860d5aba0 mb/google/brya/var/osiris: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I6157894b96da2e9faed229a1f18c0c0b7c60897b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:57 +00:00
Won Chung
fb69c56971 mb/google/brya/var/omnigul: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie0304ea4343361ff0395c7204ebb76bffb5a6d97
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:33 +00:00
Won Chung
939d07ea35 mb/google/brya/var/mithrax: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Icdb8e9a20ab536f80fa7358472cca01996faf447
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:52:14 +00:00
Tyler Wang
34ce8c7377 mb/google/rex/var/karis: Disable GSPI0 
According to the schematic, karis does not have a SPI touchscreen,
remove related settings.

BUG=b:294155897
TEST=emerge-rex coreboot

Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2023-08-24 12:52:08 +00:00
Won Chung
d68bb7c84f mb/google/brya/var/marasov: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ie2c089c0418f76ac7c8ce2e531dbbc91c66f34a0
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76901
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:51:52 +00:00
Won Chung
af1782cdcb mb/google/brya/var/kano: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I15888b4e5bd46c98e0864eaa6850e1a24b22fe65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76900
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:51:38 +00:00
Won Chung
1c8f5c7f1b mb/google/brya/var/gimble: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ief27cd6e32780683c53a88d73194c6d82c6c212b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:51:25 +00:00
Won Chung
7e00d51c39 mb/google/brya/var/felwinter: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: I7be4a47ea2a8cb2b6f4a2d633252eec523807da6
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:50:55 +00:00
Won Chung
7fcdb9f902 mb/google/brya/var/crota: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Ic5343de88f5f089c9ec4a992f5a6383c08641568
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76897
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-08-24 12:50:40 +00:00
Won Chung
767ff9127b mb/google/brya/var/banshee: Add new GFX devices with custom _PLD 
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.

BUG=b:277629750
TEST=emerge-brya coreboot

Change-Id: Iced1061bab224d918fd5f0525423ac6858e1799b
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-08-24 12:50:21 +00:00
Martin Roth
59d5092454 soc/nvidia: Fix incorrect SPDX license 
The SPDX license header for this file did not match the license text
in the file.

Update the SPDX header and remove the license text.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifc0db79e43df6d14b80b0ad3061fe42de17ed90f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77379
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
 2023-08-24 05:30:10 +00:00