Commit Graph

55014 Commits

Author SHA1 Message Date
Tim Crawford
09bdd1e515 mb/system76: Enable S0ix for darp8/darp9
The newer batch of these boards do not de-assert VW PLTRST# on S3
resume, causes the units to not power on in the EC code. Switch them to
S0ix by default, but leave S3 available.

Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2024-01-11 08:54:23 -07:00
Tim Crawford
1a5bdc52cc mb/system76: Enable EC lockdown on TGL+
Change-Id: I4b07846c404eb93ab4baf0a78a4bbffcc5d8afca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-19 08:41:08 -07:00
Tim Crawford
2f5e31762c ec/system76: Support lockdown based on EC security state
Change-Id: I202c0607c2cdac1df59f42fb41735704dd5bd95c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-19 08:41:08 -07:00
Tim Crawford
8270aee13e mb/system76: Enable dGPUs
Change-Id: I28fe45afaccd60621f2f2456af14306e18df2657
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-12-19 08:41:08 -07:00
Jeremy Soller
1cf29703ee drivers/gfx/nvidia: Add driver for NVIDIA GPU
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The
driver provides ACPI support for dynamically powering on and off the
GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU
power in romstage.

References:
- DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide
- DG-09954-001: NVIDIA GN20/QN20 Software Design Guide

Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
f97ffca766 soc/intel/alderlake: Add IRQ for non-existent CPU PCIe device
Device 0:01.1 does not exist on ADL-P. I assume this works because the
bridged device has function 1.

Fixes the following error in Linux:

    pcieport 0000:00:01.0: can't derive routing for PCI INT B
    snd_hda_intel 0000:01:00.1: PCI INT B: no GSI - using ISA IRQ 10

Which in turn resolves the conflict with the PCH HDA device...again:

    irq 10: nobody cared (try booting with the "irqpoll" option)
    <snip>
    [<00000000bf549647>] azx_interrupt [snd_hda_codec]
    Disabling IRQ #10

Change-Id: I9d9a0003764a1e031be578c1f406b2a5d7512de7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
c93689d557 mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.

Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].

[1]: https://github.com/system76/smart-amp

Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
dca78e4373 mb/system76/rpl: Enable discrete TBT device
The HX board, using PCH-S, use a discrete Thunderbolt device (Intel
Maple Ridge), as opposed to a built-in one like the boards using PCH-P.

Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller.

Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
fa90e35cae drivers/intel/dtbt: Add discrete Thunderbolt driver
Add a new driver for discrete Thunderbolt controllers. This allows using
Maple Ridge devices on Raptor Point PCH.

Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
3289a306e6 lib,soc/intel/common/block/smbus: Use a SPD length of 512 bytes for DDR5
Change-Id: I8bdc4c676a0f571fd8f34e078f6a1c73a2e90a87
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
7fcf710e7f soc/intel/adl: Fill in SPD data on both channels of DDR5 memory
CB:52731 introduced support for reading SPD from the EEPROM via SMBus.
Replace the now unneeded workaround for DDR5 with filling in the correct
channels for DDR5.

Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Meera Ravindranath
828935066d soc/common/smbus: Add support for reading spd data via smbus for DDR5
DDR5 uses a Serial Presence Detect EEPROM with hub function
(SPD5 hub device) to store the spd data.
This CL adds support to read the spd5 hub device via smbus.

BUG=b:180458099
TEST=Boot adlrvp DDR5 board to kernel

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
2023-11-19 22:05:06 -07:00
Jeremy Soller
e312861a9d soc/intel/alderlake: Hack to preserve SBREG
Change-Id: Ie70905d34a4050aeff4b5cda116eb700f19a18ea
2023-11-19 22:05:06 -07:00
Michał Kopeć
5f608c9734 drivers/smmstore/ramstage.c: retry smmstore init up 5 times
Retry calling the SMI 5 times in case the initial write to APM did not
cause SMM entry immediately.

Fixes occasional SMMSTORE initialization failure on Clevo NV4xPZ with
Intel i5-1240P processor. The issue was especially evident when all
logging in coreboot was disabled.

Based on SMMSTORE implementation in MrChromebox's fork of EDK2:
27854bc8c5

Change-Id: I8929af25c4f69873bbdd835fde5cb60fc324b6ab
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
d9977a9fa9 security/tpm/tspi: Do TPM Restart if TPM Resume fails
The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume
on S3 with the error `TPM_RC_VALUE`.

Per TPM2 spec, handle the failure by performing a TPM Restart.

> The startup behavior defined by this specification is different than
> TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter
> Failure Mode if no state is available when the TPM receives
> Startup(STATE). This is not the case in this specification. It is up
> to the CRTM to take corrective action if it the TPM returns
> TPM_RC_VALUE in response to Startup(STATE).

Fixes the following error from being repeatedly logged in Linux:

> kernel: tpm tpm0: A TPM error (256) occurred attempting get random

Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59
Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
ea848eba56 intel/block/pcie/rtd3: Also implement _PR3
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2023-11-19 22:05:06 -07:00
Jeremy Soller
5f3df49cf7 intel/block/pcie/rtd3: ACPI debug messages
Change-Id: Icc4a882ff73f62a134b92f1afb0dc298ea809189
Signed-off-by: Jeremy Soller <jeremy@system76.com>
2023-11-19 22:05:06 -07:00
Tim Crawford
9fa04e13ca submodules: Use absolute paths
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: If03415f80a6028e263e76a9e3cc10df0cde5cc3c
2023-11-19 22:05:06 -07:00
Martin Roth
c8dc4a3bd1 util/lint: Add linter to keep selects out of Kconfig.name
While having select statements in Kconfig.name files is valid in the
syntax of the Kconfig language, having the selections split between the
normal Kconfig file and Kconfig.name files makes it harder to see what's
going on.

Kconfig.name files will now be limited to their original purpose of
selecting a particular board or board variant, not actually configuring
that board.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2aab78e296f2958e77a938b1afa40a25a6aa82b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
4.22
2023-11-18 01:58:24 +00:00
Shelley Chen
7e775cf893 mb/google/brox: Use Ti50 config
Brox is using Ti50, so make sure that we set the right config for that.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18 01:54:18 +00:00
Shelley Chen
513d54708d mb/google/brox: Fix GPIO assignments in gpio.h
Assigning the macros in gpio.h to the correct GPIOs.  Also, fixing GPE
configurations so that they are mapped to the proper wake sources
(GPP_B, D, E groups).

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18 01:54:03 +00:00
Julius Werner
653f349f2f qualcomm/sc7180: Move QCSDI and increase romstage size by 4KB
We need to increase romstage size a little to make a compiler upgrade
fit (CB:70771). Unfortunately the end of the romstage directly touches
the QCSDI region in the current memlayout, and there is no other way
to reshuffle things to make more space... so we need to move QCSDI out
of the way. This means that anyone who is actually building this
platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob
that's not publicly available) will need to recompile their QCSDI binary
to match the new start address.

Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-18 00:41:53 +00:00
Martin Roth
947eebedcb Docs/releases: Update 4.22 release notes
These should be the final release notes prior to tagging coreboot

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id723f8e1fc92ef1a36e877f48e594eef59b0ba8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79077
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-18 00:26:16 +00:00
Martin Roth
6843755c26 docker/coreboot-sdk: Add perl modules for gcov
These perl modules are needed to run the coverage-report target for
gcov.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If32a42ce17edcbae94394f770c26d3300abebcbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79072
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 23:46:56 +00:00
Martin Roth
64b340065f Docs/security/vboot: Update list of boards with vboot
Update the vboot board list for the 4.22 release.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I77c5ca2c2c36d8b1ddadad4f15d2d4148ff0b325
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-11-17 22:19:04 +00:00
Felix Singer
a2dffba45f mb/google/herobrine: Move selects from Kconfig.name to Kconfig
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.

Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 22:18:21 +00:00
Felix Singer
e0a1ca5ac9 mb/google/trogdor: Move selects from Kconfig.name to Kconfig
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.

Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-17 22:18:01 +00:00
Felix Singer
c541567834 soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repo
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to
include the Qualcomm blobs, which requires to accept their license.
However, for various reasons it makes sense to build without blobs, e.g.
static analysis or just build-testing.

So in order to do that, run the steps integrating the Qualcomm blobs
into the coreboot binary only if USE_QC_BLOBS is enabled and also remove
guards which prevent building related mainboards when USE_QC_BLOBS is
not enabled.

Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 22:17:31 +00:00
Felix Held
8ccd314ce6 nb/amd/pi/00730F01: add CPU and domain ops in devicetree
Add the CPU and PCI domain operation bindings statically in the chipset
devicetree instead of adding them during runtime.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-17 16:28:10 +00:00
Felix Held
1952d13a41 nb/amd/pi/00730F01: restructure chip ops
Since this chip is a SoC and also to bring the chipset devicetree more
in line with the chipset devicetree of Sandy Bridge, merge the chip
operations of the northbridge's root complex and the northbridge itself
into one chip operations structure and use it at the top level of the
devicetree.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17 16:27:52 +00:00
Felix Held
0010b89c67 nb/amd/pi/00730F01: introduce and use chipset devicetree
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI
devices. The HDA controller in the FCH at function 2 of device 0x14 on
bus 0 was missing in the mainboard's devicetrees.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17 16:27:43 +00:00
Felix Held
10e478c4cf include/device/device: drop HAVE_ACPI_TABLES guards
There's no need to remove the corresponding fields from the
device_operations struct when HAVE_ACPI_TABLES isn't selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 15:13:15 +00:00
Felix Held
ab8a094cf0 include/device/device: drop GENERATE_SMBIOS_TABLES guards
There's no need to remove the corresponding fields from the
device_operations struct when GENERATE_SMBIOS_TABLES isn't selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17 15:12:59 +00:00
wuyang5
823f95e8a3 mb/google/corsola: Configure I2C and I2S interface for ALC5650
Configure I2S1 and I2C5 for ALC5650 to support beep sound in
depthcharge.

BRANCH=corsola
BUG=b:305828247
TEST=Verify devbeep in depthcharge console

Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-17 15:03:01 +00:00
Dinesh Gehlot
9664463c71 MAINTAINERS: Add Dinesh Gehlot as MTL SOC and GOOGLE REX MB maintainer
Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-17 15:02:35 +00:00
Matt DeVillier
a13959e3f7 mb/google/zork/morphius: Drop touchscreen detection
Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO
for touchscreen power/enable, and so fail with runtime detection
enabled. Since it only has one touchscreen option, and no SKUs lack a
touchscreen, we can safely assume it is present in all cases.

TEST=build/boot morphius w/4k screen, verify touchscreen enabled in
cbmem and functional in Linux and Windows.

Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-17 12:43:19 +00:00
Martin Roth
0bb9dcce19 util/docker: Switch back to root user in jenkins-node
Leaving the user as coreboot caused the entrypoint to run as coreboot,
which means we couldn't mount directories or run sshd correctly.

Switching to root at the end of the file fixes this.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79067
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 23:18:47 +00:00
Maximilian Brune
794d1d7f6c util/ifdtool/ifdtool.c: Add NULL check for fmapname
Some boards (e.g. prodrive/hermes) that do not provide their own FMAP
and therefore have been generated by the build system (+ ifdtool)
experience a failure when trying to build with an IFD that contains
regions which do not have equivalent fmap names (set to NULL).

Therefore add a NULL check for the fmapname and ignore the region if we
do not have an fmapname.

Test: compile prodrive/hermes

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib4589b7fdbd11d644214ca5601536e9aeb26882f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-11-16 23:09:11 +00:00
Simon Glass
d3870a2761 ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
Generated using update_ec_headers.sh [EC-DIR].

The original include/ec_commands.h version in the EC repo is:
  ab9b64ac4c Add a host command to print info about AP-firmware state
The original include/ec_cmd_api.h version in the EC repo is:
  ab9b64ac4c Add a host command to print info about AP-firmware state

BUG=b:300525571
BRANCH=none
TEST=none

Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 23:08:06 +00:00
CoolStar
42be899b65 acpi/device: Only return dev->ops->acpi_name if non-NULL
Returning a NULL device name can cause issues if something else does
handle it.

E.g. UART and GNA devices on Intel Alder Lake-N cause
INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid
packages being created from a NULL name

Test: build/boot google/nissa (craaskvin) to Win11

Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-16 22:18:25 +00:00
Matt DeVillier
31327d8b4b mb/google/skyrim/frostflow: Drop GPIO override for camera shutter
Appears to not be used under Windows, Linux, or ChromeOS, and causes
high CPU usage at idle under Windows.

BUG=none
TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter
function unchanged, CPU usage under Windows idles where expected.

Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16 18:11:25 +00:00
Felix Singer
26e7c1eae4 Revert "tests: Allow specifying vboot source directory"
This reverts commit 7713a2f295.

Reason for revert: breaks main branch

Change-Id: I2749bea9369c222e510b838e278c7797d5dce56e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78852
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-11-16 16:10:26 +00:00
Matt DeVillier
7739e53398 Update amd_blobs submodule to upstream main branch
Updating from commit id edd465837e26 (2023-10-20):
  cezanne: Update PSP binaries to release 0.11.11.75

to commit id e4519efca746 (2023-11-15):
  Revert "picasso: Update PSP binaries to release 0.8.13.7B"

This brings in 1 new commit:
e4519efca7 Revert "picasso: Update PSP binaries to release 0.8.13.7B"

Change-Id: I860aa04324128199cbc91a5f310fcdf92a2cd65d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16 16:01:40 +00:00
Matt Parnell
84e8037a43 mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX
System76 only sells units with memory speeds up to 5200 MT/s, but the
i9-13900HX supports up to 5600 MT/s memory.

Tested by running memtest and checking dmidecode reports 5600 MT/s when
using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3,
bonw15, serw13.

Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49
Signed-off-by: Matt Parnell <mparnell@gmail.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78912
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 14:44:14 +00:00
Felix Singer
a03999be25 mb/supermicro/x11: Make use of chipset devicetree
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.

Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 13:19:16 +00:00
roccochen@chromium.com
7713a2f295 tests: Allow specifying vboot source directory
Respect VBOOT_SOURCE while including generic headers.

BUG=none
TEST=make clean-unit-tests &&
     VBOOT_SOURCE=/path/to/vboot_reference/ make unit-tests -j
TEST=make clean-unit-tests && make unit-tests -j
BRANCH=none

Change-Id: Id3bb3726c91167d2dd648d748763a3948787f28d
Signed-off-by: roccochen@chromium.com <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78849
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 12:55:23 +00:00
Ruihai Zhou
94a2d74926 mb/google/geralt: Disable SD card support for Ciri
According to proto schematics, the SD card is removed.

BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None

Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-16 12:04:30 +00:00
Ruihai Zhou
d3089a36d5 mb/google/geralt: Move backlight-related functions to common panel.c
These backlight related functions can be reused in other variants, move
them out to the panel.c. Also the panel_geralt.c should be used for
Geralt, enable it on Geralt board only.

BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None

Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78955
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-11-16 12:04:07 +00:00
Maximilian Brune
77eaec6587 lib/device_tree.c: Fix print_property
This uses the size attribute to traverse the possible string.
This patch traverses the entire property for non printable characters
and not just until the first 0 is hit.

Now numbers that start with a zero (memory wise) are not falsely
recognized as strings:

before the patch:
clock-frequency = "";

after the patch:
clock-frequency = < 0x1c2000 >;

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I229c07b76468fe54f90fa9df12f103d7c7c2859d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-16 12:01:40 +00:00
Tyler Wang
f7f661f375 drivers: spi_flash: Add space before colon to fix coding style
BUG=none
TEST=build karis firmware pass

Change-Id: I67b4ca4c8fde795d4206eaa0b9ea9d9bfc768ac6
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-16 11:59:20 +00:00