When the FMAP cache is enabled, it cannot fail in pre-RAM stages unless
flash I/O in general doesn't work. Therefore, it is unnecessary and a
waste of binary size to also link a fallback path for this case.
Similarly, once the cache is written to CAR/SRAM/CBMEM there should be
no way for it to become magically corrupted between boot stages. Many
other parts of coreboot blindly assume that persistent memory stays
valid between stages so there is no reason why this code should link in
extra fallback paths in case it doesn't.
This saves a little over 200 bytes per affected (uncompressed) stage on
aarch64.
Change-Id: I7b8251dd6b34fe4f63865ebc44b9a8a103f32a57
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78904
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A recent security audit has exposed a TOCTOU risk in the FMAP
verification code: if the flash returns a tampered FMAP during the first
setup_preram_cache(), we will abort generating the cache but only after
already filling the persistent CAR/SRAM region with the tampered
version. Then we will fall back into the direct access path, which could
succeed if the flash now returns the original valid FMAP. In later
stages, we will just use the data from the persistent CAR/SRAM region as
long as it looks like an FMAP without verifying the hash again (because
the hash is only linked into the initial stage).
This patch fixes the issue by just calling die() immediately if FMAP
hash verification fails. When the verification fails, there's no
recourse anyway -- if we're not dying here we would be dying in
cbfs_get_boot_device() instead. There is no legitimate scenario where
it would still be possible to continue booting after this hash
verification fails.
Change-Id: I59ec91c3e5a59fdd960b0ba54ae5f15ddb850480
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78903
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The rarely-used fallback path for accessing the FMAP without a cache
currently only maps the FMAP header for the initial verify_fmap() call.
This used to be fine when we were just checking the magic number, but
with CBFS verification we may need to hash the entire FMAP.
Since this path is so rarely used anyway and the size difference only
has a practical impact on a few platforms, lets keep things simple and
just always map the whole FMAP.
Change-Id: Ie780a3662bf89637de93a36ce6e23f77fed86265
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78914
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The value from raw_read_cntfrq_el0() could be large enough to cause
overflow when multiplied by USECS_PER_SEC. To prevent this, both
USECS_PER_SEC and hz can be reduced by dividing them by their GCD.
This patch also modifies the return type of `timer_hz()` from
`uint64_t` to `uint32_t`, assuming that in practice the timestamp
counter should never be that fast.
BUG=b:307790895
TEST=boot to kernel and check the timestamps from `cbmem`
Change-Id: Ia55532490651fcf47128b83a8554751f050bcc89
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78888
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the hda_soc_ssdt_quirks function since it doesn't apply for any of
the SoCs supported by the Stoneyridge code which was the only SoC
implementing it. This code was added when commit 91a7abf25c
("soc/amd/hda: Move HDA PCI device from DSDT to SSDT") rewrote the code
originally added in commit 1587dc8a2b ("soc/amd/stoneyridge: Add
northbridge support") as a copy from northbridge/amd/pi/00670F00. This
code was moved around in commit 6580408a7e ("amd/pi/hudson: Move audio
to northbridge"), since the HDA controller was moved from the FCH to the
northbridge complex. When the controller was moved, the PCI config space
interface also changed, so those bits are no longer the DisableNoSnoop,
DisableNoSnoopOverride, and EnableNoSnoopRequest bits of the Misc
Control register of the HDA controller, but some bits within the
ClassCodeW field of the ACGAZ Mirrot Reg Ctrl 0 register.
BKDG #55072 Rev 3.04 (Stoneyridge), BKDG #50742 Rev 3.08 (family 15h
model 60h-6fh / 00670F00), and BKDG #52740 Rev 3.05 (family 16h model
30h-3fh) were used as a reference. Only the SoC with BKDG #52740 still
has the HDA controller in the FCH; the other two have it in the
northbridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77fc76752b1c7de62ba8a196f15c198f55be3074
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78940
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The builds from the configs directory were not being saved in the
junit.xml files that Jenkins uses to determine pass vs fail of the
individual builds.
This also fixes the path to a log file that I noticed while testing.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I37dbee676cc9e507e612ce66994a04aba062757a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78863
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 44a48ce7a4.
Reason for revert: It breaks wakeup from suspend on a bunch of boards.
While this approach of eyeballing "correct" values by chipset _should_
be fixed, it should also be accompanied by compile time verification
that the memory map works out.
Since nobody seems to care enough, let's just revert this, instead of
keeping the tree broken for a bunch of configurations.
Change-Id: I3cd73b6ce8b15f06d3480a03ab472dcd444d7ccc
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78850
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Now VBOOT is always assumed to run after romstage and be linked inside
romstage. This currently is the case but for flexibility reasons (e.g.
linking romstage into bootblock or having a verstage before romstage)
this could be more precise.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I361731c930a35e12245153920df1b6884d47064c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Instead of redirecting the output of sed into a temporary file and
copying it to its target then, just tell sed to do the replacements
in-place and don't let it create a backup of the original file. The
overhead is not needed.
Change-Id: I442616cd78098b653af5bd49bc7a4f021c99e081
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The value from raw_read_cntfrq_el0() could be large enough to cause
overflow when multiplied by USECS_PER_SEC. To prevent this, both
USECS_PER_SEC and tfreq can be reduced by dividing them by their GCD.
BUG=b:307790895
TEST=emerge-geralt coreboot
TEST=boot to kernel and check the timestamps from `cbmem`
Change-Id: I366667de05392913150414f0fa9058725be71c52
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78800
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After CB:78800 applied, the bootblock increases 2128 bytes and exceeded
its allotted size (40K). Therefore, we enlarge BOOTBLOCK to 44K to solve
the compilation error. This patch also increases PRERAM_CBFS_CACHE to
103K to fill the empty space (1K) between TIMESTAMP and TTB.
BRANCH=none
BUG=none
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -B
Change-Id: Iae9d44939b29098e823508dd3965a1bae7a69041
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To get tracehub working, it requires few settings such as
SOC_INTEL_METEORLAKE_DEBUG_CONSENT=2 and enable tracehub device in
dev tree. This commit binds all tracehub related settings to Kconfig,
so that users only need to enable SOC_INTEL_COMMON_BLOCK_TRACEHUB
TEST=boot on screebo and test tracehub device exists and working
Change-Id: Ie830fe2fd38e3456497bea37fe42ca60d26ca305
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add an entry in the min_pci_sleep_states array for SA_DEVFN_DPTF,
to correct warning in cbmem log:
[WARN] unknown min d_state for PCI device 00:04.0
TEST=build/boot google/brya (banshee), verify warning not present in
cbmem log, verify entry for DPTF device in ACPI LPI constraint list.
Change-Id: I2a9976b065f08e4acd31c3deca13c5278f031a90
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78877
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit 2bc9cee0f7 ("Braswell: Update the ACPI tables") switched the
SoC from using its own HPET generation code to the common x86 code, but
along the way the min_tick value got lost. Restore the original value
prior to the above commit, which is now set via a Kconfig override.
TEST=build/boot google/cyan (edgar), verify min_tick value in HPET
ACPI table is correct.
Change-Id: I2633e7cd0c3d74c1554ae8c1f2bb6387fd6dde2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78744
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, there are 3 separate settings for DPTF which are not always
in sync:
- the enabled/disabled state of the devicetree PCI device
- the 'dptf_enable' register, which sets the ACPI device status via GNVS
- the 'DptfDisable' register, which sets the FSP UPD of the same name
To make things sane, drop the two chip registers, and set the GNVS
variable and FSP UPD based on the enabled/disabled status of the DPTF
PCI device in the mainboard's devicetree.
TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI
devices are present/enabled when DPTF is enabled in devicetree, and not
present/disabled when disabled in devicetree.
Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The device name for the SA thermal/DPTF PCI device was missing from
soc_acpi_name(), leading to an invalid PLI device constraint entry
being generated in the SSDT (the name field was blank/missing).
Add the missing entry, matching the name to the existing ACPI
device.
TEST=build/boot Win11 on google/puff (wyvern) without a BSOD.
Change-Id: I7ac03fd292246981f32d9ad894b8f0f9870240fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78869
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add an entry in the min_pci_sleep_states array for SA_DEVFN_THERMAL,
to correct warning in cbmem log:
[WARN] unknown min d_state for PCI device 00:12.0
TEST=build/boot google/puff (wyvern), verify warning not present in
cbmem log, verify entry for THRM device in ACPI LPI constraint list.
Change-Id: Ide98c1b82c56ed1d34c608f9419f61c8e15d2dab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78868
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the LAN/WiFi device types from PCI to generic, so that the bogus
PCI device and function values don't end up in coreboot's internal
device tree. The presence of these bogus PCI devices cause the LPI
constraint generator to create a reference for an ACPI device which does
not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s) cause a
Windows BSOD (INTERNAL_POWER_ERROR).
TEST=build/boot Win11 on google/puff (wyvern). Verify LAN/WLAN devices
function correctly under Windows and Linux.
Change-Id: Ibc5f96250edb358d0517bd3840bf5604defe0b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).
BUG=b:305887856
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I5993049ac63520c4dfd057c38b566fc69502d825
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Change the dGPU/LAN/WiFi device types from PCI to generic, so that the
bogus PCI device and function values don't end up in coreboot's
internal device tree. The presence of these bogus PCI devices cause the
LPI constraint generator to create does a reference for an ACPI device
which does not exist (SB.PCI0.RP{xx}.MCHC). The invalid reference(s)
cause a Windows BSOD (INTERNAL_POWER_ERROR).
TEST=untested
Change-Id: Ic997b5ad893853b99ae53a2e5c7acf58467ea4f1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78873
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch calls into the function to join the MBUS if the GFX PEIM
module inside the FSP binary is taking care of graphics initialization
based on the RUN_FSP_GOP config option. The FW skips joining the MBUS
in case of a non-FSP solution and/or SOC_INTEL_GFX_MBUS_JOIN config is
not enabled.
BUG=b:284799726
TEST=MBUS joining is only applicable for google/rex while using GFX
PEIM.
Change-Id: I50d719a286722f5aafbad48ab4ca60500c836dd6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
gnatgcc is deprecated and in recent GCC releases its purpose is
fulfilled by the gcc binary. In case of a deprecated gnatgcc version is
installed, it doesn't provide the expected output and hostcc_has_gnat1()
fails. In this case, just set the value of CC to gcc.
It's still required to install GNAT in addition to GCC.
Change-Id: I730bdfda81268d10bd2a41ef5cb4e3810b76a42c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
