05e531946c
vc/amd/fsp/mendocino/platform_descriptors: fix dxio_port_param_type enum
...
The dxio_port_param_type enum was copied over from Cezanne to Mendocino,
but the enum on the AGESA/FSP side changed between the two generations.
Update the definition to match the definition used in the Mendocino FSP.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ie4c4d7e4e3eaf7af9a43007363135412633c7440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76446
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 16:48:42 +00:00
f06e993a87
nb/intel/gm45: Rework nb resource reading
...
- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Ic6f42053b5303151906360d8512b9d63dd297854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76249
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 15:35:18 +00:00
5acb1a0d0c
nb/intel/ironlake: Use newer resource declaration code
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Ie585a66118c6bd1951bd004bbccbed0ee0ba9f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76248
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 15:30:24 +00:00
0de34dc323
drivers/uart/oxpcie: Fix broken console output
...
The OxPCIe952 serial cards currently fails after entering
postcar, since the state of oxpcie_present is not maintained
from previous stage.
As a quick work-around test the expected UART register space
to see if anyone decodes the address.
Change-Id: I5601034be6e413616fb3433c894fb008a3e02138
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com >
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74597
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 15:28:39 +00:00
ca75c8f8c1
mb/system76: Fix CBFS_SIZE value
...
Change `CBFS_SIZE` to match the actual BIOS region size, as specified in
the FIT XML config.
Fixes building with `VALIDATE_INTEL_DESCRIPTOR` selected.
Change-Id: I91a46b3ed6cc3161df27eed19d8cdf2820e90d7e
Signed-off-by: Tim Crawford <tcrawford@system76.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76326
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 15:26:22 +00:00
a0bd3e9a97
mb/google: AMD: move tpm_tis to AMD common code
...
It moves cr50_plat_irq_status() to common code and adds Kconfig
option to specify GPIO used for interrupt.
BUG=b:277787305
TEST=Build all affected platform and confirm using right GPIO
number. Tested on Skyrim.
Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-07-14 15:13:33 +00:00
64335176d1
vc/amd/fsp/*/platform_descriptor: drop SoC name from DDI comment
...
The file for Mendocino and Phoenix still used Cezanne in the comment and
from the file it's already clear to which SoC generation this belongs,
so just drop the SoC name from the comment.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I73e8b01e46904578226bb64e5e4659016c491880
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76440
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 14:32:38 +00:00
1611f93a30
mb/system76/rpl: Add Adder WS 3 as a variant
...
The Adder Workstation 3 (addw3) is a Raptor Lake-HX board.
Tested with a custom TianoCore UefiPayloadPkg.
Working:
- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7
Not working:
- Discrete/Hybrid graphics
- Thunderbolt
Change-Id: I165a434fe18f8c0aac49cb872bb87f98551d8f2c
Signed-off-by: Jeremy Soller <jeremy@system76.com >
Signed-off-by: Tim Crawford <tcrawford@system76.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 14:31:45 +00:00
53c6eea2d4
soc/intel/adl: Add Raptor Lake-HX definitions
...
Tested by booting System76 Adder WS 3 (addw3) and Serval WS 13 (serw13)
to edk2 payload and then OS.
Ref: Intel Raptor Lake EDS, Volume 1 (#640555 , rev. 2.8)
Change-Id: I6098e9121a3afc4160c8a0c96d597e88095fd65d
Signed-off-by: Tim Crawford <tcrawford@system76.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-07-14 14:31:24 +00:00
0bde1829e7
drivers: mipi: Fine tune STA_ILI9882T panel HBP and HFP
...
coreboot logs the error below, since the value of hporch is too small. Increasing hbl from 80 to 174, and hso from 40 to 72 to revise the HBP(Horizontal Back Porch) and HFP(Horizontal Front Porch). After revising this, the actual measurement frame rate is 60.1Hz.
[ERROR]HFP plus HBP is not greater than d_phy, the panel may not work
properly.
BUG=b:284812193
TEST=cbmem -c | grep "ERROR" and measure frame rate
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com >
Change-Id: I7de5984ce8aec12d8ebe292974e05776835330d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76218
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Yidi Lin <yidilin@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 14:30:00 +00:00
d5e336720d
util/lint/checkpatch_json.py: Make output message verbatim
...
Some of the error messages of checkpatch.pl contain "*". Since now
Gerrit supports markdown, messages with "*" will be rendered
incorrectly. For example,
foo* bar should be foo *bar
will be shown as
foo bar should be foo bar
with "bar should be foo" being in italics. Fix the problem by
surrounding the output message with "`" to make it verbatim.
Change-Id: I02d0e894adf7f94a9e154f99321f51d4097963a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76392
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yidi Lin <yidilin@google.com >
2023-07-14 14:29:48 +00:00
d1d17908fa
vc/intel/fsp/mtl: Update the MemInfoHob header to FSP version 3251.81
...
This patch updates the MemInfoHob header file as per Meteor Lake
version 3251.81.
Changes include:
1. Drop DimmDFE structure variable
2. Drop unused macro MAX_COPY_DIMM_DFE_TAPS
BUG=b:290898626
TEST=Able to build and boot google/rex.
w/o this patch:
cbmem -c -1 | grep DIMM
[ERROR] No DIMMs found
w/ this patch:
cbmem -c -1 | grep DIMM
[DEBUG] 8 DIMMs found
Change-Id: I8eed410831399bb4835244f48c14d5ed9e701e68
Signed-off-by: Subrata Banik <subratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76433
Reviewed-by: Dinesh Gehlot <digehlot@google.com >
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-14 05:52:13 +00:00
7a66715ad4
soc/mediatek/common/dsi: Add actual values to the log messages
...
Per the suggestion in CB:76218, print actual values to the error
messages, which may be helpful for debugging.
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com >
Change-Id: Id3a7a8c76b6ad15e7cf71225d8529f3e034935ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76442
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2023-07-14 03:11:53 +00:00
afcd48a2f1
vc/amd/phoenix/platform_descriptor: clarify link_compliance_mode comment
...
When set to 1, the link_compliance_mode element of the DXIO port
descriptor will cause the corresponding PCIe port to not be trained but
to output a compliance testing pattern instead. Update the comment to
point out that this is only a testing mode.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Iaabb16c51a0c08391cd2d63b8064c524a748ccb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76441
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
2023-07-14 03:06:07 +00:00
2f7c7e8a77
mb/google/rex/var/screebo: Configure CNVi GPIO IO Standby State
...
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=b:286803481
TEST=Make screebo suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-13 16:38:13 +00:00
d19ebe0bd5
soc/intel: Rename pcr.asl to pch_pcr.asl
...
The PCR (Private Configuration Register) is applicable to access the
P2SB register space starting with the Intel SkyLake generation of SoC.
Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside
the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in
SoC die (same as PCH die for U/H SoC) and another in IOE die.
This patch renames pcr.asl to pch_pcr.asl to reflect the actual source
of the P2SB IP in the die (i.e., SoC die or PCH die).
BUG=b:290856936
TEST=Able to build and boot google/rex.
Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04
Signed-off-by: Subrata Banik <subratabanik@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Kapil Porwal <kapilporwal@google.com >
2023-07-13 16:37:56 +00:00
c7b27b3ad6
acpi: Reserve hardware IDs for custom Intel GMBus I2C driver
...
GMBus is an I2C compatible link on Intel IGPUs. Most non-Linux OS's
don't support accessing this ordinarily, so a custom driver is
needed with a bit of ACPI hackery. Reserve 2 IDs from the
coreboot namespace so that the 2 devices required can be populated
in Windows device manager
Change-Id: I389612441e96ce2fc5e006051e523661953eba6e
Signed-off-by: CoolStar <coolstarorganization@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
2023-07-13 16:37:21 +00:00
43169fe86d
soc/intel/braswell: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I4769f79c67c372e11bb267de3acec0920d7ab0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
2023-07-13 14:14:21 +00:00
d821c7267f
soc/intel/baytrail: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I80c8a1b58e8102ed11e22b74f30750d5a6c4eae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76283
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-13 14:13:26 +00:00
a5935c6307
mb/google/nissa/var/pujjo: Add WWAN EM060 power on sequence
...
Pujjo support WWAN EM060 device, use FW_CONFIG to handle the
power on sequence.
BUG=b:290709711
TEST=Build and check WWAN EM060 power on sequence.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com >
Change-Id: I66800c75274e8e1e55d4314c82b7fcdf2a4477bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76403
Reviewed-by: Derek Huang <derekhuang@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-13 13:16:17 +00:00
dd792f2dc5
MAINTAINERS: Add entry for Cannon Lake
...
Cannon Lake, which covers Coffee Lake and Comet Lake, has been missing
from the maintainers file. Most unmerged patches for it have recently
been abandoned after 2+ years of inactivity.
Change-Id: Ic381f8efc4a423dca83c36605002aeeabf4bfdd9
Signed-off-by: Tim Crawford <tcrawford@system76.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-07-13 13:15:01 +00:00
b6940dfdae
mb/siemens/mc_ehl4: Change GPIO GPP_B5 polarity for DRAM population
...
With the latest hardware revision, the polarity of GPP_B5 has been
changed. For a full-populated DRAM configuration, the input signal is
now connected to 3.3 V and for a half-populated configuration it is
connected to ground.
BUG=none
TEST=Use different populated mainboards and check coreboot log
GPP_B5 = 0:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
GPP_B5 = 1:
[DEBUG] 2 DIMMs found
Change-Id: Iaa3a63fa52c802d8f5d8c6cc11dd6edfac117e88
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76434
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Jan Samek <jan.samek@siemens.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-13 10:42:53 +00:00
7ecc366470
mb/google/nissa/var/uldren: Modify reset_delay_ms for EKTH7D18
...
Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18.
BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.
Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417
Reviewed-by: Derek Huang <derekhuang@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-07-13 08:28:23 +00:00
3708f54bb5
soc/intel/alderlake: Disable hwp scalibility tracking
...
Disable scalability tracking for autonomous frequency control in
order to improve power and performance.
BUG=b:280021171
TEST=Boot to OS on brya0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2023-07-13 01:06:09 +00:00
6e64c01d08
soc/intel/alderlake: Hook up UPD EnableHwpScalabilityTracking
...
Hook the newly exposed EnableHwpScalabilityTracking UPD up so that
boards can configure is via devicetree.
BUG=b:280021171
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Change-Id: I4c8845c445d46caa30a0245386ab9cd690d2623f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74722
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Sean Rhodes <sean@starlabs.systems >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2023-07-13 01:05:52 +00:00
7d1a037f88
soc/intel/alderlake: Hook up UPD DisableSagvReorder
...
Hook the newly exposed DisableSagvReorder UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Change-Id: I89235d9384b67f03e68425aadd3458e1c77ff555
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Sean Rhodes <sean@starlabs.systems >
2023-07-13 01:05:35 +00:00
6a6550be4f
soc/intel/alderlake: Disable SaGV reordering
...
Disable re-ordering SaGv point on warm reset so that most
performant SaGv point is picked after memory training and
boot time is reduced.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Change-Id: I44a1c054d52bb8585a320bb8a52a8f137e639804
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74721
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-13 01:05:06 +00:00
4ee03dc445
soc/intel/alderlake: Reduce memory test size
...
Enable upd to reduce size of the memory test.
BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-07-13 01:04:49 +00:00
433343eaaa
soc/intel/alderlake: Hook up UPD LowerBasicMemTestSize
...
Hook the newly exposed LowerBasicMemTestSize UPD up so that
boards can configure is via devicetree.
BUG=b:268546941
TEST=Verified by enabling/disabling the UPD on google/brya
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Change-Id: Ib813e9f3b7419a3cb54b4e176dcc5cc74a783dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74718
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Sean Rhodes <sean@starlabs.systems >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
2023-07-13 01:04:37 +00:00
0cc560fd3c
vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4221.00
...
The headers added are generated as per FSP v4221.00
BUG=b:290038558
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com >
Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76147
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Sean Rhodes <sean@starlabs.systems >
2023-07-13 01:03:33 +00:00
0cb5eace6c
soc/intel/common: Restore to page 0 before reading SPD
...
test: Warm reboot from Windows 11 w/ Samsung 980 Pro on Banshee
Verify memory type detected properly and following boot works
Change-Id: Iad0a2024bd0ef39f6ab57ff7a6e6aa651d7882a6
Signed-off-by: CoolStar <coolstarorganization@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2023-07-12 17:52:05 +00:00
3e52d7955f
mb/ibm/sbp1: Disable SIO Uarts
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Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead.
TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC
console. Also made sure coreboot logs are accessible via VUART.
Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2023-07-12 15:01:02 +00:00
ce3c77c305
mb/ibm/sbp1: Set coreboot ready GPIO in BS_PAYLOAD_BOOT
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Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS
completion.
Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-12 15:00:25 +00:00
211e391a82
mb/{google, intel}: Enable PCH Energy Reporting for MTL platforms
...
This patch enables PCH to CPU energy report feature which can be used
by Intel Telemetry Driver.
BUG=b:269563588
TEST=Able to build and boot google/rex and perform below check to ensure
the energy reporting is correct
w/o this cl:
# lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXX0000
w/ this cl:
#lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXXfc004
Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
2023-07-12 14:10:54 +00:00
b2b18e1064
intelblocks/cpu/mp_init: Add missing ADL-S SKUs to CPU match table
...
Only A step ADL-S CPUs were added to CPU table for MP init. Add
the remaining ADL-S CPUs to the table.
TEST=Boot MSI PRO Z690-A with C step i5-12600K and observe coreboot
no longer uses generic CPU ops.
Change-Id: I3692a3f089ca23af860bd1c8e3c29fee9d9234c9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76204
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-07-12 13:59:23 +00:00
8dc16a9ce2
soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset name
...
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2023-07-12 13:56:32 +00:00
1aa5caf2ac
soc/intel: Fix W790 chipset name
...
In newer ADL/RPL PCH EDS 619362 revision 2.1 the ESPI ID 0x7A8A
belongs to the W790 chipset. Earlier revisions had the chipset with
ID 0x7A8A named W685, which was probably just a temporary name.
Change the naming throughout the tree to W790, which is the real
existing chipset.
Change-Id: I87603298d655e9bf898b34acdd5b403f5affaee3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Crawford <tcrawford@system76.com >
2023-07-12 13:55:35 +00:00
d54a5b294f
treewide: Drop the suffixes from ADL and RPL CPUID macros and strings
...
CPUID is the same for Alder Lake and Raptor Lake S and HX variants.
To reduce the confusion and concerns how to name the macros, remove
the suffixes from macros and platform reporting strings. Thankfully
the stepping names are unique across mobile (P suffixed) and desktop
(S and HX suffixed) SKUs. Distinguishing the S from HX is possible via
host bridge PCI ID.
Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Crawford <tcrawford@system76.com >
2023-07-12 13:53:40 +00:00
573e6ded9f
soc/intel/alderlake: Add support for Raptor Lake S CPUs
...
Add PCI IDs, default VR values and power limits for Raptor Lake S
CPUs. Based on docs 639116 and 640555.
TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu
22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P
with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04.
Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155
Signed-off-by: Max Fritz <antischmock@googlemail.com >
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798
Reviewed-by: Tim Crawford <tcrawford@system76.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com >
2023-07-12 13:52:16 +00:00
5787bd21c7
security/vboot/secdata_tpm: Simplify antirollback_read_space_firmware()
...
The static function read_space_firmware() is used only once, so merge it
into antirollback_read_space_firmware(). Also change a debug log to
error.
BUG=none
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I8abcb8b90e82c3e1b01a2144070a5fde6fe7157f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Yidi Lin <yidilin@google.com >
2023-07-12 13:41:07 +00:00
ffe2ced6e4
mb/google/geralt: Initialize I2C bus for TPS65132 in mainboard
...
The CB:76219 removed mtk_i2c_bus_init() from tps65132s_setup(), so
we should initialize I2C bus for TPS65132 in mainboard now.
BUG=None
TEST=./util/abuild/abuild -t google/geralt -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com >
Change-Id: Iacf78221d2416f41467c709402b7e02e03dc5fc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2023-07-12 13:40:26 +00:00
1dadb8c01d
soc/intel/adl: Reduce microcode redundancy
...
Some of the microcode update files listed in the Makefile are redundant:
* 06-97-02 is exactly the same as 06-97-05
* 06-9a-03 is completely contained in 06-9a-04 (at offset 0x1c400)
So drop these files. This saves us about 200KiB CBFS space in each case.
Change-Id: Idfcab1de26ea4712295c1d22790bab3a73c17f93
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-07-12 13:40:01 +00:00
74add29738
cpu/amd/mtrr: Use newer function for resource declaration
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I62f34a12bc5c4807638ddcb39fa5e450d99511fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76277
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-12 10:51:49 +00:00
fdc1b541ae
soc/amd/common: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Iad8b7c705d5053700850065f90314444904b5b54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76289
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com >
2023-07-12 10:15:26 +00:00
6df8ba45e0
mb/emulation/*: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Idd623e99ee20ad94e493c8560cfdac9f7baaf890
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76281
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-12 09:33:53 +00:00
0a60d10954
soc/intel/*/pmc.c: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I852d6daebdcb8461c18e7c0eaf1c54ad7c59c0c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
2023-07-12 09:31:17 +00:00
d5e70b2131
soc/intel/common: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: If7fe96220ce5b13f5541e25935afd0c681ff40f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76286
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-12 09:30:47 +00:00
899acf19bf
soc/intel/apl: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I5728dc144b0d04a92a1e0a4b9abbe17ef0a06e41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76282
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Sean Rhodes <sean@starlabs.systems >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-12 09:15:08 +00:00
32867e77f1
soc/intel/broadwell: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: Ie44518988e999794fba35f41075ff62e82663d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76285
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-12 09:14:16 +00:00
e05693e938
pc80/tpm: Use newer function for resource declarations
...
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Change-Id: I40b8482f41e8fece55fd60fec7ec3f63f83bd030
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76280
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-07-12 09:12:37 +00:00
