Commit Graph

26 Commits

Author SHA1 Message Date
Furquan Shaikh
0f007d8ceb device: Constify struct device * parameter to write_acpi_tables
.write_acpi_tables() should not be updating the device structure. This
change makes the struct device * argument to it as const.

Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28 19:21:49 +00:00
Angel Pons
4b42983c7a src/northbridge: Use SPDX for GPL-2.0-only files
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Id2cb642baa764fd69543460ba869cd822ab5acad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-05 17:44:14 +00:00
Patrick Georgi
f3f36faf35 src (minus soc and mainboard): Remove copyright notices
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
  copyright holder?
- People sometimes have their editor auto-add themselves to files even
  though they only deleted stuff
- Or they let the editor automatically update the copyright year,
  because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?

Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.

Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-17 18:26:34 +00:00
Elyes HAOUAS
8247cc3328 northbridge: Remove unused include <device/pci.h>
Change-Id: I942457a820a59428f7ae302262c4891a4c5ef1a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37520
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06 17:27:10 +00:00
Elyes HAOUAS
748caed022 northbridge: Add missing include <device/pci_def.h>
Change-Id: Ib63835d2407bbabbd78b43927f7fbd407ca06a08
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37841
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-31 07:42:30 +00:00
Arthur Heymans
08456363f2 nb/intel/gm45: Don't create DMAR tables for disabled IGD
Change-Id: Ia9b74cfb8b68240e87d7adfa28d37db408edb519
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-13 10:50:51 +00:00
Arthur Heymans
15063e8819 nb/intel/gm45/acpi.c: Don't read PCI config to check presence
Change-Id: I4cac29c1bf59df56df8cf0035ee1d5379bbde76e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-13 10:50:27 +00:00
Elyes HAOUAS
a1e22b8192 src: Use 'include <string.h>' when appropriate
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.

Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-20 20:27:51 +00:00
Kyösti Mälkki
f1b58b7835 device/pci: Fix PCI accessor headers
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01 20:32:15 +00:00
Kyösti Mälkki
c70eed1e62 device: Use pcidev_on_root()
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06 01:17:54 +00:00
Elyes HAOUAS
1f4cb326fa northbridge: Remove useless include <device/pci_ids.h>
Change-Id: Ie221a142ed804988a05269d42904aba3ac79e0be
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19 05:21:38 +00:00
Elyes HAOUAS
8a5283ab1b src: Remove unneeded include <cbmem.h>
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16 10:56:47 +00:00
Elyes HAOUAS
ead574ed02 src: Get rid of duplicated includes
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-16 09:50:03 +00:00
Elyes HAOUAS
d2b9ec1362 src: Remove unneeded include "{arch,cpu}/cpu.h"
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-12 09:22:18 +00:00
Matt DeVillier
7866d497ad arch/x86/acpi: Add DMAR RMRR helper functions
Add DMAR RMRR table entry and helper functions, using the existing
DRHD functions as a model. As the DRHD device scope (DS) functions
aren't DRHD-specific, genericize them to be used with RMRR tables as
well. Correct DRHD bar size to match table entry in creator function,
as noted in comments from patchset below.

Adapted from/supersedes https://review.coreboot.org/25445

Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27269
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-30 09:02:56 +00:00
Elyes HAOUAS
6dcdaaf205 nb/intel/gm45: Get rid of device_t
Use of `device_t` has been abandoned in ramstage.

Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30 09:22:04 +00:00
Damien Zammit
88af372fe8 nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfaces
Previously the ME PCI interface (HECI) was being reported as present in
the DMAR ACPI table even when ME firmware was missing or the PCI device
was hidden and HECI would be unresponsive.
Now we check via the PCI config space itself to verify if the HECI
is present or not.

Note that this test could fail if ME firmware is present but
HECI is disabled in devicetree, because it would not advertise that the HECI
exists even though there is a running ME.  Perhaps this behaviour is desirable
because in this case you won't see the HECI in the lspci tree anyway.

Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16330
Tested-by: build bot (Jenkins)
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09 17:11:44 +02:00
Aaron Durbin
07a1b281a8 x86 acpi: remove ALIGN_CURRENT macro
The ALIGN_CURRENT macro relied on a local variable name
as well as being defined in numerous compilation units.
Replace those instances with an acpi_align_current()
inline function.

Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12707
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15 20:12:01 +01:00
Nico Huber
e561f35fa5 ACPI: Make DMAR flags settable
Add a parameter to acpi_create_dmar() for the flags field and define
flags given by the spec [1].

[1] Intel Virtualization Technology for Directed I/O
    Architecture Specification
    Document-Number: D51397

Change-Id: I03ae32f13bb0061bd3b9bef607db175d9b0bc5e1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12191
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-04 16:14:06 +01:00
Patrick Georgi
a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Martin Roth
4a666423c6 northbridge/intel/gm45/Kconfig: Remove IOMMU symbol choice
In the gm45 code, IOMMU is always selected to be enabled.  Instead
this patch removes the Kconfig symbol and its dependencies.  This leads
to the same effect without the need for the symbol.

The symbol is still used in the K8 code as it's not selected, simply
defaulted to being enabled, and one of the mainboards disables it.

Change-Id: Ibc5939cd1e297d497bf71b1787d852f7cc09a551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11345
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-08-31 22:02:17 +00:00
Alexander Couzens
83fc32f7a7 device_ops: add device_t argument to write_acpi_tables
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.

Change-Id: I1ba4bfa0ac36a09a82b108249158c80c50f9f5fd
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9599
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05 21:12:11 +02:00
Patrick Georgi
b890a1228d Remove address from GPLv2 headers
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.

However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.

util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.

$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
	-a \! -name \*.patch \
	-a \! -name \*_shipped \
	-a \! -name LICENSE_GPL \
	-a \! -name LGPL.txt \
	-a \! -name COPYING \
	-a \! -name DISCLAIMER \
	-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +

Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21 20:50:25 +02:00
Vladimir Serbinenko
8d70e94ae1 Make acpi_fill_dmar into parameter
Change-Id: I5e237cb7acbf47b2c8a4cd725ee8e16e422e3b17
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7371
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-27 20:37:58 +01:00
Vladimir Serbinenko
33769a5caa gm45: Convert to per-device ACPI
Change-Id: Ib04b03b2dc2ad3bfa886b43df9dd6518bbb46e3f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6803
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-15 10:54:27 +02:00
Patrick Georgi
2efc8808b8 intel/gm45: new northbridge
The code supports DDR3 boards only. RAM init for DDR2 is sufficiently
different that it requires separate code, and we have no boards to
test that.

Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1689
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-27 09:16:18 +01:00