0f007d8ceb
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
121 lines
3.0 KiB
C
121 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <types.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include "gm45.h"
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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struct device *dev;
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u32 pciexbar = 0;
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u32 pciexbar_reg;
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int max_buses;
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dev = dev_find_device(0x8086, 0x2a40, 0);
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if (!dev)
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return current;
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pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
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// MMCFG not supported or not enabled.
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if (!(pciexbar_reg & (1 << 0)))
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return current;
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switch ((pciexbar_reg >> 1) & 3) {
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case 0: // 256MB
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
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max_buses = 256;
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break;
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case 1: // 128M
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
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max_buses = 128;
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break;
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case 2: // 64M
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pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
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max_buses = 64;
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break;
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default: // RSVD
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return current;
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}
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if (!pciexbar)
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return current;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
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pciexbar, 0x0, 0x0, max_buses - 1);
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return current;
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}
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static unsigned long acpi_fill_dmar(unsigned long current)
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{
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const struct device *dev;
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dev = pcidev_on_root(3, 0);
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int me_active = dev && dev->enabled;
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dev = pcidev_on_root(2, 0);
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int igd_active = dev && dev->enabled;
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int stepping = pci_read_config8(pcidev_on_root(0, 0),
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PCI_CLASS_REVISION);
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1);
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current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0);
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acpi_dmar_drhd_fixup(tmp, current);
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if (stepping != STEPPING_B2 && igd_active) {
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tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2);
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current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0);
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current += acpi_create_dmar_ds_pci(current, 0, 0x2, 1);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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if (me_active) {
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tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE3);
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current += acpi_create_dmar_ds_pci(current, 0, 0x3, 0);
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current += acpi_create_dmar_ds_pci(current, 0, 0x3, 1);
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current += acpi_create_dmar_ds_pci(current, 0, 0x3, 2);
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current += acpi_create_dmar_ds_pci(current, 0, 0x3, 3);
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acpi_dmar_drhd_fixup(tmp, current);
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}
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current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4);
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/* TODO: reserve GTT for 0.2.0 and 0.2.1? */
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return current;
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}
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unsigned long northbridge_write_acpi_tables(const struct device *device,
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unsigned long start,
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struct acpi_rsdp *rsdp)
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{
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unsigned long current;
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acpi_dmar_t *dmar;
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current = start;
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printk(BIOS_DEBUG, "ACPI: * DMAR\n");
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dmar = (acpi_dmar_t *) current;
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acpi_create_dmar(dmar, 0, acpi_fill_dmar);
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current += dmar->header.length;
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current = acpi_align_current(current);
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acpi_add_table(rsdp, dmar);
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current = acpi_align_current(current);
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printk(BIOS_DEBUG, "current = %lx\n", current);
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return current;
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}
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