Add a new driver to support reading a board serial number from
a text file in CBFS and injecting into the SMBIOS tables.
Allow driver to be selected at the .config level and not require
inclusion at the board level.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: Ieae39f39ab36e5b1f240383b7cf47681d9a311af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Revert two of the changes made in
"arch|cpu/x86: Add Kconfig option for x86 reset vector"
I6a814f7179ee4251aeeccb2555221616e944e03d
The Intel FIT pointer and the ID section should be offsets from the
top of flash, and aren't inherently tied to the reset vector or to
bootblock.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I2c9d5e2b2c4248c999d493a72d90cfddd92197cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The APOB NV region holds the save data for resuming. Omit it if the
mainboard doesn't use HAVE_ACPI_RESUME.
The APOB information will also be board-specific so remove the
default values.
Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update Eve's VBT from v211 to v221, and change the backlight
control type from PWM to VESA eDP/AUX. This allows the OS to
select the proper backlight control type for the panel.
Test: Eve backlight control now functional under Windows 10
(Linux requires some pending patches to fix)
Change-Id: I8be2a719765891b3f2702c1869981009fa73ca05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch makes below clean-up for report_cpu_info() function.
1. Remove unused variables.
3. Reuse fill_processor_name.
TEST = Successfully able to boot hatch and verify the
cpu_name "CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz"
Change-Id: I41c76eb93f0c5229c4a49ab041339b6ad51ad24a
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like TCO
configuration and SMBus init into romstage/pch.c in order to maintain only
required chipset programming for bootblock and verstage.
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=Able to build and boot hatch successfully.
Change-Id: Idf7b04edc3fce147f7857561ce7d5b0cd05f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch renames pch_init function to bootblock_pch_init and
romstage_pch_init according to the stage it is defined in.
TEST=Able to build and boot soraka successfully.
Change-Id: Idf7b04edc3fce147f7957561ce7d5a0cd05f53fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Unlike other Panther Point boards, the ga-b75m-d3h lacks definitions
to wire SuperSpeed-capable ports to XHCI in its devicetree, causing
these ports being wired to the second EHCI, and only working as USB
2.0 ports. The missing register definitions are added to fix that.
Tested on my ga-b75-d3v board.
Change-Id: Ida4de26f1a493ead83065b1ab27c0c684a074513
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Running the x86_64 qemu mainboard target with '-accel kvm' results in hang,
as the 'D' and 'A' bits needs to be set in read only page tables.
Tested on QEMU Q35: Boots into payload with '-accel kvm'.
Change-Id: I4beae8deec6bf34f9762e7b54c5da4e5b63f6d24
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c',
following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
If the board doesn't provide VRconfig in devicetree make sure to use
the lookup table for IccMax instead of defaults for some mobile SoC.
Also use decimal values instead of hex.
Change-Id: If31063f9b483a3bbd6cc90df1c1b76b4efc66445
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37598
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_H3 gpio config for easier review. This
toggles the MAX amp which not all boards have. Move the pin
configuration to boards with the respective devicetree configuration
following on from the theme of commit b417786525.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: Iefd2223af79a13c8a42d07bc10b2772dbff6d3e5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_C15 group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I578245e24895d361d80ad016a4f18204e2b6e1ca
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The baseboard GPIO table definitions are too straineous to the extend
that variants need to redefine assumptions back to NC. Invert this so
that baseboard by default assumes the safer NC and move the specific
board configurations to their respective places.
This patch handles the GPP_A* group for easier review.
BUG=b:142094759
BRANCH=none
TEST=builds
Change-Id: I29b4323ac80b1288b2562846217c4f377714fc2c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Generally work towards a more loose baseboard definition by moving out
some original assumptions to be board specifics. Specifically Puff does
not have the MAX98357A speaker amp and enabling the driver winds up
generating incorrect SSDT tables that confuse the kernel. Since
devicetree inherits the chip from device node in base and an override
will also inherit the chip and thus dispatch the unwanted fill_ssdt fn
call.
V.2: lean on linker to drop max98357a driver when not in dt.
BRANCH=none
BUG=b:146519004
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I8e7fed69a4c6d9610ac100da6bae147828ebfa81
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37909
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Two things here:
i. ) FSP requires that function 0 be enabled whenever any non-zero
functions hang under the same bus:device.
ii.) FSP reorders function 6 RP to be function 0 if function 0 is
indeed unused.
BUG=b:146437819
BRANCH=none
TEST=none
Change-Id: I0f499a23495e18cfcc712c7c96024433a6181a4c
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Make use of introduced SSDT config mode access
* Make use of introduced SSDT mutex
* Provide ACPI functions to safely access SIO config space
* Implement method to query LDN enable state
* Implement method to set LDN enable state
* Use introduced functions to implement _DIS and _STA in the device
* Update documentation
Tested on Aspeed AST2500 and Linux 5.2.
Manually verified ACPI code that generates no errors in Linux.
Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
As discussed in CB:35077, since both measured boot and verified boot
depends on vboot library, it had better to introduce a dedicated flag
CONFIG_VBOOT_LIB to control the building and linking of the vboot
library, and make other flags needing vboot library select it. Only
the actual verification stuff should be conditional on CONFIG_VBOOT.
Change-Id: Ia1907a11c851ee45a70582e02bdbe08fb18cc6a4
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB
and heap size to be minimum 128 KiB.
Updating both Kconfig to meet size requirements.
Also updated required CAR region size during boot block due to increment
in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The delay cell result should use DDR clock PLL rate for computation,
and should not be divided by 2.
This helps to improve DRAM stability.
BUG=b:80501386,b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Idf5cce206e248bb327f9a7d27c4f364ef1c68aa1
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
