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Author SHA1 Message Date
Anand Vaikar
6b6872bdd5 mb/amd/mayan: Update DXIO descriptors per schematics 
Change-Id: I8b536f8a1ff4eab06f37aec0f25704525dc1b64e
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-04-26 20:06:16 +00:00
EricKY Cheng
09eab1f1a4 mb/google/skyrim/var/winterhold: Change to read the eMMC clkreq instead 
Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMC clkreq signal instead.

BRANCH=none
BUG=b:274377518
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.

Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2023-04-26 18:23:00 +00:00
Ashish Kumar Mishra
2ee716227e intel/mtl: Add get_cse_ver_from_cbfs function 
This patch implements helper function get_cse_ver_from_cbfs() to
retrieve the CSE Lite version from CBFE RW's metadata and calls
the helper function from cse_check_update_status()

TEST=Verified CSE Lite version in coreboot boot log

Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
 2023-04-26 17:23:32 +00:00
Martin Roth
627f4c5deb mb/google/skyrim: Disable unused SPI ROM types 
By default, coreboot includes support for all the different types of SPI
ROMs.  Excluding the unused ROM types shrinks ramstage by almost 4k.

BUG=b:267735039
TEST=Build & Boot ROM
BRANCH=Skyrim

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72769
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
 2023-04-26 17:12:40 +00:00
Matt DeVillier
b1e1b2ce08 soc/amd/common/block/gfx: Re-add signature check for vbios cache 
Commit c7b8809f155a ("soc/amd/common/block/gfx: Use TPM-stored hash
for vbios cache validation") replaced checking the vbios signature
(first two bytes) with checking against a TPM-stored hash, but there
exists an edge case where the empty cache can be hashed and therefore
never updated with the correct vbios data. To mitigate this, re-add
the signature check to ensure that an empty cache will never be hashed
to TPM.

BUG=b:255812886

BRANCH=skyrim

TEST=build/boot skyrim w/selective GOP enabled, flash full firmware
image, ensure GOP driver is run until cache updated with valid data
and hashed to TPM.

Change-Id: Id06a8cfaa44d346fb2eece53dcf74ee46f4a5352
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2023-04-26 17:11:14 +00:00
Arthur Heymans
26c571cff9 sb/intel/sleepstates.asl: Use variable to enable sleepstates 
In order to make supported sleep states a runtime configuration option
use a variable. A follow-up patch will implement updating this variable
based on an SSDT generated IntObj.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6910c2c75e668e6f75a6f431813edeb59d52dd93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
 2023-04-26 15:41:12 +00:00
Arthur Heymans
cbc5d3f34b soc/intel: Don't report _S1 state when unsupported 
Since skylake Intel hardware does not support this sleep state. Trying
to enter S1 by having the OS enter sleep results in a system hang on at
least Alder lake (prodrive/atlas).

CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices
support 'skylake style' PMC PCI device for ACPI registers.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2023-04-26 15:41:03 +00:00
Joey Peng
1dc55aa35e mb/google/brya/var/taeko: remove rtd3 for emmc 
Remove rtd3 for emmc device on taeko

BUG=b:271003060
TEST= emerge-brya coreboot, flash to DUT and can boot to OS

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2023-04-26 15:14:23 +00:00
Joey Peng
f63c7222be mb/google/brya/var/taniks: remove rtd3 for emmc 
Remove rtd3 for emmc device on taniks

BUG=b:271003060
TEST=emerge-brya coreboot, flash to DUT and can boot to OS

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2023-04-26 15:14:18 +00:00
Jon Murphy
fd7f51546e mb/google/myst: Enable tis_plat_irq_status 
This will fix:
> [INFO ]  Probing TPM I2C: tis_plat_irq_status() not implemented,
wasting 20ms to wait on Cr50!

BUG=b:277297687
TEST=builds

Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-04-26 12:15:41 +00:00
Jon Murphy
0f1826e251 mb/google/myst: Configure WLAN 
Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN.  Mapping derived from myst schematic.

BUG=b:275965982
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5059be0bc011978e74ab4245e6ae037aa177ef9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-04-26 12:14:54 +00:00
Jon Murphy
462ccbaac2 mb/google/myst: Enable PCIe devices in devicetree 
Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.

BUG=b:275960920,b:276744321
TEST=builds

Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-04-26 12:11:54 +00:00
Mario Scheithauer
3362773a5b mb/siemens/mc_ehl4: Enable SD card 
This mainboard has SD slot available and therefore it should be enabled.
Use the same SD card configuration as for mc_ehl2 mainboard.

Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2023-04-26 12:11:08 +00:00
Mario Scheithauer
1dff52556e mb/siemens/mc_ehl4: Switch RTC type and connection 
This mainboard has the RTC RV-3028-C7 connected to the I2C1.

TEST:
- Console Log shows no errors for RV-3028-C7 during I2C1 init
- Finalize device for I2C 00:52 shows correct date and time

Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-04-26 12:09:28 +00:00
Mario Scheithauer
e5eb75b9c0 mb/siemens/mc_ehl4: Adjust USB settings 
Correct the USB settings, suitable for this mainboard.

Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74651
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-04-26 12:08:56 +00:00
Mario Scheithauer
26ad425728 mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes 
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default
value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to
'0'. On this mainboard NC FPGA is connected to PCIe root port #1
(00:1c.0).

Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2023-04-26 12:08:07 +00:00
Mario Scheithauer
ae5852bd7b mb/siemens/mc_ehl4: Adjust GPIOs 
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must
be adjust according to the circuit diagram for this mainboard.

Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2023-04-26 12:07:21 +00:00
Dtrain Hsu
87389bcb5e mb/google/brya/var/omnigul: Disable Tccold Handshake 
The patch disables Tccold Handshake to prevent possible display
flicker issue for Omnigul board. Please refer to Intel doc#723158
for more information.

BUG=b:279539826
BRANCH=firmware-brya-14505.B
TEST=Verify the build for Omnigul board

Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-04-26 12:06:03 +00:00
Sean Rhodes
854bd492fc mb/{system76,msi}: Enable PchHdaAudioLinkHdaEnable via devicetree 
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iae2dc0a934f0ea3ca59d8a811f1daeedb090a7bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
 2023-04-26 12:05:42 +00:00
Fred Reitberger
d45402a55a soc/amd/phoenix/Kconfig: Update comment 
Fix copy-paste comment on closing endif

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9671a9228c304988eb3903391f74a21d80d0a8bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2023-04-26 12:04:58 +00:00
Kyösti Mälkki
3454367d64 AMD binaryPI: Use ACPI_COMMON_MADT_IOAPIC 
Change-Id: I799f61d13f7ae3ea753869ded282c14ed566793a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:06:40 +00:00
Kyösti Mälkki
8eac12fa7d soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC 
For the first IOAPIC, use the common MADT generator with
default IRQ overrides.

Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:06:10 +00:00
Kyösti Mälkki
304f8387fe soc/amd: Use ACPI_COMMON_MADT_IOAPIC 
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).

Change-Id: I2de941071fca6f7208646a065a271fbf47ac2696
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74354
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:05:09 +00:00
Kyösti Mälkki
1f9e24052a asus/p2b, emulation/qemu-i440fx: Use ACPI_COMMON_MADT_IOAPIC 
For uni-processor platforms, with SMP=n or MAX_CPUS=1,
neither the LAPIC or IOAPIC MADT entries are added.

Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:04:46 +00:00
Kyösti Mälkki
ac61a65fef aopen/dxplplusu: Use ACPI_COMMON_MADT_IOAPIC 
IRQ override from IRQ #0 to GSI #2 is changed from
MP_BUS_EISA to MP_BUS_ISA.

Change-Id: I115df037fd79e120b04e6aff9e53f963f045b997
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:04:08 +00:00
Kyösti Mälkki
6437409b76 soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPIC 
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).

Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:03:40 +00:00
Kyösti Mälkki
81dc352032 intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC 
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).

Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:03:13 +00:00
Kyösti Mälkki
7f8e2a6a4a sb/intel: Use ACPI_COMMON_MADT_IOAPIC 
i82801gx, i82801ix, i82801jx:
Maintain IRQ #0 to GSI #2 override as positive edge trigger.

ibexpeak, emulation/qemu-q35:
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).

Change-Id: Ia8a04daf3a79d9f2f4801dc85e4975278e30dc8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:02:48 +00:00
Kyösti Mälkki
10bdee1327 ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT 
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms'
implementations of adding IOAPIC and IRQ override entries
for ACPI MADT tables.

Platforms that have a more complex MADT may continue to
add custom entries using CUSTOM_ACPI_MADT.

Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 11:02:18 +00:00
Kyösti Mälkki
e742b68f1a arch/x86/ioapic: Promote ioapic_get_sci_pin() 
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.

Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 10:53:16 +00:00
Kyösti Mälkki
ae1b2d49cf soc/intel: Introduce ioapic_get_sci_pin() 
According to ACPI Release 6.5 systems supporting PIC (i8259)
interrupt mechanism need to report IRQ vector for the SCI_INT
field. In PIC mode only IRQ0..15 are allowed hardware vectors.

This change should cover section 5.2.9 to not pass SCI_INT
larger than IRQ15. Section 5.2.15.5 needs follow-up work.

Care should be taken that ioapic_get_sci_pin() is called
after platform code has potentially changed the routing
from the default.

It appears touched all platforms except siemens/mc_aplX
currently program SCI as IRQ9.

Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 10:52:21 +00:00
Kyösti Mälkki
ddc37d69cb ACPI: Add acpigen_write_PTC() 
Change-Id: Ibaf2d7105e7a5da8a50ef32b682978ff55fe31e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 10:51:35 +00:00
Kyösti Mälkki
d48982acac cpu/intel/speedstep: Separate single SSDT CPU entry 
Change-Id: Ibe5d84c8fbff79cc73b01eee0980cbed71ceb506
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2023-04-26 10:51:12 +00:00
Arthur Heymans
9368cf9025 acpi/acpi.c: Reduce scope of some functions 
These functions are only used in one compilation unit.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I6f8282f308506a68b14ce3101f11078cb13709f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74756
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2023-04-26 08:40:14 +00:00
Vesek
323a0ae2b1 Documentation/mainboard/hp: Add more about internal flashing 
Add a more detailed explanation of internal flashing
on the HP Compaq 8200 Elite SFF.

Signed-off-by: Václav Straka <venda.straka@gmail.com>
Change-Id: I53a697a2dd6c10fff8f287284f75d229c7c4b636
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
 2023-04-25 13:02:22 +00:00
Felix Singer
a87da91719 util/docker/jenkins-node: Drop Zephyr SDK 
The version of the Zephyr SDK that is used is quite old and Zephyr
hasn't been really used. Thus, drop it and also its dependencies from
u-boot.

Change-Id: Ie498d687e1566133adf650166117d8f68fcfdaf6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
 2023-04-25 05:36:13 +00:00
Felix Singer
fa41fef557 util/docker/jenkins-node: Allow pip to install packages system-wide 
Call pip3 with `--break-system-packages` allowing it to install packages
system-wide. This fixes building the Docker container.

Change-Id: Id093f2c69fec43556c434fbca7b36095a7e6bd97
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-04-25 05:36:03 +00:00
Felix Singer
98d7157a6d util/docker/jenkins-node: Merge package installations into first step 
It's not necessary to have multiple steps for installing packages and
requirements. Just merge the two install steps to one.

Change-Id: Ibe620e5b20a5f1a5d4e1c4c98942c136f450f280
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74245
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
 2023-04-25 05:35:57 +00:00
Tony Huang
0197ddf20a mb/google/nissa/var/yaviks: Update devicetree for UFC usb port 
USB port 6 connects to a USB front camera, it should always probe.
Remove probe by rear camera fw_config.

BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-04-25 03:50:16 +00:00
Tony Huang
fa945c8b1d mb/google/nissa/var/yavilla: Update devicetree based on FW_CONFIG 
Update devicetree
-Enable USB2 port5 for WWAN
-Update OVTI8856 setting
-Update USB2/3 Type-A 0/1 port location

Probe devicetree based on FW_CONFIG
-pen garage
-rear mipi cam
-USB WWAN

BUG=b:273791621, b:276369170
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I6cc7be2309483ce016bde57db34af078bd4d46b0
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2023-04-25 03:50:13 +00:00
Elyes Haouas
ec8f010a62 Documentation/releases/coreboot-4.20: Add toolchain updates section 
Change-Id: I5fff8b97f6b85165a71aa2a86417f27986fd25fe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
 2023-04-25 01:23:38 +00:00
Jon Murphy
905768b8e2 mb/google/myst: Set system type to laptop 
BUG=b:277294070
TEST=None

Change-Id: I0aa4e0bcfb06e5e5cb7e9d52f2d82b5818925267
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74284
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-04-24 16:05:52 +00:00
Jon Murphy
2c4a4d2cb4 mb/google/myst: Store XHCI PCI resources 
Implement `smm_mainboard_pci_resource_store_init` to store the
resources for XHCI devices. These stored resources are later used by
the elog code to log XHCI wake events.

BUG=b:277273428
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I608d51f438681ac529323c23cc707845a3d609d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74281
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-04-24 16:03:56 +00:00
Jon Murphy
d40cecd00d mb/google/myst: Enable gfx_hda 
Enable gfx_hda to allow for audio over hdmi.

BUG=b:277219546
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I58096f1408f66f968af1494e487cf2bfc43b9a0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74278
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-04-24 15:42:51 +00:00
Jon Murphy
8f3f0cb0e7 mb/google/myst: Enable crypto in devicetree 
Add the crypto device to the devicetree.

BUG=b:277214359
TEST=builds

Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-04-24 15:41:48 +00:00
Kyösti Mälkki
137742225d asus/p2b: Remove MADT LAPIC 
Fix after 'commit 69a13964ea ("sb,soc/amd,intel: Add and use
ACPI_COMMON_MADT_LAPIC")' broke interrupt delivery in kernel.

Apparently combination of LAPIC without IOAPIC is too rare
to be well supported.

Change-Id: I5e2fbf358cf644665b897afb0a9404abb5ca1df2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74472
Reviewed-by: Branden Waldner <scruffy99@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2023-04-24 14:25:18 +00:00
Arthur Heymans
5a24d6491e soc/mediatek/mt8183: Fix set but unused variable 
This fixes a clang warning.

Change-Id: I017ed8601e6ec4c66487e9a6f31e93251515e686
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2023-04-24 13:58:13 +00:00
Arthur Heymans
7277b26f05 vendorcode/mediatek/mt8192: Add or remove brackets 
This fixes clang compilation warnings about logic problems and
superfluous brackets.

Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2023-04-24 13:57:35 +00:00
Arthur Heymans
77b590eed1 soc/mediatek/dptx.c: Remove set but unused variables 
This fixes clang warning about set but unused variables.

Change-Id: I3a3345e33380862d6939b61485f6d1eefa3d1815
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74547
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
 2023-04-24 13:55:25 +00:00
Felix Held
27af3e6b11 include/cpu/amd/mtrr: fix typo in get_top_of_mem_above_4gb 
Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in
line with get_top_of_mem_below_4gb.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
 2023-04-23 21:41:29 +00:00