The patch adds support in the CSE Sub partition update procedure
to use GET_BOOT_PARTITION_INFO HECI command output to create the
region device for CSE RO and CSE RW. The GET_BOOT_PARTITION_INFO
HECI command provides CSE's RO and RW boot partition information.
Existing code relies on FMD file to get the CSE's boot partition's
(CSE RO and CSE RW) start and size details. This change make
independent of FMD file declaration with respect to CSE RO and CSE RW.
TEST=Build and verify the CSE RO and CSE RW region device information
through code instrumentation. Also, did boot test on Kano system.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie9a83b77ab44ea6ffe5bb20673e109a89a148629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
I don't really get around to review super I/O or superiotool patches any
more, so lower the maintenance level of those. If anyone else wants to
step up as new maintainer for those two, feel free to do so.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id7bd3c68c1adc0db82dab078291918742b453d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The FSP needs to program VrPowerDeliverDesign configuration per
platform according to the platform capabilities to avoid incorrect
electrial/power parameters. This value is an enum of the available
power delivery segments that are defined in the Platform Design
Guide.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I74859e6735e59a15084a9e690b43f68341862833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To achieve low power consumption, we disable unused PCIe and SATA
pins at beadrix/overridetree.cb according to baseboard/devicetree.cb
and mainboard schematic. Original measured beadrix board's power
consumption is about 250 mW. After we disable unused PCIe and SATA
pins, as well as, enable the other low power MUX CL (3487086: USB
MUX: Update low power mode of MUX anx7447 used as MUX only |
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/
+/3487086), the measured power consumption achieves about 110 ~ 116
mW, as well as, meets Google battery life for 14 days in the suspend
state and Intel low power consumption about 116 mW.
BRANCH=dedede
BUG=b:204882915
TEST=on beadrix, measured power consumption meets Intel power
consumption.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776
Reviewed-by: Teddy Shih <teddyshihau@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are currently two issues related to the WLAN power sequencing on
nereid:
- If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck
in S3.
- During warm reboot, if we only assert RST without pulling the power
low, then the kernel crashes.
As a workaround while we investigate these issues, we pull the EN high
in S5, then actively drive it low in bootblock and high in romstage to
make sure it goes low during warm reboot.
BUG=b:227694137, b:225261075
TEST=Cold boot succeeds, and there's no kernel crash during warm reboot.
Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
BUG=None
TEST=evtest works:
Select the device event number [0-14]: 9
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153020.275201, -------------- SYN_REPORT ------------
Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153025.848689, -------------- SYN_REPORT ------------
Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153028.383195, -------------- SYN_REPORT ------------
Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153080.869155, -------------- SYN_REPORT ------------
Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Some bytes in the descriptor need to be set differently for Type-C and
HDMI. To allow using a single firmware variant for both cases, update
the descriptor at runtime based on fw_config. This is a temporary
workaround while we find a better solution.
The byte values were determined by changing the following CSE strap and
comparing the generated descriptors:
Type-C: TypeCPort2Config = "No Thunderbolt"
HDMI: TypeCPort2Config = "DP Fixed Connection"
The default value before updating the descriptor is Type-C, but this was
chosen arbitrarily.
BUG=b:226848617
TEST=Type-C and HDMI both work on nereid with fw_config set correctly.
Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
On nereid, we need to update the descriptor based on fw_config (see
the follow-up patch), so add support to update the descriptor at
runtime. This is a temporary workaround while we find a better solution.
This is basically adding back the configure_pmc_descriptor() function
removed in CB:63339, just making it generic and allowing it to update
multiple bytes at once.
BUG=b:226848617
TEST=With the following patch, Type-C and HDMI work on nereid.
Change-Id: I43c4d2888706561e42ff6b8ce0377eedbc38dbfe
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
The patch removes Kconfig CONFIG_ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
code which updates PMC descriptor for an intermediate ADL-P SoC
stepping A0. Since intermediate ADL-P SoC is no longer supported and no
board is selecting the Kconfig, so remove the code that updates PMC
descriptor.
TEST=Build and boot Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a629353a4194a7505655346dcab4ef53059e0b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63339
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch SOC_INTEL_COMMON_BASECODE Kconfig for Comet Lake, Jasper Lake
and Tiger Lake SoCs. It allows access to intelbasecode/debug_feature.h
for Comet Lake, Jasper Lake and Tiger Lake SoCs.
TEST=Build code for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ie55ded673c8fa0edf2ca6789b15771bd2e56c95e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch adds a framework to control coreboot and Intel SoC features
dynamically. BIOS reads control information from OEM Section in the
Descriptor Region and control the developer selected features.
With the feature, debug team can control the selected SoC and coreboot
features without rebuilding coreboot.
In order to enable the feature, SOC_INTEL_COMMON_BLOCK_DEBUG_FEATURE has
to be selcted from mainboard.
The OEM section starts from offset:0xf00 till end of the Descriptor
Region(0xfff).
BUG=b:153410586
BRANCH=None
TEST=Verified CSE firmware update functionality on brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I5ba40926bd9ad909654f152e48cdd648b28afd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Remove the subsystem device ID for HDA devices, so that the correct
Intel [8086:xxxx] is used. This was an old workaround for Windows
that is no longer required with a new driver.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.
Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.
Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This field was never meant to be filled out by coreboot, because it
can't know what the right value for this will be by the time the OS
is running, so anything coreboot could fill in here is premature.
This field is only read by the chromeos-specific `crossystem` utility,
not by kernel code, so if one does not run through depthcharge there'll
be many more broken assumptions in CNVS anyway.
Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This
commit overrides the default SPD files used for these parts
BUG=b:224884904
TEST=Verified that Dewatt SKU1 and SKU3 boot with changes
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This commit adds the ability to override the SPD file that is used for a
specific part.
BUG=b:224884904
TEST=Verified that generated makefile uses specified SPD file and that
it remains unchanged when this capability is not used
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Checking whether a pointer is NULL after it has been dereferenced makes
zero sense. Make sure the `wifi_ssdt_write_properties()` function never
gets invoked with a NULL argument for the `dev` parameter, and simplify
the logic around the `is_cnvi_ddr_rfim_enabled` variable accordingly.
Change-Id: I3fbc9565e7e9b4e1c14a68f6a5fd779577045236
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
IASL reports warning on missing _SRS.
Devices have fixed configuration which is always enabled.
Remove _PRS for this fixed configuration.
BUG=N/A
TEST=built facebook monolith and verify no IASL warning is reported.
Change-Id: I554d3497255c1e50cdbe74b1cffc9f2c59fbae77
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No functional change, just refactoring to make room for CMT variant.
Built with BUILD_TIMELESS=1 and no config included before and after.
$ diff master.rom build/coreboot.rom
$
TESTED: boots to SeaBIOS on HP Z220 SFF
Flashed bios region internally, mainboard also has FDO
(flash descriptor override) jumper that allows r/w to whole flash.
Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
