Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
5) Hynix H58G56BK8BX068
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.
For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.
BUG=b:264704732
TEST=Verified all timings meet spec now
Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Since it actually depends on the SoC type whether the old PSP
directory table pointer or the new comboable PSP directory table
pointer is used in EFS, get this information from the SoC ID instead
of passing the comboable flag for the SoCs that need to use the new
comboable PSP directory table pointer.
TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia
Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add a FMAP region to support caching GOP-driver-modified VBIOS tables.
Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP.
Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP.
BUG=b:255812886
TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS
in CBFS, cached VBIOS data is used when not booting in recovery
or developer modes.
Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch overrides `SkipExtGfxScan` UPD as the Rex device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.
BUG=b:228002764
TEST=Able to save ~1ms+ boot time on google/rex.
FSP FPDT Data is showing the timestamp between those function calls.
Without this patch:
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131
With this patch:
`CheckOffboardPcieVga` is not getting called.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for the selective GOP init feature by only running the FSP
GOP driver when necessary: if the FMAP cache is invalid, or if the
board is booted in either recovery or developer mode.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I7ddadc254e05aca0fdd7a9567160a9329cb0e15c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Write the SHA256 hash of the cached VBIOS data when saving to FMAP,
and use it to validate the data read from FMAP on subsequent boots.
Add TPM2 as a dependency to the selection of VBIOS_CACHE_IN_FMAP.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I9c8f23b000b90a1072aeb7a57d3b7b2b2bc626dc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72402
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add methods to store and retrieve the hash of the data stored in the
VBIOS cache FMAP region. Add a dedicated index in TPM NVRAM to store
the hash, and methods to calculate/read/write it.
Modeled after mrc_cache_hash_tpm.{c,h}
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I030017d3bf956b8593bc09073ad6545b80a5b52b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Make does its work in two distinct phases. The first one basically
initializes and expands all variables, which are not in a recipe and
the second expands all variables inside recipes and then executes the
recipes if necessary.
Currently on some mainboards it can happen that cpu_microcode_bins
variable is filled with microcode paths AFTER swid-files-y is expanded
in the prerequisite for the sbom rule. That causes the
"$(build-dir)/intel-microcode-%.json pattern matching rule not to be
invoked. At the time, when the recipe is executed however (second phase
of make), swid-files-y will now contain the cpu microcode paths from
cpu_microcode_bins. That causes the goswid tooling to fail since the
necessary files were never created, since
"(build-dir)/intel-microcode-%.json" target was never executed.
In order to trigger the expansion of swid-files-y at the second make
phase (after cpu_microcode_bins is fully filled), this patch makes use
of make's secondary expansion feature.
Before on some boards (including samsung/lumpy) the goswid tool
complained about not finding the microcode sbom files.
Test: build samsung/lumpy with CONFIG_SBOM_MICROCODE=y
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I884469a388fd48be89d74ccda686dd8f299d63eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The correct ACPI device for DPTM is TCPU; fixing this puts the
participant devices under the correct parent device, and allows
Windows to properly go into S0ix.
TEST=builb/boot Win11 on google/banshee, verify Si0x functional.
Change-Id: I1b3e2655d4d42e008dead9bc87b73ce02868fdfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Instead of using PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC), use the equivalent
SMBUS_DEVFN define.
Even though the FCH IOAPIC is in the LPC part of the FCH, it needs the
IVRS IOAPIC table's source_dev_id field set to SMBUS_DEVFN which is the
function 0 of the FCH PCI device. LPC is function 3 of the FCH device.
When assigning LPC_DEVFN to source_dev_id, the kernel from Ubuntu
2022.04 LTS complains about the IOAPIC part of the IVRS table being
wrong:
AMD-Vi: [Firmware Bug]: : No southbridge IOAPIC found
AMD-Vi: Disabling interrupt remapping
With SMBUS_DEVFN being used as source_dev_id, no such error is reported.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8470d67b2513031e75fb422d4c1c181e017ace0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE
regions to fit. This requires moving memory addresses around to prevent
overlapping memory linker errors.
TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds
all boards
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Glinda and Phoenix have different requirements, so split the birman FMD
files to better apply to each SoC.
TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds
all boards
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia2dbaeb8af04fb1d1224c397d728929c50800dfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The EFS must be located at the 128K offset. The combination of EC,
MRC_CACHE, and FMAP push the start of the coreboot CBFS region to 128K,
leaving no room for the CBFS headers for the EFS.
Move the MRC_CACHE region to the end of the image. This matches the
chromeos MRC_CACHE layout.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3919fba40f22ee84b0a3eee1ac7b6e48c076d713
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The EFS must be located at the 128K offset. The combination of EC,
MRC_CACHE, and FMAP push the start of the coreboot CBFS region to 128K,
leaving no room for the CBFS headers for the EFS.
Move the MRC_CACHE region to the end of the image. This matches the
chromeos MRC_CACHE layout.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I15e29443d2735342a5a43339f5bb095e5115349c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some of the eDp panels use 6bit color depth as default.
Set the default color depth configuration to 6 bit when there
is no match with the supported color depths.
BUG=b:255870643
TEST=Validated on sc7280 Zombie development board
Change-Id: I2cea10ad417a05f020e4c418f15212fee06a2369
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72744
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
